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123 
	cin0_used => "true",
	cin1_used => "true",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => CLK_acombout,
	dataa => u2_aDOUT_a3_a,
	datab => FWORD_a3_a_acombout,
	aclr => GND,
	cin0 => u2_aDOUT_a2_a_a79,
	cin1 => u2_aDOUT_a2_a_a79COUT1_113,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => u2_aDOUT_a3_a,
	cout0 => u2_aDOUT_a3_a_a83,
	cout1 => u2_aDOUT_a3_a_a83COUT1_114);

u3_aDOUT_a3_a_aI : stratixgx_lcell
-- Equation(s):
-- u3_aDOUT_a3_a = DFFEAS(u2_aDOUT_a3_a, GLOBAL(CLK_acombout), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FF00",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => CLK_acombout,
	datad => u2_aDOUT_a3_a,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => u3_aDOUT_a3_a);

FWORD_a4_a_aI : stratixgx_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_FWORD(4),
	combout => FWORD_a4_a_acombout);

u2_aDOUT_a4_a_aI : stratixgx_lcell
-- Equation(s):
-- u2_aDOUT_a4_a = DFFEAS(u2_aDOUT_a4_a $ FWORD_a4_a_acombout $ !u2_aDOUT_a3_a_a83, GLOBAL(CLK_acombout), VCC, , , , , , )
-- u2_aDOUT_a4_a_a87 = CARRY(u2_aDOUT_a4_a & (FWORD_a4_a_acombout # !u2_aDOUT_a3_a_a83COUT1_114) # !u2_aDOUT_a4_a & FWORD_a4_a_acombout & !u2_aDOUT_a3_a_a83COUT1_114)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	lut_mask => "698E",
	cin0_used => "true",
	cin1_used => "true",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => CLK_acombout,
	dataa => u2_aDOUT_a4_a,
	datab => FWORD_a4_a_acombout,
	aclr => GND,
	cin0 => u2_aDOUT_a3_a_a83,
	cin1 => u2_aDOUT_a3_a_a83COUT1_114,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => u2_aDOUT_a4_a,
	cout => u2_aDOUT_a4_a_a87);

u3_aDOUT_a4_a_aI : stratixgx_lcell
-- Equation(s):
-- u3_aDOUT_a4_a = DFFEAS(GND, GLOBAL(CLK_acombout), VCC, , , u2_aDOUT_a4_a, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0000",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => CLK_acombout,
	datac => u2_aDOUT_a4_a,
	aclr => GND,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => u3_aDOUT_a4_a);

FWORD_a5_a_aI : stratixgx_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_FWORD(5),
	combout => FWORD_a5_a_acombout);

u2_aDOUT_a5_a_aI : stratixgx_lcell
-- Equation(s):
-- u2_aDOUT_a5_a = DFFEAS(FWORD_a5_a_acombout $ u2_aDOUT_a5_a $ u2_aDOUT_a4_a_a87, GLOBAL(CLK_acombout), VCC, , , , , , )
-- u2_aDOUT_a5_a_a91 = CARRY(FWORD_a5_a_acombout & !u2_aDOUT_a5_a & !u2_aDOUT_a4_a_a87 # !FWORD_a5_a_acombout & (!u2_aDOUT_a4_a_a87 # !u2_aDOUT_a5_a))
-- u2_aDOUT_a5_a_a91COUT1_115 = CARRY(FWORD_a5_a_acombout & !u2_aDOUT_a5_a & !u2_aDOUT_a4_a_a87 # !FWORD_a5_a_acombout & (!u2_aDOUT_a4_a_a87 # !u2_aDOUT_a5_a))

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	lut_mask => "9617",
	cin_used => "true",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => CLK_acombout,
	dataa => FWORD_a5_a_acombout,
	datab => u2_aDOUT_a5_a,
	aclr => GND,
	cin => u2_aDOUT_a4_a_a87,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => u2_aDOUT_a5_a,
	cout0 => u2_aDOUT_a5_a_a91,
	cout1 => u2_aDOUT_a5_a_a91COUT1_115);

u3_aDOUT_a5_a_aI : stratixgx_lcell
-- Equation(s):
-- u3_aDOUT_a5_a = DFFEAS(GND, GLOBAL(CLK_acombout), VCC, , , u2_aDOUT_a5_a, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0000",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => CLK_acombout,
	datac => u2_aDOUT_a5_a,
	aclr => GND,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => u3_aDOUT_a5_a);

FWORD_a6_a_aI : stratixgx_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_FWORD(6),
	combout => FWORD_a6_a_acombout);

u2_aDOUT_a6_a_aI : stratixgx_lcell
-- Equation(s):
-- u2_aDOUT_a6_a = DFFEAS(FWORD_a6_a_acombout $ u2_aDOUT_a6_a $ !(!u2_aDOUT_a4_a_a87 & u2_aDOUT_a5_a_a91) # (u2_aDOUT_a4_a_a87 & u2_aDOUT_a5_a_a91COUT1_115), GLOBAL(CLK_acombout), VCC, , , , , , )
-- u2_aDOUT_a6_a_a95 = CARRY(FWORD_a6_a_acombout & (u2_aDOUT_a6_a # !u2_aDOUT_a5_a_a91) # !FWORD_a6_a_acombout & u2_aDOUT_a6_a & !u2_aDOUT_a5_a_a91)
-- u2_aDOUT_a6_a_a95COUT1_116 = CARRY(FWORD_a6_a_acombout & (u2_aDOUT_a6_a # !u2_aDOUT_a5_a_a91COUT1_115) # !FWORD_a6_a_acombout & u2_aDOUT_a6_a & !u2_aDOUT_a5_a_a91COUT1_115)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	lut_mask => "698E",
	cin_used => "true",
	cin0_used => "true",
	cin1_used => "true",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => CLK_acombout,
	dataa => FWORD_a6_a_acombout,
	datab => u2_aDOUT_a6_a,
	aclr => GND,
	cin => u2_aDOUT_a4_a_a87,
	cin0 => u2_aDOUT_a5_a_a91,
	cin1 => u2_aDOUT_a5_a_a91COUT1_115,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => u2_aDOUT_a6_a,
	cout0 => u2_aDOUT_a6_a_a95,
	cout1 => u2_aDOUT_a6_a_a95COUT1_116);

u3_aDOUT_a6_a_aI : stratixgx_lcell
-- Equation(s):
-- u3_aDOUT_a6_a = DFFEAS(GND, GLOBAL(CLK_acombout), VCC, , , u2_aDOUT_a6_a, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0000",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => CLK_acombout,
	datac => u2_aDOUT_a6_a,
	aclr => GND,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => u3_aDOUT_a6_a);

FWORD_a7_a_aI : stratixgx_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_FWORD(7),
	combout => FWORD_a7_a_acombout);

u2_aDOUT_a7_a_aI : stratixgx_lcell
-- Equation(s):
-- u2_aDOUT_a7_a = DFFEAS(u2_aDOUT_a7_a $ FWORD_a7_a_acombout $ (!u2_aDOUT_a4_a_a87 & u2_aDOUT_a6_a_a95) # (u2_aDOUT_a4_a_a87 & u2_aDOUT_a6_a_a95COUT1_116), GLOBAL(CLK_acombout), VCC, , , , , , )
-- u2_aDOUT_a7_a_a99 = CARRY(u2_aDOUT_a7_a & !FWORD_a7_a_acombout & !u2_aDOUT_a6_a_a95 # !u2_aDOUT_a7_a & (!u2_aDOUT_a6_a_a95 # !FWORD_a7_a_acombout))
-- u2_aDOUT_a7_a_a99COUT1_117 = CARRY(u2_aDOUT_a7_a & !FWORD_a7_a_acombout & !u2_aDOUT_a6_a_a95COUT1_116 # !u2_aDOUT_a7_a & (!u2_aDOUT_a6_a_a95COUT1_116 # !FWORD_a7_a_acombout))

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	lut_mask => "9617",
	cin_used => "true",
	cin0_used => "true",
	cin1_used => "true",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => CLK_acombout,
	dataa => u2_aDOUT_a7_a,
	datab => FWORD_a7_a_acombout,
	aclr => GND,
	cin => u2_aDOUT_a4_a_a87,
	cin0 => u2_aDOUT_a6_a_a95,
	cin1 => u2_aDOUT_a6_a_a95COUT1_116,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => u2_aDOUT_a7_a,
	cout0 => u2_aDOUT_a7_a_a99,
	cout1 => u2_aDOUT_a7_a_a99COUT1_117);

u3_aDOUT_a7_a_aI : stratixgx_lcell
-- Equation(s):
-- u3_aDOUT_a7_a = DFFEAS(u2_aDOUT_a7_a, GLOBAL(CLK_acombout), VCC, , , , , , )

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "FF00",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => CLK_acombout,
	datad => u2_aDOUT_a7_a,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => u3_aDOUT_a7_a);

FWORD_a8_a_aI : stratixgx_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_FWORD(8),
	combout => FWORD_a8_a_acombout);

u2_aDOUT_a8_a_aI : stratixgx_lcell
-- Equation(s):
-- u2_aDOUT_a8_a = DFFEAS(u2_aDOUT_a8_a $ FWORD_a8_a_acombout $ !(!u2_aDOUT_a4_a_a87 & u2_aDOUT_a7_a_a99) # (u2_aDOUT_a4_a_a87 & u2_aDOUT_a7_a_a99COUT1_117), GLOBAL(CLK_acombout), VCC, , , , , , )
-- u2_aDOUT_a8_a_a103 = CARRY(u2_aDOUT_a8_a & (FWORD_a8_a_acombout # !u2_aDOUT_a7_a_a99) # !u2_aDOUT_a8_a & FWORD_a8_a_acombout & !u2_aDOUT_a7_a_a99)
-- u2_aDOUT_a8_a_a103COUT1_118 = CARRY(u2_aDOUT_a8_a & (FWORD_a8_a_acombout # !u2_aDOUT_a7_a_a99COUT1_117) # !u2_aDOUT_a8_a & FWORD_a8_a_acombout & !u2_aDOUT_a7_a_a99COUT1_117)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	lut_mask => "698E",
	cin_used => "true",
	cin0_used => "true",
	cin1_used => "true",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => CLK_acombout,
	dataa => u2_aDOUT_a8_a,
	datab => FWORD_a8_a_acombout,
	aclr => GND,
	cin => u2_aDOUT_a4_a_a87,
	cin0 => u2_aDOUT_a7_a_a99,
	cin1 => u2_aDOUT_a7_a_a99COUT1_117,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => u2_aDOUT_a8_a,
	cout0 => u2_aDOUT_a8_a_a103,
	cout1 => u2_aDOUT_a8_a_a103COUT1_118);

u3_aDOUT_a8_a_aI : stratixgx_lcell
-- Equation(s):
-- u3_aDOUT_a8_a = DFFEAS(GND, GLOBAL(CLK_acombout), VCC, , , u2_aDOUT_a8_a, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0000",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => CLK_acombout,
	datac => u2_aDOUT_a8_a,
	aclr => GND,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => u3_aDOUT_a8_a);

FWORD_a9_a_aI : stratixgx_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
123

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