dds.vho

dds实现波形的生成

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic       
-- functions, and any output files any of the foregoing           
-- (including device programming or simulation files), and any    
-- associated documentation or information are expressly subject  
-- to the terms and conditions of the Altera Program License      
-- Subscription Agreement, Altera MegaCore Function License       
-- Agreement, or other applicable license agreement, including,   
-- without limitation, that your use is for the sole purpose of   
-- programming logic devices manufactured by Altera and sold by   
-- Altera or its authorized distributors.  Please refer to the    
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version"

-- DATE "07/26/2006 13:34:55"

-- 
-- Device: Altera EP1SGX40GF1020C5 Package FBGA1020
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, stratixgx;
USE IEEE.std_logic_1164.all;
USE stratixgx.stratixgx_components.all;

ENTITY 	DDS_VHDL IS
    PORT (
	CLK : IN std_logic;
	FWORD : IN std_logic_vector(9 DOWNTO 0);
	FOUT : OUT std_logic_vector(9 DOWNTO 0)
	);
END DDS_VHDL;

ARCHITECTURE structure OF DDS_VHDL IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '0';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_CLK : std_logic;
SIGNAL ww_FWORD : std_logic_vector(9 DOWNTO 0);
SIGNAL ww_FOUT : std_logic_vector(9 DOWNTO 0);
SIGNAL u6_aaltsyncram_component_aauto_generated_aram_block1a0_PORTAADDR_bus : std_logic_vector(9 DOWNTO 0);
SIGNAL u6_aaltsyncram_component_aauto_generated_aram_block1a0_PORTADATAOUT_bus : std_logic_vector(3 DOWNTO 0);
SIGNAL u6_aaltsyncram_component_aauto_generated_aram_block1a1_PORTAADDR_bus : std_logic_vector(9 DOWNTO 0);
SIGNAL u6_aaltsyncram_component_aauto_generated_aram_block1a1_PORTADATAOUT_bus : std_logic_vector(3 DOWNTO 0);
SIGNAL u6_aaltsyncram_component_aauto_generated_aram_block1a3_PORTAADDR_bus : std_logic_vector(9 DOWNTO 0);
SIGNAL u6_aaltsyncram_component_aauto_generated_aram_block1a3_PORTADATAOUT_bus : std_logic_vector(1 DOWNTO 0);
SIGNAL CLK_acombout : std_logic;
SIGNAL FWORD_a0_a_acombout : std_logic;
SIGNAL u2_aDOUT_a0_a : std_logic;
SIGNAL u3_aDOUT_a0_a : std_logic;
SIGNAL FWORD_a1_a_acombout : std_logic;
SIGNAL u2_aDOUT_a0_a_a71 : std_logic;
SIGNAL u2_aDOUT_a0_a_a71COUT1_111 : std_logic;
SIGNAL u2_aDOUT_a1_a : std_logic;
SIGNAL u3_aDOUT_a1_a : std_logic;
SIGNAL FWORD_a2_a_acombout : std_logic;
SIGNAL u2_aDOUT_a1_a_a75 : std_logic;
SIGNAL u2_aDOUT_a1_a_a75COUT1_112 : std_logic;
SIGNAL u2_aDOUT_a2_a : std_logic;
SIGNAL u3_aDOUT_a2_a : std_logic;
SIGNAL FWORD_a3_a_acombout : std_logic;
SIGNAL u2_aDOUT_a2_a_a79 : std_logic;
SIGNAL u2_aDOUT_a2_a_a79COUT1_113 : std_logic;
SIGNAL u2_aDOUT_a3_a : std_logic;
SIGNAL u3_aDOUT_a3_a : std_logic;
SIGNAL FWORD_a4_a_acombout : std_logic;
SIGNAL u2_aDOUT_a3_a_a83 : std_logic;
SIGNAL u2_aDOUT_a3_a_a83COUT1_114 : std_logic;
SIGNAL u2_aDOUT_a4_a : std_logic;
SIGNAL u3_aDOUT_a4_a : std_logic;
SIGNAL FWORD_a5_a_acombout : std_logic;
SIGNAL u2_aDOUT_a4_a_a87 : std_logic;
SIGNAL u2_aDOUT_a5_a : std_logic;
SIGNAL u3_aDOUT_a5_a : std_logic;
SIGNAL FWORD_a6_a_acombout : std_logic;
SIGNAL u2_aDOUT_a5_a_a91 : std_logic;
SIGNAL u2_aDOUT_a5_a_a91COUT1_115 : std_logic;
SIGNAL u2_aDOUT_a6_a : std_logic;
SIGNAL u3_aDOUT_a6_a : std_logic;
SIGNAL FWORD_a7_a_acombout : std_logic;
SIGNAL u2_aDOUT_a6_a_a95 : std_logic;
SIGNAL u2_aDOUT_a6_a_a95COUT1_116 : std_logic;
SIGNAL u2_aDOUT_a7_a : std_logic;
SIGNAL u3_aDOUT_a7_a : std_logic;
SIGNAL FWORD_a8_a_acombout : std_logic;
SIGNAL u2_aDOUT_a7_a_a99 : std_logic;
SIGNAL u2_aDOUT_a7_a_a99COUT1_117 : std_logic;
SIGNAL u2_aDOUT_a8_a : std_logic;
SIGNAL u3_aDOUT_a8_a : std_logic;
SIGNAL FWORD_a9_a_acombout : std_logic;
SIGNAL u2_aDOUT_a8_a_a103 : std_logic;
SIGNAL u2_aDOUT_a8_a_a103COUT1_118 : std_logic;
SIGNAL u2_aDOUT_a9_a : std_logic;
SIGNAL u3_aDOUT_a9_a : std_logic;
SIGNAL u6_aaltsyncram_component_aauto_generated_aq_a_a0_a : std_logic;
SIGNAL u6_aaltsyncram_component_aauto_generated_aq_a_a1_a : std_logic;
SIGNAL u6_aaltsyncram_component_aauto_generated_aq_a_a2_a : std_logic;
SIGNAL u6_aaltsyncram_component_aauto_generated_aq_a_a3_a : std_logic;
SIGNAL u6_aaltsyncram_component_aauto_generated_aq_a_a4_a : std_logic;
SIGNAL u6_aaltsyncram_component_aauto_generated_aq_a_a5_a : std_logic;
SIGNAL u6_aaltsyncram_component_aauto_generated_aq_a_a6_a : std_logic;
SIGNAL u6_aaltsyncram_component_aauto_generated_aq_a_a7_a : std_logic;
SIGNAL u6_aaltsyncram_component_aauto_generated_aq_a_a8_a : std_logic;
SIGNAL u6_aaltsyncram_component_aauto_generated_aq_a_a9_a : std_logic;

BEGIN

ww_CLK <= CLK;
ww_FWORD <= FWORD;
FOUT <= ww_FOUT;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

u6_aaltsyncram_component_aauto_generated_aram_block1a0_PORTAADDR_bus <= (u3_aDOUT_a9_a & u3_aDOUT_a8_a & u3_aDOUT_a7_a & u3_aDOUT_a6_a & u3_aDOUT_a5_a & u3_aDOUT_a4_a & u3_aDOUT_a3_a & u3_aDOUT_a2_a & u3_aDOUT_a1_a & u3_aDOUT_a0_a);

u6_aaltsyncram_component_aauto_generated_aq_a_a0_a <= u6_aaltsyncram_component_aauto_generated_aram_block1a0_PORTADATAOUT_bus(0);
u6_aaltsyncram_component_aauto_generated_aq_a_a5_a <= u6_aaltsyncram_component_aauto_generated_aram_block1a0_PORTADATAOUT_bus(1);
u6_aaltsyncram_component_aauto_generated_aq_a_a7_a <= u6_aaltsyncram_component_aauto_generated_aram_block1a0_PORTADATAOUT_bus(2);
u6_aaltsyncram_component_aauto_generated_aq_a_a9_a <= u6_aaltsyncram_component_aauto_generated_aram_block1a0_PORTADATAOUT_bus(3);

u6_aaltsyncram_component_aauto_generated_aram_block1a1_PORTAADDR_bus <= (u3_aDOUT_a9_a & u3_aDOUT_a8_a & u3_aDOUT_a7_a & u3_aDOUT_a6_a & u3_aDOUT_a5_a & u3_aDOUT_a4_a & u3_aDOUT_a3_a & u3_aDOUT_a2_a & u3_aDOUT_a1_a & u3_aDOUT_a0_a);

u6_aaltsyncram_component_aauto_generated_aq_a_a1_a <= u6_aaltsyncram_component_aauto_generated_aram_block1a1_PORTADATAOUT_bus(0);
u6_aaltsyncram_component_aauto_generated_aq_a_a2_a <= u6_aaltsyncram_component_aauto_generated_aram_block1a1_PORTADATAOUT_bus(1);
u6_aaltsyncram_component_aauto_generated_aq_a_a4_a <= u6_aaltsyncram_component_aauto_generated_aram_block1a1_PORTADATAOUT_bus(2);
u6_aaltsyncram_component_aauto_generated_aq_a_a8_a <= u6_aaltsyncram_component_aauto_generated_aram_block1a1_PORTADATAOUT_bus(3);

u6_aaltsyncram_component_aauto_generated_aram_block1a3_PORTAADDR_bus <= (u3_aDOUT_a9_a & u3_aDOUT_a8_a & u3_aDOUT_a7_a & u3_aDOUT_a6_a & u3_aDOUT_a5_a & u3_aDOUT_a4_a & u3_aDOUT_a3_a & u3_aDOUT_a2_a & u3_aDOUT_a1_a & u3_aDOUT_a0_a);

u6_aaltsyncram_component_aauto_generated_aq_a_a3_a <= u6_aaltsyncram_component_aauto_generated_aram_block1a3_PORTADATAOUT_bus(0);
u6_aaltsyncram_component_aauto_generated_aq_a_a6_a <= u6_aaltsyncram_component_aauto_generated_aram_block1a3_PORTADATAOUT_bus(1);

CLK_aI : stratixgx_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_CLK,
	combout => CLK_acombout);

FWORD_a0_a_aI : stratixgx_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_FWORD(0),
	combout => FWORD_a0_a_acombout);

u2_aDOUT_a0_a_aI : stratixgx_lcell
-- Equation(s):
-- u2_aDOUT_a0_a = DFFEAS(FWORD_a0_a_acombout $ u2_aDOUT_a0_a, GLOBAL(CLK_acombout), VCC, , , , , , )
-- u2_aDOUT_a0_a_a71 = CARRY(FWORD_a0_a_acombout & u2_aDOUT_a0_a)
-- u2_aDOUT_a0_a_a71COUT1_111 = CARRY(FWORD_a0_a_acombout & u2_aDOUT_a0_a)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "6688",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => CLK_acombout,
	dataa => FWORD_a0_a_acombout,
	datab => u2_aDOUT_a0_a,
	aclr => GND,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => u2_aDOUT_a0_a,
	cout0 => u2_aDOUT_a0_a_a71,
	cout1 => u2_aDOUT_a0_a_a71COUT1_111);

u3_aDOUT_a0_a_aI : stratixgx_lcell
-- Equation(s):
-- u3_aDOUT_a0_a = DFFEAS(GND, GLOBAL(CLK_acombout), VCC, , , u2_aDOUT_a0_a, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0000",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => CLK_acombout,
	datac => u2_aDOUT_a0_a,
	aclr => GND,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => u3_aDOUT_a0_a);

FWORD_a1_a_aI : stratixgx_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_FWORD(1),
	combout => FWORD_a1_a_acombout);

u2_aDOUT_a1_a_aI : stratixgx_lcell
-- Equation(s):
-- u2_aDOUT_a1_a = DFFEAS(FWORD_a1_a_acombout $ u2_aDOUT_a1_a $ u2_aDOUT_a0_a_a71, GLOBAL(CLK_acombout), VCC, , , , , , )
-- u2_aDOUT_a1_a_a75 = CARRY(FWORD_a1_a_acombout & !u2_aDOUT_a1_a & !u2_aDOUT_a0_a_a71 # !FWORD_a1_a_acombout & (!u2_aDOUT_a0_a_a71 # !u2_aDOUT_a1_a))
-- u2_aDOUT_a1_a_a75COUT1_112 = CARRY(FWORD_a1_a_acombout & !u2_aDOUT_a1_a & !u2_aDOUT_a0_a_a71COUT1_111 # !FWORD_a1_a_acombout & (!u2_aDOUT_a0_a_a71COUT1_111 # !u2_aDOUT_a1_a))

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	lut_mask => "9617",
	cin0_used => "true",
	cin1_used => "true",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => CLK_acombout,
	dataa => FWORD_a1_a_acombout,
	datab => u2_aDOUT_a1_a,
	aclr => GND,
	cin0 => u2_aDOUT_a0_a_a71,
	cin1 => u2_aDOUT_a0_a_a71COUT1_111,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => u2_aDOUT_a1_a,
	cout0 => u2_aDOUT_a1_a_a75,
	cout1 => u2_aDOUT_a1_a_a75COUT1_112);

u3_aDOUT_a1_a_aI : stratixgx_lcell
-- Equation(s):
-- u3_aDOUT_a1_a = DFFEAS(GND, GLOBAL(CLK_acombout), VCC, , , u2_aDOUT_a1_a, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0000",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => CLK_acombout,
	datac => u2_aDOUT_a1_a,
	aclr => GND,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => u3_aDOUT_a1_a);

FWORD_a2_a_aI : stratixgx_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_FWORD(2),
	combout => FWORD_a2_a_acombout);

u2_aDOUT_a2_a_aI : stratixgx_lcell
-- Equation(s):
-- u2_aDOUT_a2_a = DFFEAS(u2_aDOUT_a2_a $ FWORD_a2_a_acombout $ !u2_aDOUT_a1_a_a75, GLOBAL(CLK_acombout), VCC, , , , , , )
-- u2_aDOUT_a2_a_a79 = CARRY(u2_aDOUT_a2_a & (FWORD_a2_a_acombout # !u2_aDOUT_a1_a_a75) # !u2_aDOUT_a2_a & FWORD_a2_a_acombout & !u2_aDOUT_a1_a_a75)
-- u2_aDOUT_a2_a_a79COUT1_113 = CARRY(u2_aDOUT_a2_a & (FWORD_a2_a_acombout # !u2_aDOUT_a1_a_a75COUT1_112) # !u2_aDOUT_a2_a & FWORD_a2_a_acombout & !u2_aDOUT_a1_a_a75COUT1_112)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	lut_mask => "698E",
	cin0_used => "true",
	cin1_used => "true",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => CLK_acombout,
	dataa => u2_aDOUT_a2_a,
	datab => FWORD_a2_a_acombout,
	aclr => GND,
	cin0 => u2_aDOUT_a1_a_a75,
	cin1 => u2_aDOUT_a1_a_a75COUT1_112,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => u2_aDOUT_a2_a,
	cout0 => u2_aDOUT_a2_a_a79,
	cout1 => u2_aDOUT_a2_a_a79COUT1_113);

u3_aDOUT_a2_a_aI : stratixgx_lcell
-- Equation(s):
-- u3_aDOUT_a2_a = DFFEAS(GND, GLOBAL(CLK_acombout), VCC, , , u2_aDOUT_a2_a, , , VCC)

-- pragma translate_off
GENERIC MAP (
	operation_mode => "normal",
	synch_mode => "on",
	register_cascade_mode => "off",
	sum_lutc_input => "datac",
	lut_mask => "0000",
	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	clk => CLK_acombout,
	datac => u2_aDOUT_a2_a,
	aclr => GND,
	sload => VCC,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	regout => u3_aDOUT_a2_a);

FWORD_a3_a_aI : stratixgx_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input",
	ddio_mode => "none",
	input_register_mode => "none",
	output_register_mode => "none",
	oe_register_mode => "none",
	input_async_reset => "none",
	output_async_reset => "none",
	oe_async_reset => "none",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	devoe => ww_devoe,
	oe => GND,
	padio => ww_FWORD(3),
	combout => FWORD_a3_a_acombout);

u2_aDOUT_a3_a_aI : stratixgx_lcell
-- Equation(s):
-- u2_aDOUT_a3_a = DFFEAS(u2_aDOUT_a3_a $ FWORD_a3_a_acombout $ u2_aDOUT_a2_a_a79, GLOBAL(CLK_acombout), VCC, , , , , , )
-- u2_aDOUT_a3_a_a83 = CARRY(u2_aDOUT_a3_a & !FWORD_a3_a_acombout & !u2_aDOUT_a2_a_a79 # !u2_aDOUT_a3_a & (!u2_aDOUT_a2_a_a79 # !FWORD_a3_a_acombout))
-- u2_aDOUT_a3_a_a83COUT1_114 = CARRY(u2_aDOUT_a3_a & !FWORD_a3_a_acombout & !u2_aDOUT_a2_a_a79COUT1_113 # !u2_aDOUT_a3_a & (!u2_aDOUT_a2_a_a79COUT1_113 # !FWORD_a3_a_acombout))

-- pragma translate_off
GENERIC MAP (
	operation_mode => "arithmetic",
	synch_mode => "off",
	register_cascade_mode => "off",
	sum_lutc_input => "cin",
	lut_mask => "9617",