📄 dds.pin
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.5V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 3.3V
-- Bank 3: 3.3V
-- Bank 4: 3.3V
-- Bank 5: 3.3V
-- Bank 6: 3.3V
-- Bank 7: 3.3V
-- Bank 8: 3.3V
-- Bank 9: 3.3V
-- Bank 10: 3.3V
-- Bank 11: 3.3V
-- Bank 12: 3.3V
-- Bank 13: 3.3V
-- Bank 14: 3.3V
-- Bank 15: 3.3V
-- Bank 16: 3.3V
-- Bank 17: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. This pin can either be left unconnected or
-- connected to GND. Connecting this pin to GND will improve the
-- device's immunity to noise.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- GXB_GND* : Unused GXB Receiver, Transmitter or dedicated reference clock pin. This pin
-- can be left unconnected or connected to GXB_GND through a 10Kohm resistor.
-- Connecting this pin to GXB_GND through a 10Kohm resistor may improve the
-- device's immunity to noise.
-- GXB_VCC* : Unused GXB Receiver, Transmitter or dedicated reference clock pin. This pin
-- can be left unconnected or connected to GXB_VCC through a 10Kohm resistor.
-- Connecting this pin to GXB_VCC through a 10Kohm resistor may improve the
-- device's immunity to noise.
---------------------------------------------------------------------------------
Quartus II Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
CHIP "DDS" ASSIGNED TO AN: EP1SGX40GF1020C5
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
GXB_GND : A2 : : : : :
GXB_GND : A3 : : : : :
GXB_VCC* : A4 : : : 1.5V : 13 :
GXB_GND : A5 : : : : :
GXB_VCC* : A6 : : : 1.5V : 13 :
GXB_GND : A7 : : : : :
GXB_VCC* : A8 : : : 1.5V : 13 :
GXB_GND : A9 : : : : :
GXB_VCC* : A10 : : : 1.5V : 13 :
GXB_GND : A11 : : : : :
GXB_VCC* : A12 : : : 1.5V : 13 :
VCCIO4 : A13 : power : : 3.3V : 4 :
GND* : A14 : : : : 4 :
GND* : A15 : : : : 4 :
VCCIO4 : A16 : power : : 3.3V : 4 :
FWORD[2] : A17 : input : LVTTL : : 10 : N
FOUT[5] : A18 : output : LVTTL : : 3 : N
VCCIO3 : A19 : power : : 3.3V : 3 :
GND : A20 : gnd : : : :
GND* : A21 : : : : 3 :
GND* : A22 : : : : 3 :
GND* : A23 : : : : 3 :
GND* : A24 : : : : 3 :
GND* : A25 : : : : 3 :
GND* : A26 : : : : 3 :
GND* : A27 : : : : 3 :
GND* : A28 : : : : 3 :
GND* : A29 : : : : 3 :
VCCIO3 : A30 : power : : 3.3V : 3 :
GND : A31 : gnd : : : :
GXB_GND : AA1 : : : : :
GXB_GND : AA2 : : : : :
GXB_GND : AA3 : : : : :
GXB_VCC* : AA4 : : : 1.5V : 15 :
GXB_GND* : AA5 : : : : 15 :
VCCA_B15 : AA6 : power : : 3.3V : 15 :
VCCT_B16 : AA7 : power : : 1.5V : 16 :
VCCR_B16 : AA8 : power : : 1.5V : 16 :
VCCP_B16 : AA9 : power : : 1.5V : 16 :
GND* : AA10 : : : : 7 :
GND* : AA11 : : : : 7 :
GND* : AA12 : : : : 7 :
GND* : AA13 : : : : 7 :
GND* : AA14 : : : : 7 :
VCCSEL : AA15 : : : : 7 :
GNDG_PLL12 : AA16 : gnd : : : :
GNDG_PLL6 : AA17 : gnd : : : :
VCC_PLL6_OUTB : AA18 : power : : 3.3V : 12 :
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