dds.tan.rpt
来自「dds实现波形的生成」· RPT 代码 · 共 236 行 · 第 1/5 页
RPT
236 行
; N/A ; 290.87 MHz ( period = 3.438 ns ) ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a0~porta_address_reg9 ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|q_a[0] ; CLK ; CLK ; None ; None ; 2.875 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[8] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a1~porta_address_reg8 ; CLK ; CLK ; None ; None ; 1.600 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[7] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a1~porta_address_reg7 ; CLK ; CLK ; None ; None ; 1.602 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[5] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a3~porta_address_reg5 ; CLK ; CLK ; None ; None ; 1.615 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[8] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a0~porta_address_reg8 ; CLK ; CLK ; None ; None ; 1.588 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[7] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a0~porta_address_reg7 ; CLK ; CLK ; None ; None ; 1.588 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[5] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a0~porta_address_reg5 ; CLK ; CLK ; None ; None ; 1.593 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[2] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a1~porta_address_reg2 ; CLK ; CLK ; None ; None ; 1.568 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[8] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a3~porta_address_reg8 ; CLK ; CLK ; None ; None ; 1.564 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[2] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a3~porta_address_reg2 ; CLK ; CLK ; None ; None ; 1.550 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[2] ; REG10B:u2|DOUT[9] ; CLK ; CLK ; None ; None ; 1.612 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[2] ; REG10B:u2|DOUT[8] ; CLK ; CLK ; None ; None ; 1.612 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[2] ; REG10B:u2|DOUT[7] ; CLK ; CLK ; None ; None ; 1.612 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[2] ; REG10B:u2|DOUT[6] ; CLK ; CLK ; None ; None ; 1.612 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[2] ; REG10B:u2|DOUT[5] ; CLK ; CLK ; None ; None ; 1.612 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[0] ; REG10B:u2|DOUT[9] ; CLK ; CLK ; None ; None ; 1.610 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[0] ; REG10B:u2|DOUT[8] ; CLK ; CLK ; None ; None ; 1.610 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[0] ; REG10B:u2|DOUT[7] ; CLK ; CLK ; None ; None ; 1.610 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[0] ; REG10B:u2|DOUT[6] ; CLK ; CLK ; None ; None ; 1.610 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[0] ; REG10B:u2|DOUT[5] ; CLK ; CLK ; None ; None ; 1.610 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[3] ; REG10B:u2|DOUT[9] ; CLK ; CLK ; None ; None ; 1.547 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[3] ; REG10B:u2|DOUT[8] ; CLK ; CLK ; None ; None ; 1.547 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[3] ; REG10B:u2|DOUT[7] ; CLK ; CLK ; None ; None ; 1.547 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[3] ; REG10B:u2|DOUT[6] ; CLK ; CLK ; None ; None ; 1.547 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[3] ; REG10B:u2|DOUT[5] ; CLK ; CLK ; None ; None ; 1.547 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[1] ; REG10B:u2|DOUT[9] ; CLK ; CLK ; None ; None ; 1.546 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[1] ; REG10B:u2|DOUT[8] ; CLK ; CLK ; None ; None ; 1.546 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[1] ; REG10B:u2|DOUT[7] ; CLK ; CLK ; None ; None ; 1.546 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[1] ; REG10B:u2|DOUT[6] ; CLK ; CLK ; None ; None ; 1.546 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[1] ; REG10B:u2|DOUT[5] ; CLK ; CLK ; None ; None ; 1.546 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[9] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a1~porta_address_reg9 ; CLK ; CLK ; None ; None ; 1.343 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[4] ; REG10B:u2|DOUT[9] ; CLK ; CLK ; None ; None ; 1.506 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[4] ; REG10B:u2|DOUT[8] ; CLK ; CLK ; None ; None ; 1.506 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[4] ; REG10B:u2|DOUT[7] ; CLK ; CLK ; None ; None ; 1.506 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[4] ; REG10B:u2|DOUT[6] ; CLK ; CLK ; None ; None ; 1.506 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u2|DOUT[4] ; REG10B:u2|DOUT[5] ; CLK ; CLK ; None ; None ; 1.506 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[9] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a0~porta_address_reg9 ; CLK ; CLK ; None ; None ; 1.333 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[1] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a1~porta_address_reg1 ; CLK ; CLK ; None ; None ; 1.339 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[6] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a3~porta_address_reg6 ; CLK ; CLK ; None ; None ; 1.345 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[3] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a3~porta_address_reg3 ; CLK ; CLK ; None ; None ; 1.342 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[3] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a1~porta_address_reg3 ; CLK ; CLK ; None ; None ; 1.328 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[6] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a0~porta_address_reg6 ; CLK ; CLK ; None ; None ; 1.334 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[6] ; lpm_rom0:u6|altsyncram:altsyncram_component|altsyncram_obq:auto_generated|ram_block1a1~porta_address_reg6 ; CLK ; CLK ; None ; None ; 1.323 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; REG10B:u3|DOUT[9] ; lpm_rom0:u6|altsyncram:altsync⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?