emhwlib_properties_6000.h

来自「SigmDesign SMP8634 media decode chip dev」· C头文件 代码 · 共 723 行 · 第 1/3 页

/******************************************************/
/* This file is generated automatically, DO NOT EDIT! */
/******************************************************/
/*
 * include/emhwlib_properties_6000.h
 *
 * Copyright (c) 2001-2003 Sigma Designs, Inc. 
 * All Rights Reserved. Proprietary and Confidential.
 *
 */
 
/**
  @file include/emhwlib_properties_6000.h
  @brief emhwlib generated file
   
  @author Jacques Mahe, Christian Wolff, Julien Soulier, Emmanuel Michon
  @ingroup hwlproperties
*/

#ifndef __EMHWLIB_PROPERTIES_6000_H__
#define __EMHWLIB_PROPERTIES_6000_H__

/** Module Enum Default */
enum RMSystemBlockPropertyID {
	RMSystemBlock_unused = 0, 
};

/** Module Enum Default */
enum RMCPUBlockPropertyID {
	RMCPUBlock_unused = 0, 
};

/** Module Enum Default */
enum RMXPUBlockPropertyID {
	RMXPUBlock_unused = 0, 
};

/** Module Enum Default */
enum RMIPUBlockPropertyID {
	RMIPUBlock_unused = 0, 
};

/** Module Enum Default */
enum RMDisplayBlockPropertyID {
	/** DisplayBlock_InitSurface_in_type and DisplayBlock_InitSurface_out_type, (R/W Exchange) @par 
		initialize a static surface */
	RMDisplayBlockPropertyID_InitSurface = 6001,
	/** DisplayBlock_InitMultiplePictureSurface_type, (W) @par 
		initialize a picture fifo surface */
	RMDisplayBlockPropertyID_InitMultiplePictureSurface = 6002,
	/** DisplayBlock_InitMultiplePictureSurfaceX_type, (W) @par 
		initialize a picture fifo surface */
	RMDisplayBlockPropertyID_InitMultiplePictureSurfaceX = 6191,
	/** DisplayBlock_SurfaceInfo_in_type and DisplayBlock_SurfaceInfo_out_type, (R/W Exchange) @par 
		Get the surface fields */
	RMDisplayBlockPropertyID_SurfaceInfo = 6003,
	/** DisplayBlock_PictureInfo_in_type and DisplayBlock_PictureInfo_out_type, (R/W Exchange) @par 
		Get some picture fields */
	RMDisplayBlockPropertyID_PictureInfo = 6183,
	/** DisplayBlock_SurfaceAspectRatio_type, (W) @par 
		initialize a static surface */
	RMDisplayBlockPropertyID_SurfaceAspectRatio = 6004,
	/** DisplayBlock_SurfaceSTC_type, (W) @par 
		Set/Get the STC Module ID attached to a surface */
	RMDisplayBlockPropertyID_SurfaceSTC = 6204,
	/** DisplayBlock_ForcePictureBufferAddress_type, (W) @par 
		force the picture buffer address */
	RMDisplayBlockPropertyID_ForcePictureBufferAddress = 6005,
	/** DisplayBlock_EnableGFXInteraction_type, (W) @par 
		initialize a static surface */
	RMDisplayBlockPropertyID_EnableGFXInteraction = 6006,
	/** DisplayBlock_VBUSBandwidth_type, (R/W) @par 
		@note Used to program the VBUS bandwidth arbiter */
	RMDisplayBlockPropertyID_VBUSBandwidth = 6007,
	/** DisplayBlock_ConnectReader_in_type and DisplayBlock_ConnectReader_out_type, (R/W Exchange) @par 
		Enum Default; */
	RMDisplayBlockPropertyID_ConnectReader = 6197,
	/** ::struct EMhwlibSurfaceReader, (W) @par 
		Enum Default; */
	RMDisplayBlockPropertyID_DisconnectReader = 6198,
};

/** Module Enum Default */
enum RMDispOSDScalerPropertyID {
	/** DispOSDScaler_ScalingConfig_type, (R/W) @par 
		Sets the OSD scaling mode */
	RMDispOSDScalerPropertyID_ScalingConfig = 6014,
};

/** The hardware cursor block generates a small picture to the main mixer block.@n An arbitrary bitmap is stored in 4 bit/pixel format in  a 512x32 on-chip SRAM. Thus no external memory bandwidth is required to support the cursor.@n On chips earlier than SMP8634, each 4-bit pixel is fed to a 16x6x4 lookup table to produce an output stream of 24-bit (6-6-6-6 format) aYcbCr pixels.@note Each video component is multiplied by four, and the akpha value is extended to 8 bits before being sent to the main mixer.@n On SMP8634 and later chips, each 4-bit pixel is fed to a 16x32 look-up table which outputs 32 bit 8888 aYCbCr pixels.@n The horizontal and vertical dimensions of the cursor picture is constrained as follows: @li X size less than or equal to 255 @li Y size less than or equal to 255 */
enum RMDispHardwareCursorPropertyID {
	/** ::RMCursorPix, (W) @par 
		Enum Default; */
	RMDispHardwareCursorPropertyID_Bitmap = 6031,
	/** ::RMCursorLut, (W) @par 
		Enum Default; */
	RMDispHardwareCursorPropertyID_Lut = 6032,
	/** DispHardwareCursor_Size_type, (W) @par 
		Enum Default; */
	RMDispHardwareCursorPropertyID_Size = 6033,
};

/** The main video scaler is similar in general structure to the multi-format scalers with several important differences:\n @li Only video input data formats are supported (no graphics) @li 4-tap H and V-scalers are implemented rather than 2-tap @li A special deinterlacing mode supports vertical scaling using a 2-tap filter combining previous field and current field data @li HD (ITU 709) <-> SD (ITU 601) colorimetry conversion is supported  (both directions).\n\n The main video scaler supports deinterlacing using either of two algorithms, Type 1 and Type 2.\n\n @li In the Type 1 algorithm, output frame N is constructed from both the current (field N) and previous field (field N-1). Each field has  its missing lines reconstructed by a linear interpolation of its neighboring lines. For each output line, the actual (or interpolated) data from field N is combined with the interpolated (or actual) data from field N-1, using the weighted summation: @n @verbatim Lnew = [A* LN-1 + (16 A)* LN] / 16  or Lnew = [B* LN-1 + (16-B)* LN] / 16 @endverbatim where A and B are programmed parameters. Parameter A is used when Lnew exists in the current field (N); parameter B is used when Lnew exists in the previous field (N-1).@li Type 2 deinterlacing uses 3 fields, and is motion-adaptive. Output frame N is built from frame N-1, N, and N+1. Field N-1 and N+1 luma values are compared over 4x2 pixel blocks, resulting in a localized motion detection. Fields N-1 and N are both upscaled, and information from field N-1 is inserted into the output frame depending on how much motion is detected. In other words, the algorithm shifts between inter-field (weave) deinterlacing in regions with little motion, and intra-field (bob) deinterlacing in regions with significant motion.  The Type 2 algorithm supports concurrent deinterlacing and resizing, such as converting 480i input to 720p format. Implementing the Type 2 algorithm involves a coordinated usage of the main video scaler, an available multi-scaler, and the primary mixer block. */
enum RMDispMainVideoScalerPropertyID {
	/** ::enum EMhwlibDeinterlacingMode, (R/W) @par 
		Sets the deinterlacing mode (0,1,2) */
	RMDispMainVideoScalerPropertyID_DeinterlacingMode = 6045,
	/** DispMainVideoScaler_DeinterlacingProportion_type, (R/W) @par 
		Sets the proportion of field N-1 to generate frame N */
	RMDispMainVideoScalerPropertyID_DeinterlacingProportion = 6046,
	/** DispMainVideoScaler_DeinterlacingMotionConfig_type, (R/W) @par 
		Sets the alpha motion modulation function */
	RMDispMainVideoScalerPropertyID_DeinterlacingMotionConfig = 6047,
	/** ::RMuint32, (R/W) @par 
		Sets the scaler id of the scaler needed for motion adaptative deinterlacing */
	RMDispMainVideoScalerPropertyID_DeinterlacingMotionScaler = 6048,
	/** ::RMbool, (R/W) @par 
		Enum Default; */
	RMDispMainVideoScalerPropertyID_Enable_3_2_PullDownDetection = 6049,
	/** DispMainVideoScaler_FilterSelection_type, (R/W) @par 
		Sets the scaling filter selection boundaries */
	RMDispMainVideoScalerPropertyID_FilterSelection = 6050,
};

/** Module Enum Default */
enum RMDispSubPictureScalerPropertyID {
	/** DispSubPictureScaler_ScalingConfig_type, (R/W) @par 
		Sets the SPU scaling mode */
	RMDispSubPictureScalerPropertyID_ScalingConfig = 6053,
};

/** The three multi-format scalers (VCR/CRT/GFX) are general-purpose scaling units which can accept all supported video and graphics data formats (except sub-picture). A 256x32 lookup table in each scaler supports color expansion in 1, 2, 4 and 8 bit/pixel input modes. Due to internal RAM size limitations, these scalers support a maximum of 1024 pixels/line in 32 bit/pixel modes, and a maximum of 2048 pixels/line in 16 (or less) bit/pixel modes. Each scaler processes the video stream in the YC domain, and implements 2-tap H and V-scalers with a scaling range of 0.25 to infinity. Additional downscaling is possible by employing a pre-downscaler before the 2-tap scalers. Each scaler can properly support the differing chrominance sample alignment of MPEG-1 versus MPEG-2. */
enum RMDispVCRMultiScalerPropertyID {
	RMDispVCRMultiScaler_unused = 0, 
};

/** The three multi-format scalers (VCR/CRT/GFX) are general-purpose scaling units which can accept all supported video and graphics data formats (except sub-picture). A 256x32 lookup table in each scaler supports color expansion in 1, 2, 4 and 8 bit/pixel input modes. Due to internal RAM size limitations, these scalers support a maximum of 1024 pixels/line in 32 bit/pixel modes, and a maximum of 2048 pixels/line in 16 (or less) bit/pixel modes. Each scaler processes the video stream in the YC domain, and implements 2-tap H and V-scalers with a scaling range of 0.25 to infinity. Additional downscaling is possible by employing a pre-downscaler before the 2-tap scalers. Each scaler can properly support the differing chrominance sample alignment of MPEG-1 versus MPEG-2. */
enum RMDispCRTMultiScalerPropertyID {
	RMDispCRTMultiScaler_unused = 0, 
};

/** The three multi-format scalers (VCR/CRT/GFX) are general-purpose scaling units which can accept all supported video and graphics data formats (except sub-picture). A 256x32 lookup table in each scaler supports color expansion in 1, 2, 4 and 8 bit/pixel input modes. Due to internal RAM size limitations, these scalers support a maximum of 1024 pixels/line in 32 bit/pixel modes, and a maximum of 2048 pixels/line in 16 (or less) bit/pixel modes. Each scaler processes the video stream in the YC domain, and implements 2-tap H and V-scalers with a scaling range of 0.25 to infinity. Additional downscaling is possible by employing a pre-downscaler before the 2-tap scalers. Each scaler can properly support the differing chrominance sample alignment of MPEG-1 versus MPEG-2. */
enum RMDispGFXMultiScalerPropertyID {
	RMDispGFXMultiScaler_unused = 0, 
};

/** The main mixer receives the picture streams from each of the eight sources.@n @image html DispMainMixer_Block.png "Main Mixer" @n Each incoming stream passes through a positioning block, which places the input picture at a specified horizontal and vertical position within the active display window. Within the mixer, the positioned streams are then sorted according to a programmable ordering. The highest priority (top layer) is always assigned to the hardware cursor. For each pixel, layer 5 is alpha-blended with layer 4, layer 6 is alpha-blended with the result, and layer 7 is alpha-blended to form the output pixel. If any pixel is transparent, the sort moves down the layer order until a non-transparent pixel is found. Thus the output pixel stream consists of the merged combination of the four highest priority non-transparent layers. The output of the main mixer is sent to the display routing block. @image html DispMainMixer_Position.png Position Block */
enum RMDispMainMixerPropertyID {
	/** DispMainMixer_LayerOrder_type, (R/W) @par 
		@note Only a maximum of 4 planes can be blended per pixel. A transparent pixel is not considered as alpha blended.@note Layer 7 is reserved for the Hardware Cursor */
	RMDispMainMixerPropertyID_LayerOrder = 6056,
};

/** Module Enum Default */
enum RMDispVCRMixerPropertyID {
	/** DispVCRMixer_LayerOrder_type, (R/W) @par 
		@note Only a maximum of 4 planes can be blended per pixel. A transparent pixel is not considered as alpha blended.@note Layer 7 is reserved for the Hardware Cursor */
	RMDispVCRMixerPropertyID_LayerOrder = 6065,
};

/** Module Enum Default */
enum RMDispColorBarsPropertyID {
	/** ::RMuint32, (R/W) @par 
		Enum Default; */
	RMDispColorBarsPropertyID_Intensity = 6066,
	/** ::enum EMhwlibColorBarsStandard, (R/W) @par 
		Enum Default; */
	RMDispColorBarsPropertyID_Standard = 6067,
};

/** Module Enum Default */
enum RMDispRoutingPropertyID {
	RMDispRouting_unused = 0, 
};

/** Module Enum Default */
enum RMDispVideoInputPropertyID {
	/** ::RMuint32, (R/W) @par 
		Number of bits (8 or 16) on the video input. */
	RMDispVideoInputPropertyID_BusSize = 6069,
	/** DispVideoInput_InputFormat_type, (R/W) @par 
		Enum Default; */
	RMDispVideoInputPropertyID_InputFormat = 6070,
};

/** Module Enum Default */
enum RMDispGraphicInputPropertyID {
	/** DispGraphicInput_InputFormat_type, (R/W) @par 
		Subset for video input. For all features of graphics input, use Format property. */
	RMDispGraphicInputPropertyID_InputFormat = 6079,
	/** DispGraphicInput_OutputFormat_type, (R/W) @par 
		Specifies the output surface characteristics */
	RMDispGraphicInputPropertyID_OutputFormat = 6080,
	/** DispGraphicInput_KeyColor_type, (R/W) @par 
		Enum Default; */
	RMDispGraphicInputPropertyID_KeyColor = 6081,
	/** ::RMuint32, (R/W) @par 
		Routing source of the H- and V-Sync outputs. @note Allowed module IDs: @li DispGraphicInput @li DispDigitalOut @li DispMainAnalogOut @li DispComponentOut @li DispCompositeOut */
	RMDispGraphicInputPropertyID_SyncControlModuleID = 6082,
};

/** Module Enum Default */
enum RMDispDigitalOutPropertyID {
	/** ::enum EMhwlibDigitalTimingSignal, (R/W) @par 
		Enable CCIR 656 embedded sync signals. */
	RMDispDigitalOutPropertyID_TimingSignal = 6083,
	/** ::RMbool, (R/W) @par 
		Luma or RGB components are clipped between 16 and 235, chroma is clipped from 16 to 240, if active. */
	RMDispDigitalOutPropertyID_EnableClipping = 6084,
	/** DispDigitalOut_ClippingLevel_enum, (R/W) @par 
		Luma or RGB components are clipped between 16 and 235, chroma is clipped from 16 to 240, if active. */
	RMDispDigitalOutPropertyID_ClippingLevel = 6085,
	/** ::RMuint32, (R/W) @par 
		Number of bits (8, 16 or 24) on the digital output. */
	RMDispDigitalOutPropertyID_BusSize = 6086,
	/** ::RMbool, (R/W) @par 
		Define the YUV format following MPEG2 (0) specification or MPEG1 (1) specification */
	RMDispDigitalOutPropertyID_EnableMPEG1Chroma = 6087,
	/** ::enum EMhwlibColorOrder, (R/W) @par 
		Specify the order of the digital data to: @li 24 bit R-G-B (0) or R-B-G (1) @li 24 bit Cr-Y-Cb (0) or Cr-Cb-Y (1) @li 16 bit Y-CbCr (0) CbCr-Y (1) */
	RMDispDigitalOutPropertyID_ColorOrder = 6088,
	/** ::RMbool, (R/W) @par 
		Sets the DoubleRate feature of EM863x. If TRUE, each pixel will be sent twice, doubling the pixel clock and all horizontal timing values at the digital output pads. */
	RMDispDigitalOutPropertyID_DoubleRate = 6089,
	/** ::RMbool, (R/W) @par 
		If TRUE, Delays VSYNC by one pixel clock. */
	RMDispDigitalOutPropertyID_VSyncDelay1PixClk = 6184,
	/** ::RMbool, (R/W) @par 
		If TRUE, sets the field ID logic on the HSync trailing edge. */
	RMDispDigitalOutPropertyID_TrailingEdge = 6185,
	/** ::RMuint32, (R/W) @par 
		Routing source of the H- and V-Sync outputs. @note Allowed module IDs: @li DispDigitalOut @li DispMainAnalogOut @li DispComponentOut */
	RMDispDigitalOutPropertyID_SyncControlModuleID = 6090,
	/** ::RMbool, (R/W) @par 
		enables the data pad. */
	RMDispDigitalOutPropertyID_EnableDataPAD = 6091,
	/** ::RMbool, (R/W) @par 
		enables the sync pad. */
	RMDispDigitalOutPropertyID_EnableSyncPAD = 6092,
	/** ::RMbool, (R/W) @par 
		enables the vvld pad. */