msp430f2618.ddf

ZigBee Pro协议栈。该协议栈是基于CC2520+MSP430F2618.

;;/**************************************************
;; * Definitions of I/O register description file,
;; * interrupt/exception vectors, interrupt control registers,
;; * I/O register reset values. 
;; *
;; * Copyright 2001-2007 IAR Systems. All rights reserved.
;; *
;; * $ $
;; *
;; **************************************************/


;; Memory information ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; 
;; Used to define address zones within the MSP430 address space (Memory). 
;;
;;   Name      may be almost anything
;;   AdrSpace  must be Memory
;;   StartAdr  start of memory block
;;   EndAdr    end of memory block
;;   AccType   type of access, read-only (R) or read-write (RW)

[Memory]
;;         Name             AdrSpace    StartAdr    EndAdr    AccType
Memory0  = SFR              Memory      0x0000      0x01FF      RW
Memory1  = RAM              Memory      0x1100      0x30FF      RW
Memory2  = INFO             Memory      0x1000      0x10FF      R
Memory3  = FLASH            Memory      0x3100      0x1FFFF     RW


;; I/O Register description file ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

[SfrInclude]
File = MSP430F2618.sfr

;; Interrupt definitions ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
[InterruptList]
;              Id                      Table Adr     Prio    Enable                  Pending
Interrupt0   = DAC12_VECTOR            0x1C          2       DAC12_0CTL.DAC12IE      DAC12_0CTL.DAC12IFG
Interrupt1   = DMA_VECTOR	       0x1E          2       DMA0CTL.DMAIE	     DMA0CTL.DMAIFG
Interrupt2   = USCI1TX_VECTOR          0x20          2       UC1IE.UCA1TXIE          IFG2.UCA0TXIFG
Interrupt3   = USCI1RX_VECTOR          0x22          2       UC1IE.UCA1RXIE          IFG2.UCA0RXIFG
Interrupt4   = PORT1_VECTOR            0x24          2       P1IE.P0                 P1IFG.P0
Interrupt5   = PORT1_VECTOR            0x24          2       P1IE.P1                 P1IFG.P1
Interrupt6   = PORT1_VECTOR            0x24          2       P1IE.P2                 P1IFG.P2
Interrupt7   = PORT1_VECTOR            0x24          2       P1IE.P3                 P1IFG.P3
Interrupt8   = PORT1_VECTOR            0x24          2       P1IE.P4                 P1IFG.P4
Interrupt9   = PORT1_VECTOR            0x24          2       P1IE.P5                 P1IFG.P5
Interrupt10  = PORT1_VECTOR            0x24          2       P1IE.P6                 P1IFG.P6
Interrupt11  = PORT1_VECTOR            0x24          2       P1IE.P7                 P1IFG.P7
Interrupt12  = PORT2_VECTOR            0x26          2       P2IE.P0                 P2IFG.P0
Interrupt13  = PORT2_VECTOR            0x26          2       P2IE.P1                 P2IFG.P1
Interrupt14  = PORT2_VECTOR            0x26          2       P2IE.P2                 P2IFG.P2
Interrupt15  = PORT2_VECTOR            0x26          2       P2IE.P3                 P2IFG.P3
Interrupt16  = PORT2_VECTOR            0x26          2       P2IE.P4                 P2IFG.P4
Interrupt17  = PORT2_VECTOR            0x26          2       P2IE.P5                 P2IFG.P5
Interrupt18  = PORT2_VECTOR            0x26          2       P2IE.P6                 P2IFG.P6
Interrupt19  = PORT2_VECTOR            0x26          2       P2IE.P7                 P2IFG.P7
Interrupt20  = ADC12_VECTOR            0x2A          2       ADC12IE                 ADC12IFG
Interrupt21  = USCITX_VECTOR           0x2C          2       IE2.UCA0TXIE            IFG2.UCA0TXIFG
Interrupt22  = USCIRX_VECTOR           0x2E          2       IE2.UCA0RXIE            IFG2.UCA0RXIFG
Interrupt23  = TIMERA1_TACCR1_VECTOR   0x30          2       TACCTL1.CCIE            TACCTL1.CCIFG
Interrupt24  = TIMERA1_TACCR2_VECTOR   0x30          2       TACCTL2.CCIE            TACCTL2.CCIFG
Interrupt25  = TIMERA1_TAR_VECTOR      0x30          2       TACTL.TAIE              TACTL.TAIFG
Interrupt26  = TIMERA0_VECTOR          0x32          2       TACCTL0.CCIE            TACCTL0.CCIFG
Interrupt27  = WDT_VECTOR              0x34          2       IE1.WDTIE               IFG1.WDTIFG
Interrupt28  = COMPARATORA_VECTOR      0x36          2       CACTL1.CAIE             CACTL1.CAIFG
Interrupt29  = TIMERB1_TBCCR1_VECTOR   0x38          2       TBCCTL1.CCIE            TBCCTL1.CCIFG
Interrupt30  = TIMERB1_TBCCR2_VECTOR   0x38          2       TBCCTL2.CCIE            TBCCTL2.CCIFG
Interrupt31  = TIMERB1_TBCCR3_VECTOR   0x38          2       TBCCTL3.CCIE            TBCCTL1.CCIFG
Interrupt32  = TIMERB1_TBCCR4_VECTOR   0x38          2       TBCCTL4.CCIE            TBCCTL1.CCIFG
Interrupt33  = TIMERB1_TBCCR5_VECTOR   0x38          2       TBCCTL5.CCIE            TBCCTL1.CCIFG
Interrupt34  = TIMERB1_TBCCR6_VECTOR   0x38          2       TBCCTL6.CCIE            TBCCTL1.CCIFG
Interrupt35  = TIMERB1_TBR_VECTOR      0x38          2       TBCTL.TBIE              TBCTL.TBIFG
Interrupt36  = TIMERB0_VECTOR          0x3A          2       TBCCTL0.CCIE            TBCCTL0.CCIFG
Interrupt37  = NMI_VECTOR              0x3C          2       IE1.NMIIE               IFG1.NMIIFG
Interrupt38  = RESET_VECTOR            0x3E          1
      
      
;; End of file