📄 iolpc2148.h
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#define FIO0MASK2 FIO0MASK_bit.__byte2
#define FIO0MASK2_bit FIO0MASK_bit.__byte2_bit
#define FIO0MASK3 FIO0MASK_bit.__byte3
#define FIO0MASK3_bit FIO0MASK_bit.__byte3_bit
#define FIO0MASKL FIO0MASK_bit.__shortl
#define FIO0MASKL_bit FIO0MASK_bit.__shortl_bit
#define FIO0MASKU FIO0MASK_bit.__shortu
#define FIO0MASKU_bit FIO0MASK_bit.__shortu_bit
__IO_REG32_BIT(FIO0PIN, 0x3FFFC014,__READ_WRITE,__fgpio0_bits);
#define FIO0PIN0 FIO0PIN_bit.__byte0
#define FIO0PIN0_bit FIO0PIN_bit.__byte0_bit
#define FIO0PIN1 FIO0PIN_bit.__byte1
#define FIO0PIN1_bit FIO0PIN_bit.__byte1_bit
#define FIO0PIN2 FIO0PIN_bit.__byte2
#define FIO0PIN2_bit FIO0PIN_bit.__byte2_bit
#define FIO0PIN3 FIO0PIN_bit.__byte3
#define FIO0PIN3_bit FIO0PIN_bit.__byte3_bit
#define FIO0PINL FIO0PIN_bit.__shortl
#define FIO0PINL_bit FIO0PIN_bit.__shortl_bit
#define FIO0PINU FIO0PIN_bit.__shortu
#define FIO0PINU_bit FIO0PIN_bit.__shortu_bit
__IO_REG32_BIT(FIO0SET, 0x3FFFC018,__READ_WRITE,__fgpio0_bits);
#define FIO0SET0 FIO0SET_bit.__byte0
#define FIO0SET0_bit FIO0SET_bit.__byte0_bit
#define FIO0SET1 FIO0SET_bit.__byte1
#define FIO0SET1_bit FIO0SET_bit.__byte1_bit
#define FIO0SET2 FIO0SET_bit.__byte2
#define FIO0SET2_bit FIO0SET_bit.__byte2_bit
#define FIO0SET3 FIO0SET_bit.__byte3
#define FIO0SET3_bit FIO0SET_bit.__byte3_bit
#define FIO0SETL FIO0SET_bit.__shortl
#define FIO0SETL_bit FIO0SET_bit.__shortl_bit
#define FIO0SETU FIO0SET_bit.__shortu
#define FIO0SETU_bit FIO0SET_bit.__shortu_bit
__IO_REG32_BIT(FIO0CLR, 0x3FFFC01C,__WRITE ,__fgpio0_bits);
#define FIO0CLR0 FIO0CLR_bit.__byte0
#define FIO0CLR0_bit FIO0CLR_bit.__byte0_bit
#define FIO0CLR1 FIO0CLR_bit.__byte1
#define FIO0CLR1_bit FIO0CLR_bit.__byte1_bit
#define FIO0CLR2 FIO0CLR_bit.__byte2
#define FIO0CLR2_bit FIO0CLR_bit.__byte2_bit
#define FIO0CLR3 FIO0CLR_bit.__byte3
#define FIO0CLR3_bit FIO0CLR_bit.__byte3_bit
#define FIO0CLRL FIO0CLR_bit.__shortl
#define FIO0CLRL_bit FIO0CLR_bit.__shortl_bit
#define FIO0CLRU FIO0CLR_bit.__shortu
#define FIO0CLRU_bit FIO0CLR_bit.__shortu_bit
__IO_REG32_BIT(IO1PIN, 0xE0028010,__READ_WRITE,__gpio1_bits);
__IO_REG32_BIT(IO1SET, 0xE0028014,__READ_WRITE,__gpio1_bits);
__IO_REG32_BIT(IO1DIR, 0xE0028018,__READ_WRITE,__gpio1_bits);
__IO_REG32_BIT(IO1CLR, 0xE002801C,__WRITE ,__gpio1_bits);
__IO_REG32_BIT(FIO1DIR, 0x3FFFC020,__READ_WRITE,__fgpio1_bits);
#define FIO1DIR0 FIO1DIR_bit.__byte0
#define FIO1DIR0_bit FIO1DIR_bit.__byte0_bit
#define FIO1DIR1 FIO1DIR_bit.__byte1
#define FIO1DIR1_bit FIO1DIR_bit.__byte1_bit
#define FIO1DIR2 FIO1DIR_bit.__byte2
#define FIO1DIR2_bit FIO1DIR_bit.__byte2_bit
#define FIO1DIR3 FIO1DIR_bit.__byte3
#define FIO1DIR3_bit FIO1DIR_bit.__byte3_bit
#define FIO1DIRL FIO1DIR_bit.__shortl
#define FIO1DIRL_bit FIO1DIR_bit.__shortl_bit
#define FIO1DIRU FIO1DIR_bit.__shortu
#define FIO1DIRU_bit FIO1DIR_bit.__shortu_bit
__IO_REG32_BIT(FIO1MASK, 0x3FFFC030,__READ_WRITE,__fgpio1_bits);
#define FIO1MASK0 FIO1MASK_bit.__byte0
#define FIO1MASK0_bit FIO1MASK_bit.__byte0_bit
#define FIO1MASK1 FIO1MASK_bit.__byte1
#define FIO1MASK1_bit FIO1MASK_bit.__byte1_bit
#define FIO1MASK2 FIO1MASK_bit.__byte2
#define FIO1MASK2_bit FIO1MASK_bit.__byte2_bit
#define FIO1MASK3 FIO1MASK_bit.__byte3
#define FIO1MASK3_bit FIO1MASK_bit.__byte3_bit
#define FIO1MASKL FIO1MASK_bit.__shortl
#define FIO1MASKL_bit FIO1MASK_bit.__shortl_bit
#define FIO1MASKU FIO1MASK_bit.__shortu
#define FIO1MASKU_bit FIO1MASK_bit.__shortu_bit
__IO_REG32_BIT(FIO1PIN, 0x3FFFC034,__READ_WRITE,__fgpio1_bits);
#define FIO1PIN0 FIO1PIN_bit.__byte0
#define FIO1PIN0_bit FIO1PIN_bit.__byte0_bit
#define FIO1PIN1 FIO1PIN_bit.__byte1
#define FIO1PIN1_bit FIO1PIN_bit.__byte1_bit
#define FIO1PIN2 FIO1PIN_bit.__byte2
#define FIO1PIN2_bit FIO1PIN_bit.__byte2_bit
#define FIO1PIN3 FIO1PIN_bit.__byte3
#define FIO1PIN3_bit FIO1PIN_bit.__byte3_bit
#define FIO1PINL FIO1PIN_bit.__shortl
#define FIO1PINL_bit FIO1PIN_bit.__shortl_bit
#define FIO1PINU FIO1PIN_bit.__shortu
#define FIO1PINU_bit FIO1PIN_bit.__shortu_bit
__IO_REG32_BIT(FIO1SET, 0x3FFFC038,__READ_WRITE,__fgpio1_bits);
#define FIO1SET0 FIO1SET_bit.__byte0
#define FIO1SET0_bit FIO1SET_bit.__byte0_bit
#define FIO1SET1 FIO1SET_bit.__byte1
#define FIO1SET1_bit FIO1SET_bit.__byte1_bit
#define FIO1SET2 FIO1SET_bit.__byte2
#define FIO1SET2_bit FIO1SET_bit.__byte2_bit
#define FIO1SET3 FIO1SET_bit.__byte3
#define FIO1SET3_bit FIO1SET_bit.__byte3_bit
#define FIO1SETL FIO1SET_bit.__shortl
#define FIO1SETL_bit FIO1SET_bit.__shortl_bit
#define FIO1SETU FIO1SET_bit.__shortu
#define FIO1SETU_bit FIO1SET_bit.__shortu_bit
__IO_REG32_BIT(FIO1CLR, 0x3FFFC03C,__WRITE ,__fgpio1_bits);
#define FIO1CLR0 FIO1CLR_bit.__byte0
#define FIO1CLR0_bit FIO1CLR_bit.__byte0_bit
#define FIO1CLR1 FIO1CLR_bit.__byte1
#define FIO1CLR1_bit FIO1CLR_bit.__byte1_bit
#define FIO1CLR2 FIO1CLR_bit.__byte2
#define FIO1CLR2_bit FIO1CLR_bit.__byte2_bit
#define FIO1CLR3 FIO1CLR_bit.__byte3
#define FIO1CLR3_bit FIO1CLR_bit.__byte3_bit
#define FIO1CLRL FIO1CLR_bit.__shortl
#define FIO1CLRL_bit FIO1CLR_bit.__shortl_bit
#define FIO1CLRU FIO1CLR_bit.__shortu
#define FIO1CLRU_bit FIO1CLR_bit.__shortu_bit
/***************************************************************************
**
** UART0
**
***************************************************************************/
/* U0DLL, U0RBR and U0THR share the same address */
__IO_REG8( U0RBRTHR, 0xE000C000,__READ_WRITE);
#define U0DLL U0RBRTHR
#define U0RBR U0RBRTHR
#define U0THR U0RBRTHR
/* U0DLM and U0IER share the same address */
__IO_REG32_BIT(U0IER, 0xE000C004,__READ_WRITE,__uartier0_bits);
#define U0DLM U0IER
/* U0FCR and U0IIR share the same address */
__IO_REG32_BIT(U0FCR, 0xE000C008,__READ_WRITE,__uartfcriir_bits);
#define U0IIR U0FCR
#define U0IIR_bit U0FCR_bit
__IO_REG8_BIT( U0LCR, 0xE000C00C,__READ_WRITE,__uartlcr_bits);
__IO_REG8_BIT( U0LSR, 0xE000C014,__READ ,__uartlsr_bits);
__IO_REG8( U0SCR, 0xE000C01C,__READ_WRITE);
__IO_REG8_BIT( U0FDR, 0xE000C028,__READ_WRITE,__uartfdr_bits);
__IO_REG8_BIT( U0TER, 0xE000C030,__READ_WRITE,__uartter_bits);
/***************************************************************************
**
** UART1
**
***************************************************************************/
/* U1DLL, U1RBR and U1THR share the same address */
__IO_REG8( U1RBRTHR, 0xE0010000,__READ_WRITE);
#define U1DLL U1RBRTHR
#define U1RBR U1RBRTHR
#define U1THR U1RBRTHR
/* U1DLM and U1IER share the same address */
__IO_REG32_BIT(U1IER, 0xE0010004,__READ_WRITE,__uartier1_bits);
#define U1DLM U1IER
/* U1FCR and U1IIR share the same address */
__IO_REG32_BIT(U1FCR, 0xE0010008,__READ_WRITE,__uartfcriir_bits);
#define U1IIR U1FCR
#define U1IIR_bit U1FCR_bit
__IO_REG8_BIT( U1LCR, 0xE001000C,__READ_WRITE,__uartlcr_bits);
__IO_REG8_BIT( U1MCR, 0xE0010010,__READ_WRITE,__uartmcr_bits);
__IO_REG8_BIT( U1LSR, 0xE0010014,__READ ,__uartlsr_bits);
__IO_REG8_BIT( U1MSR, 0xE0010018,__READ_WRITE,__uartmsr_bits);
__IO_REG8( U1SCR, 0xE001001C,__READ_WRITE);
__IO_REG32_BIT(U1ACR, 0xE0010020,__READ_WRITE,__uartacr_bits);
__IO_REG8_BIT( U1FDR, 0xE0010028,__READ_WRITE,__uartfdr_bits);
__IO_REG8_BIT( U1TER, 0xE0010030,__READ_WRITE,__uartter_bits);
/***************************************************************************
**
** I2C
**
***************************************************************************/
__IO_REG32_BIT(I2C0CONSET, 0xE001C000,__READ_WRITE,__i2conset_bits);
__IO_REG32_BIT(I2C0STAT, 0xE001C004,__READ ,__i2stat_bits);
__IO_REG32_BIT(I2C0DAT, 0xE001C008,__READ_WRITE,__i2dat_bits);
__IO_REG32_BIT(I2C0ADR, 0xE001C00C,__READ_WRITE,__i2adr_bits);
__IO_REG32_BIT(I2C0SCLH, 0xE001C010,__READ_WRITE,__i2scl_bits);
__IO_REG32_BIT(I2C0SCLL, 0xE001C014,__READ_WRITE,__i2scl_bits);
__IO_REG32_BIT(I2C0CONCLR, 0xE001C018,__WRITE ,__i2conclr_bits);
__IO_REG32_BIT(I2C1CONSET, 0xE005C000,__READ_WRITE,__i2conset_bits);
__IO_REG32_BIT(I2C1STAT, 0xE005C004,__READ ,__i2stat_bits);
__IO_REG32_BIT(I2C1DAT, 0xE005C008,__READ_WRITE,__i2dat_bits);
__IO_REG32_BIT(I2C1ADR, 0xE005C00C,__READ_WRITE,__i2adr_bits);
__IO_REG32_BIT(I2C1SCLH, 0xE005C010,__READ_WRITE,__i2scl_bits);
__IO_REG32_BIT(I2C1SCLL, 0xE005C014,__READ_WRITE,__i2scl_bits);
__IO_REG32_BIT(I2C1CONCLR, 0xE005C018,__WRITE ,__i2conclr_bits);
//The names of the registers above have been corrected according to the chip
//documentation. The defines below are aliases with the old names for backwards
//compatibility.
#define I20CONSET I2C0CONSET
#define I20STAT I2C0STAT
#define I20DAT I2C0DAT
#define I20ADR I2C0ADR
#define I20SCLH I2C0SCLH
#define I20SCLL I2C0SCLL
#define I20CONCLR I2C0CONCLR
#define I21CONSET I2C1CONSET
#define I21STAT I2C1STAT
#define I21DAT I2C1DAT
#define I21ADR I2C1ADR
#define I21SCLH I2C1SCLH
#define I21SCLL I2C1SCLL
#define I21CONCLR I2C1CONCLR
/***************************************************************************
**
** SPI
**
***************************************************************************/
__IO_REG32_BIT(S0SPCR, 0xE0020000,__READ_WRITE,__spcr_bits);
__IO_REG32_BIT(S0SPSR, 0xE0020004,__READ ,__spsr_bits);
__IO_REG32_BIT(S0SPDR, 0xE0020008,__READ_WRITE,__spdr_bits);
__IO_REG32_BIT(S0SPCCR, 0xE002000C,__READ_WRITE,__spccr_bits);
__IO_REG32_BIT(S0SPINT, 0xE002001C,__READ_WRITE,__spint_bits);
/***************************************************************************
**
** SSP
**
***************************************************************************/
__IO_REG32_BIT(SSPCR0, 0xE0068000,__READ_WRITE,__sspcr0_bits);
__IO_REG32_BIT(SSPCR1, 0xE0068004,__READ_WRITE,__sspcr1_bits);
__IO_REG32_BIT(SSPDR, 0xE0068008,__READ_WRITE,__sspdr_bits);
__IO_REG32_BIT(SSPSR, 0xE006800C,__READ ,__sspsr_bits);
__IO_REG32_BIT(SSPCPSR, 0xE0068010,__READ_WRITE,__sspcpsr_bits);
__IO_REG32_BIT(SSPIMSC, 0xE0068014,__READ_WRITE,__sspimsc_bits);
__IO_REG32_BIT(SSPRIS, 0xE0068018,__READ_WRITE,__sspris_bits);
__IO_REG32_BIT(SSPMIS, 0xE006801C,__READ ,__sspmis_bits);
__IO_REG32_BIT(SSPICR, 0xE0068020,__WRITE ,__sspicr_bits);
/***************************************************************************
**
** TIMER0
**
***************************************************************************/
__IO_REG32_BIT(T0IR, 0xE0004000,__READ_WRITE,__ir_bits);
__IO_REG32_BIT(T0TCR, 0xE0004004,__READ_WRITE,__tcr_bits);
__IO_REG32( T0TC, 0xE0004008,__READ_WRITE);
__IO_REG32( T0PR, 0xE000400C,__READ_WRITE);
__IO_REG32( T0PC, 0xE0004010,__READ_WRITE);
__IO_REG32_BIT(T0MCR, 0xE0004014,__READ_WRITE,__mcr_bits);
__IO_REG32( T0MR0, 0xE0004018,__READ_WRITE);
__IO_REG32( T0MR1, 0xE000401C,__READ_WRITE);
__IO_REG32( T0MR2, 0xE0004020,__READ_WRITE);
__IO_REG32( T0MR3, 0xE0004024,__READ_WRITE);
__IO_REG32_BIT(T0CCR, 0xE0004028,__READ_WRITE,__ccr_bits);
__IO_REG32( T0CR0, 0xE000402C,__READ );
__IO_REG32( T0CR1, 0xE0004030,__READ );
__IO_REG32( T0CR2, 0xE0004034,__READ );
__IO_REG32( T0CR3, 0xE0004038,__READ );
__IO_REG32_BIT(T0EMR, 0xE000403C,__READ_WRITE,__emr_bits);
__IO_REG32_BIT(T0CTCR, 0xE0004070,__READ_WRITE,__ctcr_bits);
/***************************************************************************
**
** TIMER1
**
***************************************************************************/
__IO_REG32_BIT(T1IR, 0xE0008000,__READ_WRITE,__ir_bits);
__IO_REG32_BIT(T1TCR, 0xE0008004,__READ_WRITE,__tcr_bits);
__IO_REG32( T1TC, 0xE0008008,__READ_WRITE);
__IO_REG32( T1PR, 0xE000800C,__READ_WRITE);
__IO_REG32( T1PC, 0xE0008010,__READ_WRITE);
__IO_REG32_BIT(T1MCR, 0xE0008014,__READ_WRITE,__mcr_bits);
__IO_REG32( T1MR0, 0xE0008018,__READ_WRITE);
__IO_REG32( T1MR1, 0xE000801C,__READ_WRITE);
__IO_REG32( T1MR2, 0xE0008020,__READ_WRITE);
__IO_REG32( T1MR3, 0xE0008024,__READ_WRITE);
__IO_REG32_BIT(T1CCR, 0xE0008028,__READ_WRITE,__ccr_bits);
__IO_REG32( T1CR0, 0xE000802C,__READ );
__IO_REG32( T1CR1, 0xE0008030,__READ );
__IO_REG32( T1CR2, 0xE0008034,__READ );
__IO_REG32( T1CR3, 0xE0008038,__READ );
__IO_REG32_BIT(T1EMR, 0xE000803C,__READ_WRITE,__emr_bits);
__IO_REG32_BIT(T1CTCR, 0xE0008070,__READ_WRITE,__ctcr_bits);
/***************************************************************************
**
** PWM
**
***************************************************************************/
__IO_REG32_BIT(PWMIR, 0xE0014000,__READ_WRITE,__pwmir_bits);
__IO_REG32_BIT(PWMTCR, 0xE0014004,__READ_WRITE,__pwmtcr_bits);
__IO_REG32( PWMTC, 0xE0014008,__READ_WRITE);
__IO_REG32( PWMPR, 0xE001400C,__READ_WRITE);
__IO_REG32( PWMPC, 0xE0014010,__READ_WRITE);
__IO_REG32_BIT(PWMMCR, 0xE0014014,__READ_WRITE,__pwmmcr_bits);
__IO_REG32( PWMMR0, 0xE0014018,__READ_WRITE);
__IO_REG32( PWMMR1, 0xE001401C,__READ_WRITE);
__IO_REG32( PWMMR2, 0xE0014020,__READ_WRITE);
__IO_REG32( PWMMR3, 0xE0014024,__READ_WRITE);
__IO_REG32( PWMMR4, 0xE0014040,__READ_WRITE);
__IO_REG32( PWMMR5, 0xE0014044,__READ_WRITE);
__IO_REG32( PWMMR6, 0xE0014048,__READ_WRITE);
__IO_REG32_BIT(PWMPCR, 0xE001404C,__READ_WRITE,__pwmpcr_bits);
__IO_REG32_BIT(PWMLER, 0xE0014050,__READ_WRITE,__pwmler_bits);
/***************************************************************************
**
** A/D Converters
**
***************************************************************************/
/* AD0 & AD1 */
__IO_REG32_BIT(ADGSR, 0xE0034008,__WRITE ,__adgsr_bits);
/* For backwards compatibility with 4.30A */
#define AD0DR AD0GDR
#define AD0DR_bit AD0GDR_bit
#define AD1DR AD1GDR
#define AD1DR_bit AD1GDR_bit
/* AD0 */
__IO_REG32_BIT(AD0CR, 0xE0034000,__READ_WRITE,__adcr_bits);
__IO_REG32_BIT(AD0GDR, 0xE0034004,__READ_WRITE,__adgdr_bits);
__IO_REG32_BIT(AD0INTEN, 0xE003400C,__READ_WRITE,__adinten_bits);
__IO_REG32_BIT(AD0DR0, 0xE0034010,__READ ,__addr_bits);
__IO_REG32_BIT(AD0DR1, 0xE0034014,__READ ,__addr_bits);
__IO_REG32_BIT(AD0DR2, 0xE0034018,__READ ,__addr_bits);
__IO_REG32_BIT(AD0DR3, 0xE003401C,__READ ,__addr_bits);
__IO_REG32_BIT(AD0DR4, 0xE0034020,__READ ,__addr_bits);
__IO_REG32_BIT(AD0DR5, 0xE0034024,__READ ,__addr_bits);
__IO_REG32_BIT(AD0DR6, 0xE0034028,__READ ,__addr_bits);
__IO_REG32_BIT(AD0DR7, 0xE003402C,__READ ,__addr_bits);
__IO_REG32_BIT(AD0STAT, 0xE0034030,__READ ,__adstat_bits);
/* AD1 */
__IO_REG32_BIT(AD1CR, 0xE0060000,__READ_WRITE,__adcr_bits);
__IO_REG32_BIT(AD1GDR, 0xE0060004,__READ_WRITE,__adgdr_bits);
__IO_REG32_BIT(AD1INTEN, 0xE006000C,__READ_WRITE,__adinten_bits);
__IO_REG32_BIT(AD1DR0, 0xE0060010,__READ ,__addr_bits);
__IO_REG32_BIT(AD1DR1, 0xE0060014,__READ ,__addr_bits);
__IO_REG32_BIT(AD1DR2, 0xE0060018,__READ ,__addr_bits);
__IO_REG32_BIT(AD1DR3, 0xE006001C,__READ ,__addr_bits);
__IO_REG32_BIT(AD1DR4, 0xE0060020,__READ ,__addr_bits);
__IO_REG32_BIT(AD1DR5, 0xE0060024,__READ ,__addr_bits);
__IO_REG32_BIT(AD1DR6, 0xE0060028,__READ ,__addr_bits);
__IO_REG32_BIT(AD1DR7, 0xE006002C,__READ ,__addr_bits);
__IO_REG32_BIT(AD1STAT, 0xE0060030,__READ ,__adstat_bits);
/***************************************************************************
**
** D/A Converter
**
***************************************************************************/
__IO_REG32_BIT(DACR, 0xE006C000,__READ_WRITE,__dacr_bits);
/***************************************************************************
**
** RTC
**
***************************************************************************/
__IO_REG32_BIT(ILR, 0xE0024000,__READ_WRITE,__ilr_bits);
__IO_REG32_BIT(CTC, 0xE0024004,__READ ,__ctc_bits);
__IO_REG32_BIT(CCR, 0xE0024008,__READ_WRITE,__rtcccr_bits);
__IO_REG32_BIT(CIIR, 0xE002400C,__READ_WRITE,__ciir_bits);
__IO_REG32_BIT(AMR, 0xE0024010,__READ_WRITE,__amr_bits);
__IO_REG32_BIT(CTIME0, 0xE0024014,__READ ,__ctime0_bits);
__IO_REG32_BIT(CTIME1, 0xE0024018,__READ ,__ctime1_bits);
__IO_REG32_BIT(CTIME2, 0xE002401C,__READ ,__ctime2_bits);
__IO_REG32_BIT(SEC, 0xE0024020,__READ_WRITE,__sec_bits);
__IO_REG32_BIT(MIN, 0xE0024024,__READ_WRITE,__min_bits);
__IO_REG32_BIT(HOUR, 0xE0024028,__READ_WRITE,__hour_bits);
__IO_REG32_BIT(DOM, 0xE002402C,__READ_WRITE,__dom_bits);
__IO_REG32_BIT(DOW, 0xE0024030,__READ_WRITE,__dow_bits);
__IO_REG32_BIT(DOY, 0xE0024034,__READ_WRITE,__doy_bits);
__IO_REG32_BIT(MONTH, 0xE0024038,__READ_WRITE,__month_bits);
__IO_REG32_BIT(YEAR, 0xE002403C,__READ_WRITE,__year_bits);
__IO_REG32_BIT(ALSEC, 0xE0024060,__READ_WRITE,__sec_bits);
__IO_REG32_BIT(ALMIN, 0xE0024064,__READ_WRITE,__min_bits);
__IO_REG32_BIT(ALHOUR, 0xE0024068,__READ_WRITE,__hour_bits);
__IO_REG32_BIT(ALDOM, 0xE002406C,__READ_WRITE,__dom_bits);
__IO_REG32_BIT(ALDOW, 0xE0024070,__READ_WRITE,__dow_bits);
__IO_REG32_BIT(ALDOY, 0xE0024074,__READ_WRITE,__doy_bits);
__IO_REG32_BIT(ALMON, 0xE0024078,__READ_WRITE,__month_bits);
__IO_REG32_BIT(ALYEAR, 0xE002407C,__READ_WRITE,__year_bits);
__IO_REG32_BIT(PREINT, 0xE0024080,__READ_WRITE,__preint_bits);
__IO_REG32_BIT(PREFRAC, 0xE0024084,__READ_WRITE,__prefrac_bits);
/***************************************************************************
**
** Watchdog
**
***************************************************************************/
__IO_REG32_BIT(WDMOD, 0xE0000000,__READ_WRITE,__wdmod_bits);
__IO_REG32( WDTC, 0xE0000004,__READ_WRITE);
__IO_REG32_BIT(WDFEED, 0xE0000008,__WRITE ,__wdfeed_bits);
__IO_REG32( WDTV, 0xE000000C,__READ );
/***************************************************************************
**
** USB
**
***************************************************************************/
__IO_REG32_BIT(USBINTS, 0xe01fc1c0, __READ_WRITE, __usbints_bits);
__IO_REG32_BIT(DEVINTS, 0xe0090000, __READ , __devints_bits);
__IO_REG32_BIT(DEVINTEN, 0xe0090004, __READ_WRITE, __devints_bits);
__IO_REG32_BIT(DEVINTCLR, 0xe0090008, __WRITE , __devints_bits);
__IO_REG32_BIT(DEVINTSET, 0xe009000c, __WRITE , __devints_bits);
__IO_REG8_BIT(DEVINTPRI, 0xe009002c, __WRITE , __devintpri_bits);
__IO_REG32_BIT(ENDPINTS, 0xe0090030, __READ , __endpints_bits);
__IO_REG32_BIT(ENDPINTEN, 0xe0090034, __READ_WRITE, __endpints_bits);
__IO_REG32_BIT(ENDPINTCLR, 0xe0090038, __WRITE , __endpints_bits);
__IO_REG32_BIT(ENDPINTSET, 0xe009003c, __WRITE , __endpints_bits);
__IO_REG32_BIT(ENDPINTPRI, 0xe0090040, __WRITE , __endpints_bits);
__IO_REG32_BIT(REALIZEENDP, 0xe0090044, __READ_WRITE, __realizeendp_bits);
__IO_REG32_BIT(ENDPIND, 0xe0090048, __WRITE , __endpind_bits);
__IO_REG32_BIT(MAXPACKSIZE, 0xe009004c, __READ_WRITE, __maxpacksize_bits);
__IO_REG32(RCVEDATA, 0xe0090018, __READ);
__IO_REG32_BIT(RCVEPKTLEN, 0xe0090020, __READ , __rcvepktlen_bits);
__IO_REG32(TDATA, 0xe009001c, __WRITE);
__IO_REG32_BIT(TPKTLEN, 0xe0090024, __WRITE , __transmitpktlen_bits);
__IO_REG32_BIT(USBCTRL, 0xe0090028, __READ_WRITE, __usbctrl_bits);
__IO_REG32_BIT(CMDCODE, 0xe0090010, __WRITE , __cmdcode_bits);
__IO_REG32_BIT(CMDDATA, 0xe0090014, __READ , __cmddata_bits);
__IO_REG32_BIT(DMARQSTSTAT, 0xe0090050, __READ , __dmarqstdiv_bits);
__IO_REG32_BIT(DMARQSTCLR, 0xe0090054, __WRITE , __dmarqstdiv_bits);
__IO_REG32_BIT(DMARQSTSET, 0xe0090058, __WRITE , __dmarqstdiv_bits);
__IO_REG32_BIT(UDCAHEAD, 0xe0090080, __READ_WRITE, __udcahead_bits);
__IO_REG32_BIT(EPDMASTAT, 0xe0090084, __READ , __epdmadiv_bits);
__IO_REG32_BIT(EPDMAEN, 0xe0090088, __WRITE , __epdmadiv_bits);
__IO_REG32_BIT(EPDMADIS, 0xe009008c, __WRITE , __epdmadiv_bits);
__IO_REG32_BIT(DMAINTSTAT, 0xe0090090, __READ , __dmaintstat_bits);
__IO_REG32_BIT(DMAINTEN, 0xe0090094, __READ_WRITE, __dmaintstat_bits);
__IO_REG32_BIT(NEWDDRINTSTAT, 0xe00900ac, __READ , __newdddiv_bits);
__IO_REG32_BIT(NEWDDRINTCLR, 0xe00900b0, __WRITE , __newdddiv_bits);
__IO_REG32_BIT(NEWDDRINTSET, 0xe00900b4, __WRITE , __newdddiv_bits);
__IO_REG32_BIT(EOTINTSTAT, 0xe00900a0, __READ , __newdddiv_bits);
__IO_REG32_BIT(EOTINTCLR, 0xe00900a4, __WRITE , __newdddiv_bits);
__IO_REG32_BIT(EOTINTSET, 0xe00900a8, __WRITE , __newdddiv_bits);
__IO_REG32_BIT(SYSERRINTSTAT, 0xe00900b8, __READ , __newdddiv_bits);
__IO_REG32_BIT(SYSERRINTCLR, 0xe00900bc, __WRITE , __newdddiv_bits);
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