📄 iolpc2148.h
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__REG32 WDEN : 1;
__REG32 WDRESET : 1;
__REG32 WDTOF : 1;
__REG32 WDINT : 1;
__REG32 :28;
} __wdmod_bits;
/* Watchdog feed register */
typedef struct{
__REG32 FEED : 8;
__REG32 :24;
} __wdfeed_bits;
/* USB - USB Interrupt Status Register */
typedef struct {
__REG32 USB_INT_REQ_LP : 1;
__REG32 USB_INT_REQ_HP : 1;
__REG32 USB_INT_REQ_DMA : 1;
__REG32 : 5;
__REG32 USB_NEED_CLK : 1;
__REG32 :22;
__REG32 EN_USB_INTS : 1;
} __usbints_bits;
/* USB - Device Interrupt Status Register */
/* USB - Device Interrupt Enable Register */
/* USB - Device Interrupt Clear Register */
/* USB - Device Interrupt Set Register */
typedef struct {
__REG32 FRAME : 1;
__REG32 EP_FAST : 1;
__REG32 EP_SLOW : 1;
__REG32 DEV_STAT : 1;
__REG32 CCEMTY : 1;
__REG32 CDFULL : 1;
__REG32 RxENDPKT : 1;
__REG32 TxENDPKT : 1;
__REG32 EP_RLZED : 1;
__REG32 ERR_INT : 1;
__REG32 :22;
} __devints_bits;
/* USB - Device Interrupt Priority Register */
typedef struct {
__REG8 FRAME : 1;
__REG8 EP_FAST : 1;
__REG8 : 6;
} __devintpri_bits;
/* USB - Endpoint Interrupt Status Register */
/* USB - Endpoint Interrupt Enable Register */
/* USB - Endpoint Interrupt Clear Register */
/* USB - Endpoint Interrupt Set Register */
/* USB - Endpoint Interrupt Priority Register */
typedef struct {
__REG32 EP_0RX : 1;
__REG32 EP_0TX : 1;
__REG32 EP_1RX : 1;
__REG32 EP_1TX : 1;
__REG32 EP_2RX : 1;
__REG32 EP_2TX : 1;
__REG32 EP_3RX : 1;
__REG32 EP_3TX : 1;
__REG32 EP_4RX : 1;
__REG32 EP_4TX : 1;
__REG32 EP_5RX : 1;
__REG32 EP_5TX : 1;
__REG32 EP_6RX : 1;
__REG32 EP_6TX : 1;
__REG32 EP_7RX : 1;
__REG32 EP_7TX : 1;
__REG32 EP_8RX : 1;
__REG32 EP_8TX : 1;
__REG32 EP_9RX : 1;
__REG32 EP_9TX : 1;
__REG32 EP_10RX : 1;
__REG32 EP_10TX : 1;
__REG32 EP_11RX : 1;
__REG32 EP_11TX : 1;
__REG32 EP_12RX : 1;
__REG32 EP_12TX : 1;
__REG32 EP_13RX : 1;
__REG32 EP_13TX : 1;
__REG32 EP_14RX : 1;
__REG32 EP_14TX : 1;
__REG32 EP_15RX : 1;
__REG32 EP_15TX : 1;
} __endpints_bits;
/* USB - Realize Enpoint Register */
typedef struct {
__REG32 EP0 : 1;
__REG32 EP1 : 1;
__REG32 EP2 : 1;
__REG32 EP3 : 1;
__REG32 EP4 : 1;
__REG32 EP5 : 1;
__REG32 EP6 : 1;
__REG32 EP7 : 1;
__REG32 EP8 : 1;
__REG32 EP9 : 1;
__REG32 EP10 : 1;
__REG32 EP11 : 1;
__REG32 EP12 : 1;
__REG32 EP13 : 1;
__REG32 EP14 : 1;
__REG32 EP15 : 1;
__REG32 EP16 : 1;
__REG32 EP17 : 1;
__REG32 EP18 : 1;
__REG32 EP19 : 1;
__REG32 EP20 : 1;
__REG32 EP21 : 1;
__REG32 EP22 : 1;
__REG32 EP23 : 1;
__REG32 EP24 : 1;
__REG32 EP25 : 1;
__REG32 EP26 : 1;
__REG32 EP27 : 1;
__REG32 EP28 : 1;
__REG32 EP29 : 1;
__REG32 EP30 : 1;
__REG32 EP31 : 1;
} __realizeendp_bits;
/* USB - Endpoint Index Register */
typedef struct {
__REG32 PHY_ENDP : 5;
__REG32 :27;
} __endpind_bits;
/* USB - MaxPacketSize Register */
typedef struct {
__REG32 MaxPacketSize :10;
__REG32 :22;
} __maxpacksize_bits;
/* USB - Receive Packet Length Register */
typedef struct {
__REG32 PKT_LNGTH :10;
__REG32 DV : 1;
__REG32 PKT_RDY : 1;
__REG32 :20;
} __rcvepktlen_bits;
/* USB - Transmit Packet Length Register */
typedef struct {
__REG32 PKT_LNGHT :10;
__REG32 :22;
} __transmitpktlen_bits;
/* USB - Control Register */
typedef struct {
__REG32 RD_EN : 1;
__REG32 WR_EN : 1;
__REG32 LOG_ENDPOINT : 4;
__REG32 :26;
} __usbctrl_bits;
/* USB - Command Code Register */
typedef struct {
__REG32 : 8;
__REG32 CMD_PHASE : 8;
__REG32 CMD_CODE : 8;
__REG32 : 8;
} __cmdcode_bits;
/* USB - Command Data Register */
typedef struct {
__REG32 CMD_DATA : 8;
__REG32 :24;
} __cmddata_bits;
/* USB - DMA Request Status Register */
/* USB - DMA Request Clear Register */
/* USB - DMA Request Set Regiser */
typedef struct {
__REG32 EP0 : 1;
__REG32 EP1 : 1;
__REG32 EP2 : 1;
__REG32 EP3 : 1;
__REG32 EP4 : 1;
__REG32 EP5 : 1;
__REG32 EP6 : 1;
__REG32 EP7 : 1;
__REG32 EP8 : 1;
__REG32 EP9 : 1;
__REG32 EP10 : 1;
__REG32 EP11 : 1;
__REG32 EP12 : 1;
__REG32 EP13 : 1;
__REG32 EP14 : 1;
__REG32 EP15 : 1;
__REG32 EP16 : 1;
__REG32 EP17 : 1;
__REG32 EP18 : 1;
__REG32 EP19 : 1;
__REG32 EP20 : 1;
__REG32 EP21 : 1;
__REG32 EP22 : 1;
__REG32 EP23 : 1;
__REG32 EP24 : 1;
__REG32 EP25 : 1;
__REG32 EP26 : 1;
__REG32 EP27 : 1;
__REG32 EP28 : 1;
__REG32 EP29 : 1;
__REG32 EP30 : 1;
__REG32 EP31 : 1;
} __dmarqstdiv_bits;
/* USB - UDCA Head Register */
typedef struct {
__REG32 : 7;
__REG32 UDCA_Header :25;
} __udcahead_bits;
/* USB - EP DMA Status Register */
/* USB - EP DMA Enable Register */
/* USB - EP DMA Disable Register */
typedef struct {
__REG32 EP0 : 1;
__REG32 EP1 : 1;
__REG32 EP2 : 1;
__REG32 EP3 : 1;
__REG32 EP4 : 1;
__REG32 EP5 : 1;
__REG32 EP6 : 1;
__REG32 EP7 : 1;
__REG32 EP8 : 1;
__REG32 EP9 : 1;
__REG32 EP10 : 1;
__REG32 EP11 : 1;
__REG32 EP12 : 1;
__REG32 EP13 : 1;
__REG32 EP14 : 1;
__REG32 EP15 : 1;
__REG32 EP16 : 1;
__REG32 EP17 : 1;
__REG32 EP18 : 1;
__REG32 EP19 : 1;
__REG32 EP20 : 1;
__REG32 EP21 : 1;
__REG32 EP22 : 1;
__REG32 EP23 : 1;
__REG32 EP24 : 1;
__REG32 EP25 : 1;
__REG32 EP26 : 1;
__REG32 EP27 : 1;
__REG32 EP28 : 1;
__REG32 EP29 : 1;
__REG32 EP30 : 1;
__REG32 EP31 : 1;
} __epdmadiv_bits;
/* USB - DMA Interrupt Status Register */
/* USB - DMA Interrupt Enable Register */
typedef struct {
__REG32 End_of_Transfer_Interrupt : 1;
__REG32 New_DD_Request_Interrupt : 1;
__REG32 System_Error_Interrupt : 1;
__REG32 :29;
} __dmaintstat_bits;
/* USB - New DD Request Interrupt Status Register */
/* USB - New DD Request Interrupt Clear Register */
/* USB - New DD Request Interrupt Set Register */
/* USB - End Of Transfer Interrupt Status Register */
/* USB - End Of Transfer Interrupt Clear Register */
/* USB - End Of Transfer Interrupt Set Register */
/* USB - System Error Interrupt Status Register */
/* USB - System Error Interrupt Clear Register */
/* USB - System Error Interrupt Set Register */
typedef struct {
__REG32 EP0 : 1;
__REG32 EP1 : 1;
__REG32 EP2 : 1;
__REG32 EP3 : 1;
__REG32 EP4 : 1;
__REG32 EP5 : 1;
__REG32 EP6 : 1;
__REG32 EP7 : 1;
__REG32 EP8 : 1;
__REG32 EP9 : 1;
__REG32 EP10 : 1;
__REG32 EP11 : 1;
__REG32 EP12 : 1;
__REG32 EP13 : 1;
__REG32 EP14 : 1;
__REG32 EP15 : 1;
__REG32 EP16 : 1;
__REG32 EP17 : 1;
__REG32 EP18 : 1;
__REG32 EP19 : 1;
__REG32 EP20 : 1;
__REG32 EP21 : 1;
__REG32 EP22 : 1;
__REG32 EP23 : 1;
__REG32 EP24 : 1;
__REG32 EP25 : 1;
__REG32 EP26 : 1;
__REG32 EP27 : 1;
__REG32 EP28 : 1;
__REG32 EP29 : 1;
__REG32 EP30 : 1;
__REG32 EP31 : 1;
} __newdddiv_bits;
#endif /* __IAR_SYSTEMS_ICC__ */
/* Declarations common to compiler and assembler **************************/
/***************************************************************************
**
** System control block
**
***************************************************************************/
__IO_REG32_BIT(EXTINT, 0xE01FC140,__READ_WRITE,__extint_bits);
__IO_REG32_BIT(EXTWAKE, 0xE01FC144,__READ_WRITE,__extwake_bits);
__IO_REG32_BIT(EXTMODE, 0xE01FC148,__READ_WRITE,__extmode_bits);
__IO_REG32_BIT(EXTPOLAR, 0xE01FC14C,__READ_WRITE,__extpolar_bits);
__IO_REG32_BIT(MEMMAP, 0xE01FC040,__READ_WRITE,__memmap_bits);
__IO_REG32_BIT(PLLCON, 0xE01FC080,__READ_WRITE,__pllcon_bits);
__IO_REG32_BIT(PLLCFG, 0xE01FC084,__READ_WRITE,__pllcfg_bits);
__IO_REG32_BIT(PLLSTAT, 0xE01FC088,__READ ,__pllstat_bits);
__IO_REG32_BIT(PLLFEED, 0xE01FC08C,__WRITE ,__pllfeed_bits);
__IO_REG32_BIT(PCON, 0xE01FC0C0,__READ_WRITE,__pcon_bits);
__IO_REG32_BIT(PCONP, 0xE01FC0C4,__READ_WRITE,__pconp_bits);
__IO_REG32_BIT(VPBDIV, 0xE01FC100,__READ_WRITE,__vpbdiv_bits);
__IO_REG32_BIT(RSID, 0xE01FC180,__READ_WRITE,__rsid_bits);
#define RSIR RSID
#define RSIR_bit RSID_bit
__IO_REG32( CSPR, 0xE01FC184,__READ_WRITE);
__IO_REG32_BIT(SCS, 0xE01FC1A0,__READ_WRITE,__scs_bits);
__IO_REG32_BIT(PLL1CON, 0xE01FC0A0,__READ_WRITE, __pllcon_bits);
__IO_REG32_BIT(PLL1CFG, 0xE01FC0A4,__READ_WRITE, __pllcfg_bits);
__IO_REG32_BIT(PLL1STAT, 0xE01FC0A8,__READ , __pllstat_bits);
__IO_REG32_BIT(PLL1FEED, 0xE01FC0AC,__WRITE , __pllfeed_bits);
#define PLL48CON PLL1CON
#define PLL48CON_bit PLL1CON_bit
#define PLL48CFG PLL1CFG
#define PLL48CFG_bit PLL1CFG_bit
#define PLL48STAT PLL1STAT
#define PLL48STAT_bit PLL1STAT_bit
#define PLL48FEED PLL1FEED
#define PLL48FEED_bit PLL1FEED_bit
/***************************************************************************
**
** MAM
**
***************************************************************************/
__IO_REG32_BIT(MAMCR, 0xE01FC000,__READ_WRITE,__mamcr_bits);
__IO_REG32_BIT(MAMTIM, 0xE01FC004,__READ_WRITE,__mamtim_bits);
/***************************************************************************
**
** VIC
**
***************************************************************************/
__IO_REG32_BIT(VICIRQStatus, 0xFFFFF000,__READ ,__vicint_bits);
__IO_REG32_BIT(VICFIQStatus, 0xFFFFF004,__READ ,__vicint_bits);
__IO_REG32_BIT(VICRawIntr, 0xFFFFF008,__READ ,__vicint_bits);
__IO_REG32_BIT(VICIntSelect, 0xFFFFF00C,__READ_WRITE,__vicint_bits);
__IO_REG32_BIT(VICIntEnable, 0xFFFFF010,__READ_WRITE,__vicint_bits);
__IO_REG32_BIT(VICIntEnClear, 0xFFFFF014,__WRITE ,__vicint_bits);
__IO_REG32_BIT(VICSoftInt, 0xFFFFF018,__READ_WRITE,__vicint_bits);
__IO_REG32_BIT(VICSoftIntClear, 0xFFFFF01C,__WRITE ,__vicint_bits);
__IO_REG32_BIT(VICProtection, 0xFFFFF020,__READ_WRITE,__vicprotection_bits);
__IO_REG32( VICVectAddr, 0xFFFFF030,__READ_WRITE);
__IO_REG32( VICDefVectAddr, 0xFFFFF034,__READ_WRITE);
__IO_REG32( VICVectAddr0, 0xFFFFF100,__READ_WRITE);
__IO_REG32( VICVectAddr1, 0xFFFFF104,__READ_WRITE);
__IO_REG32( VICVectAddr2, 0xFFFFF108,__READ_WRITE);
__IO_REG32( VICVectAddr3, 0xFFFFF10C,__READ_WRITE);
__IO_REG32( VICVectAddr4, 0xFFFFF110,__READ_WRITE);
__IO_REG32( VICVectAddr5, 0xFFFFF114,__READ_WRITE);
__IO_REG32( VICVectAddr6, 0xFFFFF118,__READ_WRITE);
__IO_REG32( VICVectAddr7, 0xFFFFF11C,__READ_WRITE);
__IO_REG32( VICVectAddr8, 0xFFFFF120,__READ_WRITE);
__IO_REG32( VICVectAddr9, 0xFFFFF124,__READ_WRITE);
__IO_REG32( VICVectAddr10, 0xFFFFF128,__READ_WRITE);
__IO_REG32( VICVectAddr11, 0xFFFFF12C,__READ_WRITE);
__IO_REG32( VICVectAddr12, 0xFFFFF130,__READ_WRITE);
__IO_REG32( VICVectAddr13, 0xFFFFF134,__READ_WRITE);
__IO_REG32( VICVectAddr14, 0xFFFFF138,__READ_WRITE);
__IO_REG32( VICVectAddr15, 0xFFFFF13C,__READ_WRITE);
__IO_REG32_BIT(VICVectCntl0, 0xFFFFF200,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl1, 0xFFFFF204,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl2, 0xFFFFF208,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl3, 0xFFFFF20C,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl4, 0xFFFFF210,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl5, 0xFFFFF214,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl6, 0xFFFFF218,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl7, 0xFFFFF21C,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl8, 0xFFFFF220,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl9, 0xFFFFF224,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl10, 0xFFFFF228,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl11, 0xFFFFF22C,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl12, 0xFFFFF230,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl13, 0xFFFFF234,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl14, 0xFFFFF238,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl15, 0xFFFFF23C,__READ_WRITE,__vicvectcntl_bits);
/***************************************************************************
**
** Pin connect block
**
***************************************************************************/
__IO_REG32_BIT(PINSEL0, 0xE002C000,__READ_WRITE,__pinsel0_bits);
__IO_REG32_BIT(PINSEL1, 0xE002C004,__READ_WRITE,__pinsel1_bits);
__IO_REG32( PINSEL2, 0xE002C014,__READ_WRITE);
/***************************************************************************
**
** GPIO
**
***************************************************************************/
__IO_REG32_BIT(IO0PIN, 0xE0028000,__READ_WRITE,__gpio0_bits);
__IO_REG32_BIT(IO0SET, 0xE0028004,__READ_WRITE,__gpio0_bits);
__IO_REG32_BIT(IO0DIR, 0xE0028008,__READ_WRITE,__gpio0_bits);
__IO_REG32_BIT(IO0CLR, 0xE002800C,__WRITE ,__gpio0_bits);
__IO_REG32_BIT(FIO0DIR, 0x3FFFC000,__READ_WRITE,__fgpio0_bits);
#define FIO0DIR0 FIO0DIR_bit.__byte0
#define FIO0DIR0_bit FIO0DIR_bit.__byte0_bit
#define FIO0DIR1 FIO0DIR_bit.__byte1
#define FIO0DIR1_bit FIO0DIR_bit.__byte1_bit
#define FIO0DIR2 FIO0DIR_bit.__byte2
#define FIO0DIR2_bit FIO0DIR_bit.__byte2_bit
#define FIO0DIR3 FIO0DIR_bit.__byte3
#define FIO0DIR3_bit FIO0DIR_bit.__byte3_bit
#define FIO0DIRL FIO0DIR_bit.__shortl
#define FIO0DIRL_bit FIO0DIR_bit.__shortl_bit
#define FIO0DIRU FIO0DIR_bit.__shortu
#define FIO0DIRU_bit FIO0DIR_bit.__shortu_bit
__IO_REG32_BIT(FIO0MASK, 0x3FFFC010,__READ_WRITE,__fgpio0_bits);
#define FIO0MASK0 FIO0MASK_bit.__byte0
#define FIO0MASK0_bit FIO0MASK_bit.__byte0_bit
#define FIO0MASK1 FIO0MASK_bit.__byte1
#define FIO0MASK1_bit FIO0MASK_bit.__byte1_bit
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