📄 platform_private.h
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/************************************************************************************
* This header file is provided as an interface to hardware
* This file holds definitions of the peripheral registers
*
*
* Author(s): r04471, r04473
*
* (c) Copyright 2006, Freescale, Inc. All rights reserved.
*
*
* No part of this document must be reproduced in any form - including copied,
* transcribed, printed or by any electronic means - without specific written
* permission from Freescale.
*
* Revision history:
* date Author Comments
* ---------- ------------------------ -------
* 05.05.2006 r04471 Created
* 25.05.2006 r04473 Modified - Review ID 3557
* 12.09.2007 r01191 Added ASM regs
*
************************************************************************************/
#ifndef _PLATFORM_H_
#define _PLATFORM_H_
#include "CrmRegs.h"
#include "Ssi_Regs.h"
/* platform clock boundaries */
#define PLATFORM_MAX_CLOCK (26214) // maximum value of platform clock is 26214 kHz
#define PLATFORM_MIN_CLOCK (1000) // minimum value of platform clock is 1000 kHz
/* RAM jumpvectores located @ Memory start. 0x00400000 */
#define RAM_BASE 0x00400000
#define RAM_TOP 0x00417FFF
/* ROM to RAM access pointers addresses */
#define MACPHY_RAM_TABLE_PTR (RAM_BASE + 0x44)
#define UART_RAM_TABLE_PTR (RAM_BASE + 0x48)
#define SPI_RAM_TABLE_PTR (RAM_BASE + 0x4C)
#define TMR_RAM_TABLE_PTR (RAM_BASE + 0x50)
#define I2C_RAM_TABLE_PTR (RAM_BASE + 0x54)
/*-- Defines for Processor Modes --------------------------*/
#define Mode_Fvc 0x11 // FIQ
#define Mode_Ivc 0x12 // IRQ
#define Mode_Svc 0x13 // supervisor
#define Mode_Avc 0x17 // abort
#define Mode_Uvc 0x1b // undefined
#define Mode_USER 0x10 // user
#define Mode_SYS 0x1f // system mode
/*Peripheral Memory Map Base addresses*/
#define MBAR_AIPI 0x80000000 //32 bit
#define MBAR_GPIO 0x80000000 //32 bit
#define MBAR_SSI 0x80001000 //32 bit
#define MBAR_SPI 0x80002000 //32 bit
#define MBAR_CRM 0x80003000 //32 bit
#define MBAR_MACA 0x80004000 //32 bit
#define MBAR_UART1 0x80005000 //32 bit
#define MBAR_I2C 0x80006000 //32 bit
#define MBAR_TMR 0x80007000 //16 bit
#define MBAR_TMR0 0x80007000 //16 bit
#define MBAR_TMR1 0x80007020 //16 bit
#define MBAR_TMR2 0x80007040 //16 bit
#define MBAR_TMR3 0x80007060 //16 bit
#define MBAR_TMR_EN 0x8000701E //16 bit
#define MBAR_ASM 0x80008000 //32 bit
#define MBAR_MODEM 0x80009000 //32 bit
#define MBAR_RF 0x8000A000 //32 bit
#define MBAR_UART2 0x8000B000 //32 bit
#define MBAR_FLASH 0x8000C000 //32 bit
#define MBAR_ADC 0x8000D000 //16 bit
#define MBAR_AITC 0x80020000 //32 bit
#define MBAR_ITC 0x80020000 //32 bit
#define MBAR_NEX 0x80040000 //32 bit
/* Peripheral Structure Pointer definitions */
#define GPIO_REGS_P ((GpioRegs_t *)MBAR_GPIO)
#define SSI_REGS_P ((SsiRegs_t *)MBAR_SSI)
#define SPI_REGS_P ((SpiRegs_t *)MBAR_SPI)
#define CRM_REGS_P ((CrmRegs_t *)MBAR_CRM)
#define MACA_REGS_P ((MacaRegs_t *)MBAR_MACA)
#define UART1_REGS_P ((UartRegs_t *)MBAR_UART1)
#define I2C_REGS_P ((I2cRegs_t *)MBAR_I2C)
#define TMR_REGS_P ((TmrRegs_t *)MBAR_TMR)
#define TMR0_REGS_P ((TmrRegs_t *)MBAR_TMR0)
#define TMR1_REGS_P ((TmrRegs_t *)MBAR_TMR1)
#define TMR2_REGS_P ((TmrRegs_t *)MBAR_TMR2)
#define TMR3_REGS_P ((TmrRegs_t *)MBAR_TMR3)
#define TMR_EN_REG_P ((volatile uint16_t * )MBAR_TMR_EN)
#define ASM_REGS_P ((AsmRegs_t *)MBAR_ASM)
#define MODEM_REGS_P ((ModemRegs_t *)MBAR_MODEM)
#define RF_REGS_P ((RfRegs_t *)MBAR_RF)
#define UART2_REGS_P ((UartRegs_t *)MBAR_UART2)
#define FLASH_REGS_P ((SpiRegs_t *)MBAR_FLASH)
#define ADC_REGS_P ((AdcRegs_t *)MBAR_ADC)
#define AITC_REGS_P ((AitcRegs_t *)MBAR_AITC)
#define ITC_REGS_P ((ItcRegs_t *)MBAR_ITC)
#define NEX_REGS_P ((NexRegs_t *)MBAR_NEX)
/* extended pointer definition */
#define GPIO (*GPIO_REGS_P)
#define SSI (*SSI_REGS_P)
#define SPI (*SPI_REGS_P)
#define CRM (*CRM_REGS_P)
#define MACA (*MACA_REGS_P)
#define UART1 (*UART1_REGS_P)
#define I2C (*I2C_REGS_P)
#define TMR0 (*TMR0_REGS_P)
#define TMR1 (*TMR1_REGS_P)
#define TMR2 (*TMR1_REGS_P)
#define TMR3 (*TMR1_REGS_P)
#define TMR_EN (*TMR_EN_REG_P)
#define ASM (*ASM_REGS_P)
#define MODEM (*MODEM_REGS_P)
#define RF (*RF_REGS_P)
#define UART2 (*UART2_REGS_P)
#define FLASH (*FLASH_REGS_P)
#define ADC (*ADC_REGS_P)
#define AITC (*AITC_REGS_P)
#define ITC (*ITC_REGS_P)
#define NEX (*NEX_REGS_P)
//define the registers for the GPIO peripheral
typedef struct
{ // Registers
volatile unsigned long DirLo; //MBAR_GPIO + 0x00
volatile unsigned long DirHi; //MBAR_GPIO + 0x04
volatile unsigned long DataLo; //MBAR_GPIO + 0x08
volatile unsigned long DataHi; //MBAR_GPIO + 0x0C
volatile unsigned long PuEnLo; //MBAR_GPIO + 0x10
volatile unsigned long PuEnHi; //MBAR_GPIO + 0x14
volatile unsigned long FuncSel0; //MBAR_GPIO + 0x18
volatile unsigned long FuncSel1; //MBAR_GPIO + 0x1C
volatile unsigned long FuncSel2; //MBAR_GPIO + 0x20
volatile unsigned long FuncSel3; //MBAR_GPIO + 0x24
volatile unsigned long InputDataSelLo; //MBAR_GPIO + 0x28
volatile unsigned long InputDataSelHi; //MBAR_GPIO + 0x2C
volatile unsigned long PuSelLo; //MBAR_GPIO + 0x30
volatile unsigned long PuSelHi; //MBAR_GPIO + 0x34
volatile unsigned long HystEnLo; //MBAR_GPIO + 0x38
volatile unsigned long HystEnHi; //MBAR_GPIO + 0x3C
volatile unsigned long PuKeepLo; //MBAR_GPIO + 0x40
volatile unsigned long PuKeepHi; //MBAR_GPIO + 0x44
// Virtual registers
volatile unsigned long DataSetLo; //MBAR_GPIO + 0x48
volatile unsigned long DataSetHi; //MBAR_GPIO + 0x4C
volatile unsigned long DataResetLo; //MBAR_GPIO + 0x50
volatile unsigned long DataResetHi; //MBAR_GPIO + 0x54
volatile unsigned long DirSetLo; //MBAR_GPIO + 0x58
volatile unsigned long DirSetHi; //MBAR_GPIO + 0x5C
volatile unsigned long DirResetLo; //MBAR_GPIO + 0x60
volatile unsigned long DirResetHi; //MBAR_GPIO + 0x64
} GpioRegs_t;
//define the registers for the CRM peripheral
typedef struct
{
volatile unsigned long SysCntl; //MBAR_CRM + 0x00
volatile unsigned long WuCntl; //MBAR_CRM + 0x04
volatile unsigned long SleepCntl; //MBAR_CRM + 0x08
volatile unsigned long BsCntl; //MBAR_CRM + 0x0C
volatile unsigned long CopCntl; //MBAR_CRM + 0x10
volatile unsigned long CopService; //MBAR_CRM + 0x14
volatile unsigned long Status; //MBAR_CRM + 0x18
volatile unsigned long ModStatus; //MBAR_CRM + 0x1C
volatile unsigned long WuCount; //MBAR_CRM + 0x20
volatile unsigned long WuTimeout; //MBAR_CRM + 0x24
volatile unsigned long RtcCount; //MBAR_CRM + 0x28
volatile unsigned long RtcTimeout; //MBAR_CRM + 0x2C
volatile unsigned long Reserved; //MBAR_CRM + 0x30
volatile unsigned long CalCntl; //MBAR_CRM + 0x34
volatile unsigned long CalXtalCnt; //MBAR_CRM + 0x38
volatile unsigned long RingOsclCntl; //MBAR_CRM + 0x3C
volatile unsigned long XtalCntl; //MBAR_CRM + 0x40
volatile unsigned long Xtal32Cntl; //MBAR_CRM + 0x44
volatile unsigned long VregCntl; //MBAR_CRM + 0x48
volatile unsigned long VregTrim; //MBAR_CRM + 0x4C
volatile unsigned long SwRst; //MBAR_CRM + 0x50
volatile unsigned long DigTest; //MBAR_CRM + 0x54
volatile unsigned long XtalTest; //MBAR_CRM + 0x58
volatile unsigned long VregTest; //MBAR_CRM + 0x5C
} CrmRegs_t;
//define the registers for the ITC peripheral
typedef struct
{
volatile unsigned long IntCntl; //MBAR_ITC + 0x00
volatile unsigned long NiMask; //MBAR_ITC + 0x04
volatile unsigned long IntEnNum; //MBAR_ITC + 0x08
volatile unsigned long IntDisNum; //MBAR_ITC + 0x0C
volatile unsigned long IntEnable; //MBAR_ITC + 0x10
volatile unsigned long IntType; //MBAR_ITC + 0x14
volatile unsigned long reserved3; //MBAR_ITC + 0x18
volatile unsigned long reserved2; //MBAR_ITC + 0x1C
volatile unsigned long reserved1; //MBAR_ITC + 0x20
volatile unsigned long reserved0; //MBAR_ITC + 0x24
volatile unsigned long NiVector; //MBAR_ITC + 0x28
volatile unsigned long FiVector; //MBAR_ITC + 0x2C
volatile unsigned long IntSrc; //MBAR_ITC + 0x30
volatile unsigned long IntFrc; //MBAR_ITC + 0x34
volatile unsigned long NiPend; //MBAR_ITC + 0x38
volatile unsigned long FiPend; //MBAR_ITC + 0x3C
} ItcRegs_t, AitcRegs_t;
//define the registers for the UART peripherals
typedef struct
{
volatile unsigned long Ucon; //MBAR_UARTx + 0x00
volatile unsigned long Ustat; //MBAR_UARTx + 0x04
volatile unsigned long Udata; //MBAR_UARTx + 0x08
volatile unsigned long Urxcon; //MBAR_UARTx + 0x0C
volatile unsigned long Utxcon; //MBAR_UARTx + 0x10
volatile unsigned long Ucts; //MBAR_UARTx + 0x14
volatile unsigned long Ubr; //MBAR_UARTx + 0x18
} UartRegs_t;
//define the registers for the SPI peripherals
typedef struct
{
volatile unsigned long TxData; //MBAR_SPIx + 0x00
volatile unsigned long RxData; //MBAR_SPIx + 0x04
volatile unsigned long ClkCtrl; //MBAR_SPIx + 0x08
volatile unsigned long Setup; //MBAR_SPIx + 0x0C
volatile unsigned long Status; //MBAR_SPIx + 0x10
} SpiRegs_t;
//define the registers for the TIMER peripherals
typedef struct
{
volatile unsigned short Comp1; //MBAR_TMRx + 0x00
volatile unsigned short Comp2; //MBAR_TMRx + 0x02
volatile unsigned short Capt; //MBAR_TMRx + 0x04
volatile unsigned short Load; //MBAR_TMRx + 0x06
volatile unsigned short Hold; //MBAR_TMRx + 0x08
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