maca.h

基于MMA7260QR2的跌落检查程序

#ifndef _MACA_H_
#define _MACA_H_

#include "../../../../PLM/Interface/EmbeddedTypes.h"
  
//rom_base_adr      equ 0x00000000   ; rom  base address
//ram_base_adr      equ 0x00400000   ; ram  base address
//ram0_base_adr     equ 0x00400000   ; ram0 base address (2K words =  8K
//bytes)
//ram1_base_adr     equ 0x00402000   ; ram1 base address (6K words = 24K
//bytes)
//ram2_base_adr     equ 0x00408000   ; ram2 base address (8K words = 32K
//bytes)
//ram3_base_adr     equ 0x00410000   ; ram3 base address (8K words
enum {
   cc_success          = 0,
   cc_timeout          = 1,
   cc_channel_busy     = 2,
   cc_crc_fail         = 3,
   cc_aborted          = 4,
   cc_no_ack           = 5,
   cc_no_data          = 6,
   cc_late_start       = 7,
   cc_ext_timeout      = 8,
   cc_ext_pnd_timeout  = 9,
   cc_nc1              = 10,
   cc_nc2              = 11,
   cc_nc3              = 12,
   cc_cc_external_abort= 13,
   cc_not_completed    = 14,
   cc_bus_error        = 15
};
//control codes for mode bits

enum {
   control_mode_no_cca      = 0,
   control_mode_non_slotted = (1<<3),
   control_mode_slotted     = (1<<4)
};
//control codes for sequence bits
enum {
    control_seq_nop    = 0,
    control_seq_abort  = 1,
    control_seq_wait   = 2,
    control_seq_tx     = 3,
    control_seq_rx     = 4,
    control_seq_txpoll = 5,
    control_seq_cca    = 6,
    control_seq_ed     = 7
};  

#define maca_status_cc_mask           (0x0F)

#define maca_reset_rst                (1<<0)
#define maca_reset_cln_on             (1<<1)

#define maca_frmpnd_data_pending      (1<<0)
#define maca_frmpnd_no_data_pending   (0x00)

#define maca_txlen_max_rxlen          (127<<16)

#define max_rx_ackwnd_slotted_mode    (0xFFF<<16)
#define max_rx_ackwnd_normal_mode     (0xFFF)


#define control_pre_count (7<<16)   /* preamble reapeat counter       */
#define control_rst_slot  (1<<15)   /* reset slot counter             */
#define control_role      (1<<13)   /* set if PAN coordinator         */
#define control_nofc      (1<<12)   /* set to disable FCS             */
#define control_prm       (1<<11)   /* set for promiscuous mode       */
#define control_relative  (1<<10)   /* 1 for relative, 0 for absolute */
#define control_asap      (1<<9)    /* 1 start now, 0 timer start     */
#define control_bcn       (1<<8)    /* 1 beacon only, 0 for a         */
#define control_auto      (1<<7)    /* 1 continuous rx, rx only once  */
#define control_lfsr      (1<<6)    /* 1 use polynomial for Turbolink */

#define maca_irq_strt     (1<<15)   /*
                                      STRT
                                      Bit 15
                                      Action Started Interrupt桝n auto-sequence is started, either
                                      immediately or by timer trigger.
                                      1 = Clear interrupt source
                                      0 = Leave source untouched
                                    */
#define maca_irq_sync     (1<<14)   /*
                                      SYNC
                                      Bit 14
                                      Sync Detected Interrupt桾he modem has detected the beginning
                                      of a new packet
                                      1 = Clear interrupt source
                                      0 = Leave source untouched
                                    */
#define maca_irq_cm       (1<<13)   /*
                                      CM
                                      Bit 13
                                      Complete Clock Interrupt桾he complete clock has generated a
                                      trigger.
                                      1 = Clear interrupt source
                                      0 = Leave source untouched
                                    */
#define maca_irq_crc      (1<<12)   /*
                                      CRC
                                      Bit 12
                                      Checksum Failed Interrupt桾he checksum failed for the received
                                      packet.
                                      1 = Clear interrupt source
                                      0 = Leave source untouched
                                    */
#define maca_irq_flt      (1<<11)   /*
                                      FLT
                                      Bit 11
                                      Filter Failed Interrupt桾he receive header filter failed. 1 = Clear interrupt source
                                      0 = Leave source untouched
                                      SFT
                                      Bit 10
                                      Soft Complete Clock Interrupt桾he soft complete clock has
                                      generated a trigger.
                                      1 = Clear interrupt source
                                      0 = Leave source untouched
                                    */
#define maca_irq_sftclk   (1<<10)

#define maca_irq_lvl      (1<<9)    /*
                                      LVL
                                      Bit 9
                                      FIFO Level interrupt桾he receive FIFO level is reached or
                                      exceeded.
                                      1 = Clear interrupt source
                                      0 = Leave source untouched
                                      Bit 8-5 Reserved bits桼ead as zero and written with zero for future
                                      compatibility. N/A
                                    */
#define maca_irq_rst      (1<<4)    /*
                                      RST
                                      Bit 4
                                      Reset Interrupt桝 non maskable reset interrupt detected (TBD!!!) 1 = Clear interrupt source
                                      0 = Leave source untouched
                                      WU
                                      Bit 3
                                      Wake-up Interrupt桳ow power mode has been exited (TBD in
                                      connection with CCM module).
                                      1 = Clear interrupt source
                                      0 = Leave source untouched
                                    */
#define maca_irq_wu       (1<<3)

#define maca_irq_di       (1<<2)    /*
                                      DI
                                      Bit 2
                                      Data Indication Interrupt桪uring receive, a packet has been
                                      successfully received.
                                      1 = Clear interrupt source
                                      0 = Leave source untouched
                                    */
#define maca_irq_poll     (1<<1)    /*
                                      POLL
                                      Bit 1
                                      Poll Indication Interrupt桰ssued when data request received (and
                                      before ACK transmitted). MCU may then set MACA_FRMPND and
                                      prepare fast response. TBD: Shall this be skipped if
                                      MACA_FRMPND is clear?
                                      1 = Clear interrupt source
                                      0 = Leave source untouched
                                    */
#define maca_irq_acpl     (1<<0)    /*
                                      ACPL
                                      Action Complete Interrupt桵arks the completion of a complete
                                      auto-sequence.
                                      1 = Clear interrupt source
                                      0 = Leave source untouched
                                    */


#define maca_start_clk          (1<<0)/*
                                        TMREN & TMRDIS enable/disable start clock
                                      */

#define maca_cpl_clk            (1<<1)/*
                                        TMREN & TMRDIS enable/disable complete clock
                                      */

#define maca_soft_clk           (1<<2)/*
                                        TMREN & TMRDIS enable/disable soft complete clock
                                      */

#define maca_abort_start_clk    (1<<3)/*
                                        TMRDIS abort start clock
                                      */

#define maca_abort_cpl_clk      (1<<4)/*
                                        TMRDIS abort complete clock
                                      */

#define maca_abort_soft_clk     (1<<5)/*
                                        TMRDIS abort soft complete clock
                                      */