config_pad_mode.h

freescale atk source code

#define PC_VS2_SW_PAD_REG SW_PAD_CTL_PC_VS2_PC_BVD1_PC_BVD2
#define PC_VS2_BYTE_IN_SW_PAD 2
#define PC_BVD1_SW_PAD_REG SW_PAD_CTL_PC_VS2_PC_BVD1_PC_BVD2
#define PC_BVD1_BYTE_IN_SW_PAD 1
#define PC_BVD2_SW_PAD_REG SW_PAD_CTL_PC_VS2_PC_BVD1_PC_BVD2
#define PC_BVD2_BYTE_IN_SW_PAD 0
#define PC_RST_SW_PAD_REG SW_PAD_CTL_PC_RST_IOIS16_PC_RW_B
#define PC_RST_BYTE_IN_SW_PAD 2
#define IOIS16_SW_PAD_REG SW_PAD_CTL_PC_RST_IOIS16_PC_RW_B
#define IOIS16_BYTE_IN_SW_PAD 1
#define PC_RW_B_SW_PAD_REG SW_PAD_CTL_PC_RST_IOIS16_PC_RW_B
#define PC_RW_B_BYTE_IN_SW_PAD 0
#define PC_POE_SW_PAD_REG SW_PAD_CTL_PC_POE_M_REQUEST_M_GRANT
#define PC_POE_BYTE_IN_SW_PAD 2
#define M_REQUEST_SW_PAD_REG SW_PAD_CTL_PC_POE_M_REQUEST_M_GRANT
#define M_REQUEST_BYTE_IN_SW_PAD 1
#define M_GRANT_SW_PAD_REG SW_PAD_CTL_PC_POE_M_REQUEST_M_GRANT
#define M_GRANT_BYTE_IN_SW_PAD 0
#define CSI_D4_SW_PAD_REG SW_PAD_CTL_CSI_D4_CSI_D5_CSI_D6
#define CSI_D4_BYTE_IN_SW_PAD 2
#define CSI_D5_SW_PAD_REG SW_PAD_CTL_CSI_D4_CSI_D5_CSI_D6
#define CSI_D5_BYTE_IN_SW_PAD 1
#define CSI_D6_SW_PAD_REG SW_PAD_CTL_CSI_D4_CSI_D5_CSI_D6
#define CSI_D6_BYTE_IN_SW_PAD 0
#define CSI_D7_SW_PAD_REG SW_PAD_CTL_CSI_D7_CSI_D8_CSI_D9
#define CSI_D7_BYTE_IN_SW_PAD 2
#define CSI_D8_SW_PAD_REG SW_PAD_CTL_CSI_D7_CSI_D8_CSI_D9
#define CSI_D8_BYTE_IN_SW_PAD 1
#define CSI_D9_SW_PAD_REG SW_PAD_CTL_CSI_D7_CSI_D8_CSI_D9
#define CSI_D9_BYTE_IN_SW_PAD 0
#define CSI_D10_SW_PAD_REG SW_PAD_CTL_CSI_D10_CSI_D11_CSI_D12
#define CSI_D10_BYTE_IN_SW_PAD 2
#define CSI_D11_SW_PAD_REG SW_PAD_CTL_CSI_D10_CSI_D11_CSI_D12
#define CSI_D11_BYTE_IN_SW_PAD 1
#define CSI_D12_SW_PAD_REG SW_PAD_CTL_CSI_D10_CSI_D11_CSI_D12
#define CSI_D12_BYTE_IN_SW_PAD 0
#define CSI_D13_SW_PAD_REG SW_PAD_CTL_CSI_D13_CSI_D14_CSI_D15
#define CSI_D13_BYTE_IN_SW_PAD 2
#define CSI_D14_SW_PAD_REG SW_PAD_CTL_CSI_D13_CSI_D14_CSI_D15
#define CSI_D14_BYTE_IN_SW_PAD 1
#define CSI_D15_SW_PAD_REG SW_PAD_CTL_CSI_D13_CSI_D14_CSI_D15
#define CSI_D15_BYTE_IN_SW_PAD 0
#define CSI_MCLK_SW_PAD_REG SW_PAD_CTL_CSI_MCLK_CSI_VSYNC_CSI_HSYNC
#define CSI_MCLK_BYTE_IN_SW_PAD 2
#define CSI_VSYNC_SW_PAD_REG SW_PAD_CTL_CSI_MCLK_CSI_VSYNC_CSI_HSYNC
#define CSI_VSYNC_BYTE_IN_SW_PAD 1
#define CSI_HSYNC_SW_PAD_REG SW_PAD_CTL_CSI_MCLK_CSI_VSYNC_CSI_HSYNC
#define CSI_HSYNC_BYTE_IN_SW_PAD 0
#define CSI_PIXCLK_SW_PAD_REG SW_PAD_CTL_CSI_PIXCLK_I2C_CLK_I2C_DAT
#define CSI_PIXCLK_BYTE_IN_SW_PAD 2
#define I2C_CLK_SW_PAD_REG SW_PAD_CTL_CSI_PIXCLK_I2C_CLK_I2C_DAT
#define I2C_CLK_BYTE_IN_SW_PAD 1
#define I2C_DAT_SW_PAD_REG SW_PAD_CTL_CSI_PIXCLK_I2C_CLK_I2C_DAT
#define I2C_DAT_BYTE_IN_SW_PAD 0
#define STXD3_SW_PAD_REG SW_PAD_CTL_STXD3_SRXD3_SCK3
#define STXD3_BYTE_IN_SW_PAD 2
#define SRXD3_SW_PAD_REG SW_PAD_CTL_STXD3_SRXD3_SCK3
#define SRXD3_BYTE_IN_SW_PAD 1
#define SCK3_SW_PAD_REG SW_PAD_CTL_STXD3_SRXD3_SCK3
#define SCK3_BYTE_IN_SW_PAD 0
#define SFS3_SW_PAD_REG SW_PAD_CTL_SFS3_STXD4_SRXD4
#define SFS3_BYTE_IN_SW_PAD 2
#define STXD4_SW_PAD_REG SW_PAD_CTL_SFS3_STXD4_SRXD4
#define STXD4_BYTE_IN_SW_PAD 1
#define SRXD4_SW_PAD_REG SW_PAD_CTL_SFS3_STXD4_SRXD4
#define SRXD4_BYTE_IN_SW_PAD 0
#define SCK4_SW_PAD_REG SW_PAD_CTL_SCK4_SFS4_STXD5
#define SCK4_BYTE_IN_SW_PAD 2
#define SFS4_SW_PAD_REG SW_PAD_CTL_SCK4_SFS4_STXD5
#define SFS4_BYTE_IN_SW_PAD 1
#define STXD5_SW_PAD_REG SW_PAD_CTL_SCK4_SFS4_STXD5
#define STXD5_BYTE_IN_SW_PAD 0
#define SRXD5_SW_PAD_REG SW_PAD_CTL_SRXD5_SCK5_SFS5
#define SRXD5_BYTE_IN_SW_PAD 2
#define SCK5_SW_PAD_REG SW_PAD_CTL_SRXD5_SCK5_SFS5
#define SCK5_BYTE_IN_SW_PAD 1
#define SFS5_SW_PAD_REG SW_PAD_CTL_SRXD5_SCK5_SFS5
#define SFS5_BYTE_IN_SW_PAD 0
#define STXD6_SW_PAD_REG SW_PAD_CTL_STXD6_SRXD6_SCK6
#define STXD6_BYTE_IN_SW_PAD 2
#define SRXD6_SW_PAD_REG SW_PAD_CTL_STXD6_SRXD6_SCK6
#define SRXD6_BYTE_IN_SW_PAD 1
#define SCK6_SW_PAD_REG SW_PAD_CTL_STXD6_SRXD6_SCK6
#define SCK6_BYTE_IN_SW_PAD 0
#define SFS6_SW_PAD_REG SW_PAD_CTL_SFS6_CSPI1_MOSI_CSPI1_MISO
#define SFS6_BYTE_IN_SW_PAD 2
#define CSPI1_MOSI_SW_PAD_REG SW_PAD_CTL_SFS6_CSPI1_MOSI_CSPI1_MISO
#define CSPI1_MOSI_BYTE_IN_SW_PAD 1
#define CSPI1_MISO_SW_PAD_REG SW_PAD_CTL_SFS6_CSPI1_MOSI_CSPI1_MISO
#define CSPI1_MISO_BYTE_IN_SW_PAD 0
#define CSPI1_SS0_SW_PAD_REG SW_PAD_CTL_CSPI1_SS0_CSPI1_SS1_CSPI1_SS2
#define CSPI1_SS0_BYTE_IN_SW_PAD 2
#define CSPI1_SS1_SW_PAD_REG SW_PAD_CTL_CSPI1_SS0_CSPI1_SS1_CSPI1_SS2
#define CSPI1_SS1_BYTE_IN_SW_PAD 1
#define CSPI1_SS2_SW_PAD_REG SW_PAD_CTL_CSPI1_SS0_CSPI1_SS1_CSPI1_SS2
#define CSPI1_SS2_BYTE_IN_SW_PAD 0
#define CSPI1_SCLK_SW_PAD_REG SW_PAD_CTL_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI
#define CSPI1_SCLK_BYTE_IN_SW_PAD 2
#define CSPI1_SPI_RDY_SW_PAD_REG SW_PAD_CTL_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI
#define CSPI1_SPI_RDY_BYTE_IN_SW_PAD 1
#define CSPI2_MOSI_SW_PAD_REG SW_PAD_CTL_CSPI1_SCLK_CSPI1_SPI_RDY_CSPI2_MOSI
#define CSPI2_MOSI_BYTE_IN_SW_PAD 0
#define CSPI2_MISO_SW_PAD_REG SW_PAD_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1
#define CSPI2_MISO_BYTE_IN_SW_PAD 2
#define CSPI2_SS0_SW_PAD_REG SW_PAD_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1
#define CSPI2_SS0_BYTE_IN_SW_PAD 1
#define CSPI2_SS1_SW_PAD_REG SW_PAD_CTL_CSPI2_MISO_CSPI2_SS0_CSPI2_SS1
#define CSPI2_SS1_BYTE_IN_SW_PAD 0
#define CSPI2_SS2_SW_PAD_REG SW_PAD_CTL_CSPI2_SS2_CSPI2_SCLK_CSPI2_SPI_RDY
#define CSPI2_SS2_BYTE_IN_SW_PAD 2
#define CSPI2_SCLK_SW_PAD_REG SW_PAD_CTL_CSPI2_SS2_CSPI2_SCLK_CSPI2_SPI_RDY
#define CSPI2_SCLK_BYTE_IN_SW_PAD 1
#define CSPI2_SPI_RDY_SW_PAD_REG SW_PAD_CTL_CSPI2_SS2_CSPI2_SCLK_CSPI2_SPI_RDY
#define CSPI2_SPI_RDY_BYTE_IN_SW_PAD 0
#define RXD1_SW_PAD_REG SW_PAD_CTL_RXD1_TXD1_RTS1
#define RXD1_BYTE_IN_SW_PAD 2
#define TXD1_SW_PAD_REG SW_PAD_CTL_RXD1_TXD1_RTS1
#define TXD1_BYTE_IN_SW_PAD 1
#define RTS1_SW_PAD_REG SW_PAD_CTL_RXD1_TXD1_RTS1
#define RTS1_BYTE_IN_SW_PAD 0
#define CTS1_SW_PAD_REG SW_PAD_CTL_CTS1_DTR_DCE1_DSR_DCE1
#define CTS1_BYTE_IN_SW_PAD 2
#define DTR_DCE1_SW_PAD_REG SW_PAD_CTL_CTS1_DTR_DCE1_DSR_DCE1
#define DTR_DCE1_BYTE_IN_SW_PAD 1
#define DSR_DCE1_SW_PAD_REG SW_PAD_CTL_CTS1_DTR_DCE1_DSR_DCE1
#define DSR_DCE1_BYTE_IN_SW_PAD 0
#define RI_DCE1_SW_PAD_REG SW_PAD_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1
#define RI_DCE1_BYTE_IN_SW_PAD 2
#define DCD_DCE1_SW_PAD_REG SW_PAD_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1
#define DCD_DCE1_BYTE_IN_SW_PAD 1
#define DTR_DTE1_SW_PAD_REG SW_PAD_CTL_RI_DCE1_DCD_DCE1_DTR_DTE1
#define DTR_DTE1_BYTE_IN_SW_PAD 0
#define DSR_DTE1_SW_PAD_REG SW_PAD_CTL_DSR_DTE1_RI_DTE1_DCD_DTE1
#define DSR_DTE1_BYTE_IN_SW_PAD 2
#define RI_DTE1_SW_PAD_REG SW_PAD_CTL_DSR_DTE1_RI_DTE1_DCD_DTE1
#define RI_DTE1_BYTE_IN_SW_PAD 1
#define DCD_DTE1_SW_PAD_REG SW_PAD_CTL_DSR_DTE1_RI_DTE1_DCD_DTE1
#define DCD_DTE1_BYTE_IN_SW_PAD 0
#define DTR_DCE2_SW_PAD_REG SW_PAD_CTL_DTR_DCE2_RXD2_TXD2
#define DTR_DCE2_BYTE_IN_SW_PAD 2
#define RXD2_SW_PAD_REG SW_PAD_CTL_DTR_DCE2_RXD2_TXD2
#define RXD2_BYTE_IN_SW_PAD 1
#define TXD2_SW_PAD_REG SW_PAD_CTL_DTR_DCE2_RXD2_TXD2
#define TXD2_BYTE_IN_SW_PAD 0
#define RTS2_SW_PAD_REG SW_PAD_CTL_RTS2_CTS2_BATT_LINE
#define RTS2_BYTE_IN_SW_PAD 2
#define CTS2_SW_PAD_REG SW_PAD_CTL_RTS2_CTS2_BATT_LINE
#define CTS2_BYTE_IN_SW_PAD 1
#define BATT_LINE_SW_PAD_REG SW_PAD_CTL_RTS2_CTS2_BATT_LINE
#define BATT_LINE_BYTE_IN_SW_PAD 0
#define KEY_ROW0_SW_PAD_REG SW_PAD_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2
#define KEY_ROW0_BYTE_IN_SW_PAD 2
#define KEY_ROW1_SW_PAD_REG SW_PAD_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2
#define KEY_ROW1_BYTE_IN_SW_PAD 1
#define KEY_ROW2_SW_PAD_REG SW_PAD_CTL_KEY_ROW0_KEY_ROW1_KEY_ROW2
#define KEY_ROW2_BYTE_IN_SW_PAD 0
#define KEY_ROW3_SW_PAD_REG SW_PAD_CTL_KEY_ROW3_KEY_ROW4_KEY_ROW5
#define KEY_ROW3_BYTE_IN_SW_PAD 2
#define KEY_ROW4_SW_PAD_REG SW_PAD_CTL_KEY_ROW3_KEY_ROW4_KEY_ROW5
#define KEY_ROW4_BYTE_IN_SW_PAD 1
#define KEY_ROW5_SW_PAD_REG SW_PAD_CTL_KEY_ROW3_KEY_ROW4_KEY_ROW5
#define KEY_ROW5_BYTE_IN_SW_PAD 0
#define KEY_ROW6_SW_PAD_REG SW_PAD_CTL_KEY_ROW6_KEY_ROW7_KEY_COL0
#define KEY_ROW6_BYTE_IN_SW_PAD 2
#define KEY_ROW7_SW_PAD_REG SW_PAD_CTL_KEY_ROW6_KEY_ROW7_KEY_COL0
#define KEY_ROW7_BYTE_IN_SW_PAD 1
#define KEY_COL0_SW_PAD_REG SW_PAD_CTL_KEY_ROW6_KEY_ROW7_KEY_COL0
#define KEY_COL0_BYTE_IN_SW_PAD 0
#define KEY_COL1_SW_PAD_REG SW_PAD_CTL_KEY_COL1_KEY_COL2_KEY_COL3
#define KEY_COL1_BYTE_IN_SW_PAD 2
#define KEY_COL2_SW_PAD_REG SW_PAD_CTL_KEY_COL1_KEY_COL2_KEY_COL3
#define KEY_COL2_BYTE_IN_SW_PAD 1
#define KEY_COL3_SW_PAD_REG SW_PAD_CTL_KEY_COL1_KEY_COL2_KEY_COL3
#define KEY_COL3_BYTE_IN_SW_PAD 0
#define KEY_COL4_SW_PAD_REG SW_PAD_CTL_KEY_COL4_KEY_COL5_KEY_COL6
#define KEY_COL4_BYTE_IN_SW_PAD 2
#define KEY_COL5_SW_PAD_REG SW_PAD_CTL_KEY_COL4_KEY_COL5_KEY_COL6
#define KEY_COL5_BYTE_IN_SW_PAD 1
#define KEY_COL6_SW_PAD_REG SW_PAD_CTL_KEY_COL4_KEY_COL5_KEY_COL6
#define KEY_COL6_BYTE_IN_SW_PAD 0
#define KEY_COL7_SW_PAD_REG SW_PAD_CTL_KEY_COL7_RTCK_TCK
#define KEY_COL7_BYTE_IN_SW_PAD 2
#define RTCK_SW_PAD_REG SW_PAD_CTL_KEY_COL7_RTCK_TCK
#define RTCK_BYTE_IN_SW_PAD 1
#define TCK_SW_PAD_REG SW_PAD_CTL_KEY_COL7_RTCK_TCK
#define TCK_BYTE_IN_SW_PAD 0
#define TMS_SW_PAD_REG SW_PAD_CTL_TMS_TDI_TDO
#define TMS_BYTE_IN_SW_PAD 2
#define TDI_SW_PAD_REG SW_PAD_CTL_TMS_TDI_TDO
#define TDI_BYTE_IN_SW_PAD 1
#define TDO_SW_PAD_REG SW_PAD_CTL_TMS_TDI_TDO
#define TDO_BYTE_IN_SW_PAD 0
#define TRSTB_SW_PAD_REG SW_PAD_CTL_TRSTB_DE_B_SJC_MOD
#define TRSTB_BYTE_IN_SW_PAD 2
#define DE_B_SW_PAD_REG SW_PAD_CTL_TRSTB_DE_B_SJC_MOD
#define DE_B_BYTE_IN_SW_PAD 1
#define SJC_MOD_SW_PAD_REG SW_PAD_CTL_TRSTB_DE_B_SJC_MOD
#define SJC_MOD_BYTE_IN_SW_PAD 0
#define USB_PWR_SW_PAD_REG SW_PAD_CTL_USB_PWR_USB_OC_USB_BYP
#define USB_PWR_BYTE_IN_SW_PAD 2
#define USB_OC_SW_PAD_REG SW_PAD_CTL_USB_PWR_USB_OC_USB_BYP
#define USB_OC_BYTE_IN_SW_PAD 1
#define USB_BYP_SW_PAD_REG SW_PAD_CTL_USB_PWR_USB_OC_USB_BYP
#define USB_BYP_BYTE_IN_SW_PAD 0
#define USBOTG_CLK_SW_PAD_REG SW_PAD_CTL_USBOTG_CLK_USBOTG_DIR_USBOTG_STP
#define USBOTG_CLK_BYTE_IN_SW_PAD 2
#define USBOTG_DIR_SW_PAD_REG SW_PAD_CTL_USBOTG_CLK_USBOTG_DIR_USBOTG_STP
#define USBOTG_DIR_BYTE_IN_SW_PAD 1
#define USBOTG_STP_SW_PAD_REG SW_PAD_CTL_USBOTG_CLK_USBOTG_DIR_USBOTG_STP
#define USBOTG_STP_BYTE_IN_SW_PAD 0
#define USBOTG_NXT_SW_PAD_REG SW_PAD_CTL_USBOTG_NXT_USBOTG_DATA0_USBOTG_DATA1
#define USBOTG_NXT_BYTE_IN_SW_PAD 2
#define USBOTG_DATA0_SW_PAD_REG SW_PAD_CTL_USBOTG_NXT_USBOTG_DATA0_USBOTG_DATA1
#define USBOTG_DATA0_BYTE_IN_SW_PAD 1
#define USBOTG_DATA1_SW_PAD_REG SW_PAD_CTL_USBOTG_NXT_USBOTG_DATA0_USBOTG_DATA1
#define USBOTG_DATA1_BYTE_IN_SW_PAD 0
#define USBOTG_DATA2_SW_PAD_REG SW_PAD_CTL_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4
#define USBOTG_DATA2_BYTE_IN_SW_PAD 2
#define USBOTG_DATA3_SW_PAD_REG SW_PAD_CTL_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4
#define USBOTG_DATA3_BYTE_IN_SW_PAD 1
#define USBOTG_DATA4_SW_PAD_REG SW_PAD_CTL_USBOTG_DATA2_USBOTG_DATA3_USBOTG_DATA4
#define USBOTG_DATA4_BYTE_IN_SW_PAD 0
#define USBOTG_DATA5_SW_PAD_REG SW_PAD_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7
#define USBOTG_DATA5_BYTE_IN_SW_PAD 2
#define USBOTG_DATA6_SW_PAD_REG SW_PAD_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7
#define USBOTG_DATA6_BYTE_IN_SW_PAD 1
#define USBOTG_DATA7_SW_PAD_REG SW_PAD_CTL_USBOTG_DATA5_USBOTG_DATA6_USBOTG_DATA7
#define USBOTG_DATA7_BYTE_IN_SW_PAD 0
#define USBH2_CLK_SW_PAD_REG SW_PAD_CTL_USBH2_CLK_USBH2_DIR_USBH2_STP
#define USBH2_CLK_BYTE_IN_SW_PAD 2
#define USBH2_DIR_SW_PAD_REG SW_PAD_CTL_USBH2_CLK_USBH2_DIR_USBH2_STP
#define USBH2_DIR_BYTE_IN_SW_PAD 1
#define USBH2_STP_SW_PAD_REG SW_PAD_CTL_USBH2_CLK_USBH2_DIR_USBH2_STP
#define USBH2_STP_BYTE_IN_SW_PAD 0
#define USBH2_NXT_SW_PAD_REG SW_PAD_CTL_USBH2_NXT_USBH2_DATA0_USBH2_DATA1
#define USBH2_NXT_BYTE_IN_SW_PAD 2
#define USBH2_DATA0_SW_PAD_REG SW_PAD_CTL_USBH2_NXT_USBH2_DATA0_USBH2_DATA1
#define USBH2_DATA0_BYTE_IN_SW_PAD 1
#define USBH2_DATA1_SW_PAD_REG SW_PAD_CTL_USBH2_NXT_USBH2_DATA0_USBH2_DATA1
#define USBH2_DATA1_BYTE_IN_SW_PAD 0
#define LD0_SW_PAD_REG SW_PAD_CTL_LD0_LD1_LD2
#define LD0_BYTE_IN_SW_PAD 2
#define LD1_SW_PAD_REG SW_PAD_CTL_LD0_LD1_LD2
#define LD1_BYTE_IN_SW_PAD 1
#define LD2_SW_PAD_REG SW_PAD_CTL_LD0_LD1_LD2
#define LD2_BYTE_IN_SW_PAD 0
#define LD3_SW_PAD_REG SW_PAD_CTL_LD3_LD4_LD5
#define LD3_BYTE_IN_SW_PAD 2
#define LD4_SW_PAD_REG SW_PAD_CTL_LD3_LD4_LD5
#define LD4_BYTE_IN_SW_PAD 1
#define LD5_SW_PAD_REG SW_PAD_CTL_LD3_LD4_LD5
#define LD5_BYTE_IN_SW_PAD 0
#define LD6_SW_PAD_REG SW_PAD_CTL_LD6_LD7_LD8
#define LD6_BYTE_IN_SW_PAD 2
#define LD7_SW_PAD_REG SW_PAD_CTL_LD6_LD7_LD8
#define LD7_BYTE_IN_SW_PAD 1
#define LD8_SW_PAD_REG SW_PAD_CTL_LD6_LD7_LD8
#define LD8_BYTE_IN_SW_PAD 0
#define LD9_SW_PAD_REG SW_PAD_CTL_LD9_LD10_LD11
#define LD9_BYTE_IN_SW_PAD 2
#define LD10_SW_PAD_REG SW_PAD_CTL_LD9_LD10_LD11
#define LD10_BYTE_IN_SW_PAD 1
#define LD11_SW_PAD_REG SW_PAD_CTL_LD9_LD10_LD11
#define LD11_BYTE_IN_SW_PAD 0
#define LD12_SW_PAD_REG SW_PAD_CTL_LD12_LD13_LD14
#define LD12_BYTE_IN_SW_PAD 2
#define LD13_SW_PAD_REG SW_PAD_CTL_LD12_LD13_LD14
#define LD13_BYTE_IN_SW_PAD 1
#define LD14_SW_PAD_REG SW_PAD_CTL_LD12_LD13_LD14
#define LD14_BYTE_IN_SW_PAD 0
#define LD15_SW_PAD_REG SW_PAD_CTL_LD15_LD16_LD17
#define LD15_BYTE_IN_SW_PAD 2
#define LD16_SW_PAD_REG SW_PAD_CTL_LD15_LD16_LD17
#define LD16_BYTE_IN_SW_PAD 1
#define LD17_SW_PAD_REG SW_PAD_CTL_LD15_LD16_LD17
#define LD17_BYTE_IN_SW_PAD 0
#define VSYNC0_SW_PAD_REG SW_PAD_CTL_VSYNC0_HSYNC_FPSHIFT
#define VSYNC0_BYTE_IN_SW_PAD 2
#define HSYNC_SW_PAD_REG SW_PAD_CTL_VSYNC0_HSYNC_FPSHIFT
#define HSYNC_BYTE_IN_SW_PAD 1
#define FPSHIFT_SW_PAD_REG SW_PAD_CTL_VSYNC0_HSYNC_FPSHIFT
#define FPSHIFT_BYTE_IN_SW_PAD 0
#define DRDY0_SW_PAD_REG SW_PAD_CTL_DRDY0_SD_D_I_SD_D_IO
#define DRDY0_BYTE_IN_SW_PAD 2
#define SD_D_I_SW_PAD_REG SW_PAD_CTL_DRDY0_SD_D_I_SD_D_IO
#define SD_D_I_BYTE_IN_SW_PAD 1
#define SD_D_IO_SW_PAD_REG SW_PAD_CTL_DRDY0_SD_D_I_SD_D_IO
#define SD_D_IO_BYTE_IN_SW_PAD 0
#define SD_D_CLK_SW_PAD_REG SW_PAD_CTL_SD_D_CLK_LCS0_LCS1
#define SD_D_CLK_BYTE_IN_SW_PAD 2
#define LCS0_SW_PAD_REG SW_PAD_CTL_SD_D_CLK_LCS0_LCS1
#define LCS0_BYTE_IN_SW_PAD 1
#define LCS1_SW_PAD_REG SW_PAD_CTL_SD_D_CLK_LCS0_LCS1
#define LCS1_BYTE_IN_SW_PAD 0
#define SER_RS_SW_PAD_REG SW_PAD_CTL_SER_RS_PAR_RS_WRITE
#define SER_RS_BYTE_IN_SW_PAD 2
#define PAR_RS_SW_PAD_REG SW_PAD_CTL_SER_RS_PAR_RS_WRITE
#define PAR_RS_BYTE_IN_SW_PAD 1
#define WRITE_SW_PAD_REG SW_PAD_CTL_SER_RS_PAR_RS_WRITE
#define WRITE_BYTE_IN_SW_PAD 0
#define READ_SW_PAD_REG SW_PAD_CTL_READ_VSYNC3_CONTRAST
#define READ_BYTE_IN_SW_PAD 2
#define VSYNC3_SW_PAD_REG SW_PAD_CTL_READ_VSYNC3_CONTRAST
#define VSYNC3_BYTE_IN_SW_PAD 1
#define CONTRAST_SW_PAD_REG SW_PAD_CTL_READ_VSYNC3_CONTRAST
#define CONTRAST_BYTE_IN_SW_PAD 0
#define D3_REV_SW_PAD_REG SW_PAD_CTL_D3_REV_D3_CLS_D3_SPL
#define D3_REV_BYTE_IN_SW_PAD 2
#define D3_CLS_SW_PAD_REG SW_PAD_CTL_D3_REV_D3_CLS_D3_SPL
#define D3_CLS_BYTE_IN_SW_PAD 1
#define D3_SPL_SW_PAD_REG SW_PAD_CTL_D3_REV_D3_CLS_D3_SPL
#define D3_SPL_BYTE_IN_SW_PAD 0
#define SD1_CMD_SW_PAD_REG SW_PAD_CTL_SD1_CMD_SD1_CLK_SD1_DATA0
#define SD1_CMD_BYTE_IN_SW_PAD 2
#define SD1_CLK_SW_PAD_REG SW_PAD_CTL_SD1_CMD_SD1_CLK_SD1_DATA0
#define SD1_CLK_BYTE_IN_SW_PAD 1
#define SD1_DATA0_SW_PAD_REG SW_PAD_CTL_SD1_CMD_SD1_CLK_SD1_DATA0
#define SD1_DATA0_BYTE_IN_SW_PAD 0
#define SD1_DATA1_SW_PAD_REG SW_PAD_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3
#define SD1_DATA1_BYTE_IN_SW_PAD 2
#define SD1_DATA2_SW_PAD_REG SW_PAD_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3
#define SD1_DATA2_BYTE_IN_SW_PAD 1
#define SD1_DATA3_SW_PAD_REG SW_PAD_CTL_SD1_DATA1_SD1_DATA2_SD1_DATA3
#define SD1_DATA3_BYTE_IN_SW_PAD 0
#defin