config_pad_mode.h

freescale atk source code

#define ATA_DMACK_BYTE_IN_SW_MUX 0
#define ATA_RESET_B_SW_MUX_REG SW_MUX_CTL_ATA_RESET_B_CE_CONTROL_CLKSS_CSPI3_MOSI
#define ATA_RESET_B_BYTE_IN_SW_MUX 3
#define CE_CONTROL_SW_MUX_REG SW_MUX_CTL_ATA_RESET_B_CE_CONTROL_CLKSS_CSPI3_MOSI
#define CE_CONTROL_BYTE_IN_SW_MUX 2
#define CLKSS_SW_MUX_REG SW_MUX_CTL_ATA_RESET_B_CE_CONTROL_CLKSS_CSPI3_MOSI
#define CLKSS_BYTE_IN_SW_MUX 1
#define CSPI3_MOSI_SW_MUX_REG SW_MUX_CTL_ATA_RESET_B_CE_CONTROL_CLKSS_CSPI3_MOSI
#define CSPI3_MOSI_BYTE_IN_SW_MUX 0
#define CSPI3_MISO_SW_MUX_REG SW_MUX_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY_TTM_PAD
#define CSPI3_MISO_BYTE_IN_SW_MUX 3
#define CSPI3_SCLK_SW_MUX_REG SW_MUX_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY_TTM_PAD
#define CSPI3_SCLK_BYTE_IN_SW_MUX 2
#define CSPI3_SPI_RDY_SW_MUX_REG SW_MUX_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY_TTM_PAD
#define CSPI3_SPI_RDY_BYTE_IN_SW_MUX 1
#define TTM_PAD_SW_MUX_REG SW_MUX_CTL_CSPI3_MISO_CSPI3_SCLK_CSPI3_SPI_RDY_TTM_PAD
#define TTM_PAD_BYTE_IN_SW_MUX 0

//  SW_PAD_CTL defines :
// ######################

#define CAPTURE_SW_PAD_REG SW_PAD_CTL_CAPTURE_COMPARE_WATCHDOG_RST
#define CAPTURE_BYTE_IN_SW_PAD 2
#define COMPARE_SW_PAD_REG SW_PAD_CTL_CAPTURE_COMPARE_WATCHDOG_RST
#define COMPARE_BYTE_IN_SW_PAD 1
#define WATCHDOG_RST_SW_PAD_REG SW_PAD_CTL_CAPTURE_COMPARE_WATCHDOG_RST
#define WATCHDOG_RST_BYTE_IN_SW_PAD 0
#define PWMO_SW_PAD_REG SW_PAD_CTL_PWMO_GPIO1_0_GPIO1_1
#define PWMO_BYTE_IN_SW_PAD 2
#define GPIO1_0_SW_PAD_REG SW_PAD_CTL_PWMO_GPIO1_0_GPIO1_1
#define GPIO1_0_BYTE_IN_SW_PAD 1
#define GPIO1_1_SW_PAD_REG SW_PAD_CTL_PWMO_GPIO1_0_GPIO1_1
#define GPIO1_1_BYTE_IN_SW_PAD 0
#define GPIO1_2_SW_PAD_REG SW_PAD_CTL_GPIO1_2_GPIO1_3_GPIO1_4
#define GPIO1_2_BYTE_IN_SW_PAD 2
#define GPIO1_3_SW_PAD_REG SW_PAD_CTL_GPIO1_2_GPIO1_3_GPIO1_4
#define GPIO1_3_BYTE_IN_SW_PAD 1
#define GPIO1_4_SW_PAD_REG SW_PAD_CTL_GPIO1_2_GPIO1_3_GPIO1_4
#define GPIO1_4_BYTE_IN_SW_PAD 0
#define GPIO1_5_SW_PAD_REG SW_PAD_CTL_GPIO1_5_GPIO1_6_GPIO3_0
#define GPIO1_5_BYTE_IN_SW_PAD 2
#define GPIO1_6_SW_PAD_REG SW_PAD_CTL_GPIO1_5_GPIO1_6_GPIO3_0
#define GPIO1_6_BYTE_IN_SW_PAD 1
#define GPIO3_0_SW_PAD_REG SW_PAD_CTL_GPIO1_5_GPIO1_6_GPIO3_0
#define GPIO3_0_BYTE_IN_SW_PAD 0
#define GPIO3_1_SW_PAD_REG SW_PAD_CTL_GPIO3_1_SCLK0_SRST0
#define GPIO3_1_BYTE_IN_SW_PAD 2
#define SCLK0_SW_PAD_REG SW_PAD_CTL_GPIO3_1_SCLK0_SRST0
#define SCLK0_BYTE_IN_SW_PAD 1
#define SRST0_SW_PAD_REG SW_PAD_CTL_GPIO3_1_SCLK0_SRST0
#define SRST0_BYTE_IN_SW_PAD 0
#define SVEN0_SW_PAD_REG SW_PAD_CTL_SVEN0_STX0_SRX0
#define SVEN0_BYTE_IN_SW_PAD 2
#define STX0_SW_PAD_REG SW_PAD_CTL_SVEN0_STX0_SRX0
#define STX0_BYTE_IN_SW_PAD 1
#define SRX0_SW_PAD_REG SW_PAD_CTL_SVEN0_STX0_SRX0
#define SRX0_BYTE_IN_SW_PAD 0
#define SIMPD0_SW_PAD_REG SW_PAD_CTL_SIMPD0_CKIH_RESET_IN_B
#define SIMPD0_BYTE_IN_SW_PAD 2
#define CKIH_SW_PAD_REG SW_PAD_CTL_SIMPD0_CKIH_RESET_IN_B
#define CKIH_BYTE_IN_SW_PAD 1
#define RESET_IN_B_SW_PAD_REG SW_PAD_CTL_SIMPD0_CKIH_RESET_IN_B
#define RESET_IN_B_BYTE_IN_SW_PAD 0
#define POR_B_SW_PAD_REG SW_PAD_CTL_POR_B_CLKO_BOOT_MODE0
#define POR_B_BYTE_IN_SW_PAD 2
#define CLKO_SW_PAD_REG SW_PAD_CTL_POR_B_CLKO_BOOT_MODE0
#define CLKO_BYTE_IN_SW_PAD 1
#define BOOT_MODE0_SW_PAD_REG SW_PAD_CTL_POR_B_CLKO_BOOT_MODE0
#define BOOT_MODE0_BYTE_IN_SW_PAD 0
#define BOOT_MODE1_SW_PAD_REG SW_PAD_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3
#define BOOT_MODE1_BYTE_IN_SW_PAD 2
#define BOOT_MODE2_SW_PAD_REG SW_PAD_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3
#define BOOT_MODE2_BYTE_IN_SW_PAD 1
#define BOOT_MODE3_SW_PAD_REG SW_PAD_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3
#define BOOT_MODE3_BYTE_IN_SW_PAD 0
#define BOOT_MODE4_SW_PAD_REG SW_PAD_CTL_BOOT_MODE4_CKIL_POWER_FAIL
#define BOOT_MODE4_BYTE_IN_SW_PAD 2
#define CKIL_SW_PAD_REG SW_PAD_CTL_BOOT_MODE4_CKIL_POWER_FAIL
#define CKIL_BYTE_IN_SW_PAD 1
#define POWER_FAIL_SW_PAD_REG SW_PAD_CTL_BOOT_MODE4_CKIL_POWER_FAIL
#define POWER_FAIL_BYTE_IN_SW_PAD 0
#define VSTBY_SW_PAD_REG SW_PAD_CTL_VSTBY_DVFS0_DVFS1
#define VSTBY_BYTE_IN_SW_PAD 2
#define DVFS0_SW_PAD_REG SW_PAD_CTL_VSTBY_DVFS0_DVFS1
#define DVFS0_BYTE_IN_SW_PAD 1
#define DVFS1_SW_PAD_REG SW_PAD_CTL_VSTBY_DVFS0_DVFS1
#define DVFS1_BYTE_IN_SW_PAD 0
#define VPG0_SW_PAD_REG SW_PAD_CTL_VPG0_VPG1_A0
#define VPG0_BYTE_IN_SW_PAD 2
#define VPG1_SW_PAD_REG SW_PAD_CTL_VPG0_VPG1_A0
#define VPG1_BYTE_IN_SW_PAD 1
#define A0_SW_PAD_REG SW_PAD_CTL_VPG0_VPG1_A0
#define A0_BYTE_IN_SW_PAD 0
#define A1_SW_PAD_REG SW_PAD_CTL_A1_A2_A3
#define A1_BYTE_IN_SW_PAD 2
#define A2_SW_PAD_REG SW_PAD_CTL_A1_A2_A3
#define A2_BYTE_IN_SW_PAD 1
#define A3_SW_PAD_REG SW_PAD_CTL_A1_A2_A3
#define A3_BYTE_IN_SW_PAD 0
#define A4_SW_PAD_REG SW_PAD_CTL_A4_A5_A6
#define A4_BYTE_IN_SW_PAD 2
#define A5_SW_PAD_REG SW_PAD_CTL_A4_A5_A6
#define A5_BYTE_IN_SW_PAD 1
#define A6_SW_PAD_REG SW_PAD_CTL_A4_A5_A6
#define A6_BYTE_IN_SW_PAD 0
#define A7_SW_PAD_REG SW_PAD_CTL_A7_A8_A9
#define A7_BYTE_IN_SW_PAD 2
#define A8_SW_PAD_REG SW_PAD_CTL_A7_A8_A9
#define A8_BYTE_IN_SW_PAD 1
#define A9_SW_PAD_REG SW_PAD_CTL_A7_A8_A9
#define A9_BYTE_IN_SW_PAD 0
#define A10_SW_PAD_REG SW_PAD_CTL_A10_MA10_A11
#define A10_BYTE_IN_SW_PAD 2
#define MA10_SW_PAD_REG SW_PAD_CTL_A10_MA10_A11
#define MA10_BYTE_IN_SW_PAD 1
#define A11_SW_PAD_REG SW_PAD_CTL_A10_MA10_A11
#define A11_BYTE_IN_SW_PAD 0
#define A12_SW_PAD_REG SW_PAD_CTL_A12_A13_A14
#define A12_BYTE_IN_SW_PAD 2
#define A13_SW_PAD_REG SW_PAD_CTL_A12_A13_A14
#define A13_BYTE_IN_SW_PAD 1
#define A14_SW_PAD_REG SW_PAD_CTL_A12_A13_A14
#define A14_BYTE_IN_SW_PAD 0
#define A15_SW_PAD_REG SW_PAD_CTL_A15_A16_A17
#define A15_BYTE_IN_SW_PAD 2
#define A16_SW_PAD_REG SW_PAD_CTL_A15_A16_A17
#define A16_BYTE_IN_SW_PAD 1
#define A17_SW_PAD_REG SW_PAD_CTL_A15_A16_A17
#define A17_BYTE_IN_SW_PAD 0
#define A18_SW_PAD_REG SW_PAD_CTL_A18_A19_A20
#define A18_BYTE_IN_SW_PAD 2
#define A19_SW_PAD_REG SW_PAD_CTL_A18_A19_A20
#define A19_BYTE_IN_SW_PAD 1
#define A20_SW_PAD_REG SW_PAD_CTL_A18_A19_A20
#define A20_BYTE_IN_SW_PAD 0
#define A21_SW_PAD_REG SW_PAD_CTL_A21_A22_A23
#define A21_BYTE_IN_SW_PAD 2
#define A22_SW_PAD_REG SW_PAD_CTL_A21_A22_A23
#define A22_BYTE_IN_SW_PAD 1
#define A23_SW_PAD_REG SW_PAD_CTL_A21_A22_A23
#define A23_BYTE_IN_SW_PAD 0
#define A24_SW_PAD_REG SW_PAD_CTL_A24_A25_SDBA1
#define A24_BYTE_IN_SW_PAD 2
#define A25_SW_PAD_REG SW_PAD_CTL_A24_A25_SDBA1
#define A25_BYTE_IN_SW_PAD 1
#define SDBA1_SW_PAD_REG SW_PAD_CTL_A24_A25_SDBA1
#define SDBA1_BYTE_IN_SW_PAD 0
#define SDBA0_SW_PAD_REG SW_PAD_CTL_SDBA0_SD0_SD1
#define SDBA0_BYTE_IN_SW_PAD 2
#define SD0_SW_PAD_REG SW_PAD_CTL_SDBA0_SD0_SD1
#define SD0_BYTE_IN_SW_PAD 1
#define SD1_SW_PAD_REG SW_PAD_CTL_SDBA0_SD0_SD1
#define SD1_BYTE_IN_SW_PAD 0
#define SD2_SW_PAD_REG SW_PAD_CTL_SD2_SD3_SD4
#define SD2_BYTE_IN_SW_PAD 2
#define SD3_SW_PAD_REG SW_PAD_CTL_SD2_SD3_SD4
#define SD3_BYTE_IN_SW_PAD 1
#define SD4_SW_PAD_REG SW_PAD_CTL_SD2_SD3_SD4
#define SD4_BYTE_IN_SW_PAD 0
#define SD5_SW_PAD_REG SW_PAD_CTL_SD5_SD6_SD7
#define SD5_BYTE_IN_SW_PAD 2
#define SD6_SW_PAD_REG SW_PAD_CTL_SD5_SD6_SD7
#define SD6_BYTE_IN_SW_PAD 1
#define SD7_SW_PAD_REG SW_PAD_CTL_SD5_SD6_SD7
#define SD7_BYTE_IN_SW_PAD 0
#define SD8_SW_PAD_REG SW_PAD_CTL_SD8_SD9_SD10
#define SD8_BYTE_IN_SW_PAD 2
#define SD9_SW_PAD_REG SW_PAD_CTL_SD8_SD9_SD10
#define SD9_BYTE_IN_SW_PAD 1
#define SD10_SW_PAD_REG SW_PAD_CTL_SD8_SD9_SD10
#define SD10_BYTE_IN_SW_PAD 0
#define SD11_SW_PAD_REG SW_PAD_CTL_SD11_SD12_SD13
#define SD11_BYTE_IN_SW_PAD 2
#define SD12_SW_PAD_REG SW_PAD_CTL_SD11_SD12_SD13
#define SD12_BYTE_IN_SW_PAD 1
#define SD13_SW_PAD_REG SW_PAD_CTL_SD11_SD12_SD13
#define SD13_BYTE_IN_SW_PAD 0
#define SD14_SW_PAD_REG SW_PAD_CTL_SD14_SD15_SD16
#define SD14_BYTE_IN_SW_PAD 2
#define SD15_SW_PAD_REG SW_PAD_CTL_SD14_SD15_SD16
#define SD15_BYTE_IN_SW_PAD 1
#define SD16_SW_PAD_REG SW_PAD_CTL_SD14_SD15_SD16
#define SD16_BYTE_IN_SW_PAD 0
#define SD17_SW_PAD_REG SW_PAD_CTL_SD17_SD18_SD19
#define SD17_BYTE_IN_SW_PAD 2
#define SD18_SW_PAD_REG SW_PAD_CTL_SD17_SD18_SD19
#define SD18_BYTE_IN_SW_PAD 1
#define SD19_SW_PAD_REG SW_PAD_CTL_SD17_SD18_SD19
#define SD19_BYTE_IN_SW_PAD 0
#define SD20_SW_PAD_REG SW_PAD_CTL_SD20_SD21_SD22
#define SD20_BYTE_IN_SW_PAD 2
#define SD21_SW_PAD_REG SW_PAD_CTL_SD20_SD21_SD22
#define SD21_BYTE_IN_SW_PAD 1
#define SD22_SW_PAD_REG SW_PAD_CTL_SD20_SD21_SD22
#define SD22_BYTE_IN_SW_PAD 0
#define SD23_SW_PAD_REG SW_PAD_CTL_SD23_SD24_SD25
#define SD23_BYTE_IN_SW_PAD 2
#define SD24_SW_PAD_REG SW_PAD_CTL_SD23_SD24_SD25
#define SD24_BYTE_IN_SW_PAD 1
#define SD25_SW_PAD_REG SW_PAD_CTL_SD23_SD24_SD25
#define SD25_BYTE_IN_SW_PAD 0
#define SD26_SW_PAD_REG SW_PAD_CTL_SD26_SD27_SD28
#define SD26_BYTE_IN_SW_PAD 2
#define SD27_SW_PAD_REG SW_PAD_CTL_SD26_SD27_SD28
#define SD27_BYTE_IN_SW_PAD 1
#define SD28_SW_PAD_REG SW_PAD_CTL_SD26_SD27_SD28
#define SD28_BYTE_IN_SW_PAD 0
#define SD29_SW_PAD_REG SW_PAD_CTL_SD29_SD30_SD31
#define SD29_BYTE_IN_SW_PAD 2
#define SD30_SW_PAD_REG SW_PAD_CTL_SD29_SD30_SD31
#define SD30_BYTE_IN_SW_PAD 1
#define SD31_SW_PAD_REG SW_PAD_CTL_SD29_SD30_SD31
#define SD31_BYTE_IN_SW_PAD 0
#define DQM0_SW_PAD_REG SW_PAD_CTL_DQM0_DQM1_DQM2
#define DQM0_BYTE_IN_SW_PAD 2
#define DQM1_SW_PAD_REG SW_PAD_CTL_DQM0_DQM1_DQM2
#define DQM1_BYTE_IN_SW_PAD 1
#define DQM2_SW_PAD_REG SW_PAD_CTL_DQM0_DQM1_DQM2
#define DQM2_BYTE_IN_SW_PAD 0
#define DQM3_SW_PAD_REG SW_PAD_CTL_DQM3_EB0_EB1
#define DQM3_BYTE_IN_SW_PAD 2
#define EB0_SW_PAD_REG SW_PAD_CTL_DQM3_EB0_EB1
#define EB0_BYTE_IN_SW_PAD 1
#define EB1_SW_PAD_REG SW_PAD_CTL_DQM3_EB0_EB1
#define EB1_BYTE_IN_SW_PAD 0
#define OE_SW_PAD_REG SW_PAD_CTL_OE_CS0_CS1
#define OE_BYTE_IN_SW_PAD 2
#define CS0_SW_PAD_REG SW_PAD_CTL_OE_CS0_CS1
#define CS0_BYTE_IN_SW_PAD 1
#define CS1_SW_PAD_REG SW_PAD_CTL_OE_CS0_CS1
#define CS1_BYTE_IN_SW_PAD 0
#define CS2_SW_PAD_REG SW_PAD_CTL_CS2_CS3_CS4
#define CS2_BYTE_IN_SW_PAD 2
#define CS3_SW_PAD_REG SW_PAD_CTL_CS2_CS3_CS4
#define CS3_BYTE_IN_SW_PAD 1
#define CS4_SW_PAD_REG SW_PAD_CTL_CS2_CS3_CS4
#define CS4_BYTE_IN_SW_PAD 0
#define CS5_SW_PAD_REG SW_PAD_CTL_CS5_ECB_LBA
#define CS5_BYTE_IN_SW_PAD 2
#define ECB_SW_PAD_REG SW_PAD_CTL_CS5_ECB_LBA
#define ECB_BYTE_IN_SW_PAD 1
#define LBA_SW_PAD_REG SW_PAD_CTL_CS5_ECB_LBA
#define LBA_BYTE_IN_SW_PAD 0
#define BCLK_SW_PAD_REG SW_PAD_CTL_BCLK_RW_RAS
#define BCLK_BYTE_IN_SW_PAD 2
#define RW_SW_PAD_REG SW_PAD_CTL_BCLK_RW_RAS
#define RW_BYTE_IN_SW_PAD 1
#define RAS_SW_PAD_REG SW_PAD_CTL_BCLK_RW_RAS
#define RAS_BYTE_IN_SW_PAD 0
#define CAS_SW_PAD_REG SW_PAD_CTL_CAS_SDWE_SDCKE0
#define CAS_BYTE_IN_SW_PAD 2
#define SDWE_SW_PAD_REG SW_PAD_CTL_CAS_SDWE_SDCKE0
#define SDWE_BYTE_IN_SW_PAD 1
#define SDCKE0_SW_PAD_REG SW_PAD_CTL_CAS_SDWE_SDCKE0
#define SDCKE0_BYTE_IN_SW_PAD 0
#define SDCKE1_SW_PAD_REG SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B
#define SDCKE1_BYTE_IN_SW_PAD 2
#define SDCLK_SW_PAD_REG SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B
#define SDCLK_BYTE_IN_SW_PAD 1
#define SDCLK_B_SW_PAD_REG SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B
#define SDCLK_B_BYTE_IN_SW_PAD 0
#define SDQS0_SW_PAD_REG SW_PAD_CTL_SDQS0_SDQS1_SDQS2
#define SDQS0_BYTE_IN_SW_PAD 2
#define SDQS1_SW_PAD_REG SW_PAD_CTL_SDQS0_SDQS1_SDQS2
#define SDQS1_BYTE_IN_SW_PAD 1
#define SDQS2_SW_PAD_REG SW_PAD_CTL_SDQS0_SDQS1_SDQS2
#define SDQS2_BYTE_IN_SW_PAD 0
#define SDQS3_SW_PAD_REG SW_PAD_CTL_SDQS3_NFWE_B_NFRE_B
#define SDQS3_BYTE_IN_SW_PAD 2
#define NFWE_B_SW_PAD_REG SW_PAD_CTL_SDQS3_NFWE_B_NFRE_B
#define NFWE_B_BYTE_IN_SW_PAD 1
#define NFRE_B_SW_PAD_REG SW_PAD_CTL_SDQS3_NFWE_B_NFRE_B
#define NFRE_B_BYTE_IN_SW_PAD 0
#define NFALE_SW_PAD_REG SW_PAD_CTL_NFALE_NFCLE_NFWP_B
#define NFALE_BYTE_IN_SW_PAD 2
#define NFCLE_SW_PAD_REG SW_PAD_CTL_NFALE_NFCLE_NFWP_B
#define NFCLE_BYTE_IN_SW_PAD 1
#define NFWP_B_SW_PAD_REG SW_PAD_CTL_NFALE_NFCLE_NFWP_B
#define NFWP_B_BYTE_IN_SW_PAD 0
#define NFCE_B_SW_PAD_REG SW_PAD_CTL_NFCE_B_NFRB_D15
#define NFCE_B_BYTE_IN_SW_PAD 2
#define NFRB_SW_PAD_REG SW_PAD_CTL_NFCE_B_NFRB_D15
#define NFRB_BYTE_IN_SW_PAD 1
#define D15_SW_PAD_REG SW_PAD_CTL_NFCE_B_NFRB_D15
#define D15_BYTE_IN_SW_PAD 0
#define D14_SW_PAD_REG SW_PAD_CTL_D14_D13_D12
#define D14_BYTE_IN_SW_PAD 2
#define D13_SW_PAD_REG SW_PAD_CTL_D14_D13_D12
#define D13_BYTE_IN_SW_PAD 1
#define D12_SW_PAD_REG SW_PAD_CTL_D14_D13_D12
#define D12_BYTE_IN_SW_PAD 0
#define D11_SW_PAD_REG SW_PAD_CTL_D11_D10_D9
#define D11_BYTE_IN_SW_PAD 2
#define D10_SW_PAD_REG SW_PAD_CTL_D11_D10_D9
#define D10_BYTE_IN_SW_PAD 1
#define D9_SW_PAD_REG SW_PAD_CTL_D11_D10_D9
#define D9_BYTE_IN_SW_PAD 0
#define D8_SW_PAD_REG SW_PAD_CTL_D8_D7_D6
#define D8_BYTE_IN_SW_PAD 2
#define D7_SW_PAD_REG SW_PAD_CTL_D8_D7_D6
#define D7_BYTE_IN_SW_PAD 1
#define D6_SW_PAD_REG SW_PAD_CTL_D8_D7_D6
#define D6_BYTE_IN_SW_PAD 0
#define D5_SW_PAD_REG SW_PAD_CTL_D5_D4_D3
#define D5_BYTE_IN_SW_PAD 2
#define D4_SW_PAD_REG SW_PAD_CTL_D5_D4_D3
#define D4_BYTE_IN_SW_PAD 1
#define D3_SW_PAD_REG SW_PAD_CTL_D5_D4_D3
#define D3_BYTE_IN_SW_PAD 0
#define D2_SW_PAD_REG SW_PAD_CTL_D2_D1_D0
#define D2_BYTE_IN_SW_PAD 2
#define D1_SW_PAD_REG SW_PAD_CTL_D2_D1_D0
#define D1_BYTE_IN_SW_PAD 1
#define D0_SW_PAD_REG SW_PAD_CTL_D2_D1_D0
#define D0_BYTE_IN_SW_PAD 0
#define PC_CD1_B_SW_PAD_REG SW_PAD_CTL_PC_CD1_B_PC_CD2_B_PC_WAIT_B
#define PC_CD1_B_BYTE_IN_SW_PAD 2
#define PC_CD2_B_SW_PAD_REG SW_PAD_CTL_PC_CD1_B_PC_CD2_B_PC_WAIT_B
#define PC_CD2_B_BYTE_IN_SW_PAD 1
#define PC_WAIT_B_SW_PAD_REG SW_PAD_CTL_PC_CD1_B_PC_CD2_B_PC_WAIT_B
#define PC_WAIT_B_BYTE_IN_SW_PAD 0
#define PC_READY_SW_PAD_REG SW_PAD_CTL_PC_READY_PC_PWRON_PC_VS1
#define PC_READY_BYTE_IN_SW_PAD 2
#define PC_PWRON_SW_PAD_REG SW_PAD_CTL_PC_READY_PC_PWRON_PC_VS1
#define PC_PWRON_BYTE_IN_SW_PAD 1
#define PC_VS1_SW_PAD_REG SW_PAD_CTL_PC_READY_PC_PWRON_PC_VS1
#define PC_VS1_BYTE_IN_SW_PAD 0