config_pad_mode.h

freescale atk source code

#define ATA_DIOR 318
#define ATA_DIOW 319
#define ATA_DMACK 320
#define ATA_RESET_B 321
#define CE_CONTROL 322
#define CLKSS 323
#define CSPI3_MOSI 324
#define CSPI3_MISO 325
#define CSPI3_SCLK 326
#define CSPI3_SPI_RDY 327
#define TTM_PAD 328

// SW_MUX_CTL defines :
//######################

#define CAPTURE_SW_MUX_REG SW_MUX_CTL_CAPTURE_COMPARE_WATCHDOG_RST_PWMO
#define CAPTURE_BYTE_IN_SW_MUX 3
#define COMPARE_SW_MUX_REG SW_MUX_CTL_CAPTURE_COMPARE_WATCHDOG_RST_PWMO
#define COMPARE_BYTE_IN_SW_MUX 2
#define WATCHDOG_RST_SW_MUX_REG SW_MUX_CTL_CAPTURE_COMPARE_WATCHDOG_RST_PWMO
#define WATCHDOG_RST_BYTE_IN_SW_MUX 1
#define PWMO_SW_MUX_REG SW_MUX_CTL_CAPTURE_COMPARE_WATCHDOG_RST_PWMO
#define PWMO_BYTE_IN_SW_MUX 0
#define GPIO1_0_SW_MUX_REG SW_MUX_CTL_GPIO1_0_GPIO1_1_GPIO1_2_GPIO1_3
#define GPIO1_0_BYTE_IN_SW_MUX 3
#define GPIO1_1_SW_MUX_REG SW_MUX_CTL_GPIO1_0_GPIO1_1_GPIO1_2_GPIO1_3
#define GPIO1_1_BYTE_IN_SW_MUX 2
#define GPIO1_2_SW_MUX_REG SW_MUX_CTL_GPIO1_0_GPIO1_1_GPIO1_2_GPIO1_3
#define GPIO1_2_BYTE_IN_SW_MUX 1
#define GPIO1_3_SW_MUX_REG SW_MUX_CTL_GPIO1_0_GPIO1_1_GPIO1_2_GPIO1_3
#define GPIO1_3_BYTE_IN_SW_MUX 0
#define GPIO1_4_SW_MUX_REG SW_MUX_CTL_GPIO1_4_GPIO1_5_GPIO1_6_GPIO3_0
#define GPIO1_4_BYTE_IN_SW_MUX 3
#define GPIO1_5_SW_MUX_REG SW_MUX_CTL_GPIO1_4_GPIO1_5_GPIO1_6_GPIO3_0
#define GPIO1_5_BYTE_IN_SW_MUX 2
#define GPIO1_6_SW_MUX_REG SW_MUX_CTL_GPIO1_4_GPIO1_5_GPIO1_6_GPIO3_0
#define GPIO1_6_BYTE_IN_SW_MUX 1
#define GPIO3_0_SW_MUX_REG SW_MUX_CTL_GPIO1_4_GPIO1_5_GPIO1_6_GPIO3_0
#define GPIO3_0_BYTE_IN_SW_MUX 0
#define GPIO3_1_SW_MUX_REG SW_MUX_CTL_GPIO3_1_SCLK0_SRST0_SVEN0
#define GPIO3_1_BYTE_IN_SW_MUX 3
#define SCLK0_SW_MUX_REG SW_MUX_CTL_GPIO3_1_SCLK0_SRST0_SVEN0
#define SCLK0_BYTE_IN_SW_MUX 2
#define SRST0_SW_MUX_REG SW_MUX_CTL_GPIO3_1_SCLK0_SRST0_SVEN0
#define SRST0_BYTE_IN_SW_MUX 1
#define SVEN0_SW_MUX_REG SW_MUX_CTL_GPIO3_1_SCLK0_SRST0_SVEN0
#define SVEN0_BYTE_IN_SW_MUX 0
#define STX0_SW_MUX_REG SW_MUX_CTL_STX0_SRX0_SIMPD0_CKIH
#define STX0_BYTE_IN_SW_MUX 3
#define SRX0_SW_MUX_REG SW_MUX_CTL_STX0_SRX0_SIMPD0_CKIH
#define SRX0_BYTE_IN_SW_MUX 2
#define SIMPD0_SW_MUX_REG SW_MUX_CTL_STX0_SRX0_SIMPD0_CKIH
#define SIMPD0_BYTE_IN_SW_MUX 1
#define CKIH_SW_MUX_REG SW_MUX_CTL_STX0_SRX0_SIMPD0_CKIH
#define CKIH_BYTE_IN_SW_MUX 0
#define RESET_IN_B_SW_MUX_REG SW_MUX_CTL_RESET_IN_B_POR_B_CLKO_BOOT_MODE0
#define RESET_IN_B_BYTE_IN_SW_MUX 3
#define POR_B_SW_MUX_REG SW_MUX_CTL_RESET_IN_B_POR_B_CLKO_BOOT_MODE0
#define POR_B_BYTE_IN_SW_MUX 2
#define CLKO_SW_MUX_REG SW_MUX_CTL_RESET_IN_B_POR_B_CLKO_BOOT_MODE0
#define CLKO_BYTE_IN_SW_MUX 1
#define BOOT_MODE0_SW_MUX_REG SW_MUX_CTL_RESET_IN_B_POR_B_CLKO_BOOT_MODE0
#define BOOT_MODE0_BYTE_IN_SW_MUX 0
#define BOOT_MODE1_SW_MUX_REG SW_MUX_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3_BOOT_MODE4
#define BOOT_MODE1_BYTE_IN_SW_MUX 3
#define BOOT_MODE2_SW_MUX_REG SW_MUX_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3_BOOT_MODE4
#define BOOT_MODE2_BYTE_IN_SW_MUX 2
#define BOOT_MODE3_SW_MUX_REG SW_MUX_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3_BOOT_MODE4
#define BOOT_MODE3_BYTE_IN_SW_MUX 1
#define BOOT_MODE4_SW_MUX_REG SW_MUX_CTL_BOOT_MODE1_BOOT_MODE2_BOOT_MODE3_BOOT_MODE4
#define BOOT_MODE4_BYTE_IN_SW_MUX 0
#define CKIL_SW_MUX_REG SW_MUX_CTL_CKIL_POWER_FAIL_VSTBY_DVFS0
#define CKIL_BYTE_IN_SW_MUX 3
#define POWER_FAIL_SW_MUX_REG SW_MUX_CTL_CKIL_POWER_FAIL_VSTBY_DVFS0
#define POWER_FAIL_BYTE_IN_SW_MUX 2
#define VSTBY_SW_MUX_REG SW_MUX_CTL_CKIL_POWER_FAIL_VSTBY_DVFS0
#define VSTBY_BYTE_IN_SW_MUX 1
#define DVFS0_SW_MUX_REG SW_MUX_CTL_CKIL_POWER_FAIL_VSTBY_DVFS0
#define DVFS0_BYTE_IN_SW_MUX 0
#define DVFS1_SW_MUX_REG SW_MUX_CTL_DVFS1_VPG0_VPG1_A0
#define DVFS1_BYTE_IN_SW_MUX 3
#define VPG0_SW_MUX_REG SW_MUX_CTL_DVFS1_VPG0_VPG1_A0
#define VPG0_BYTE_IN_SW_MUX 2
#define VPG1_SW_MUX_REG SW_MUX_CTL_DVFS1_VPG0_VPG1_A0
#define VPG1_BYTE_IN_SW_MUX 1
#define A0_SW_MUX_REG SW_MUX_CTL_DVFS1_VPG0_VPG1_A0
#define A0_BYTE_IN_SW_MUX 0
#define A1_SW_MUX_REG SW_MUX_CTL_A1_A2_A3_A4
#define A1_BYTE_IN_SW_MUX 3
#define A2_SW_MUX_REG SW_MUX_CTL_A1_A2_A3_A4
#define A2_BYTE_IN_SW_MUX 2
#define A3_SW_MUX_REG SW_MUX_CTL_A1_A2_A3_A4
#define A3_BYTE_IN_SW_MUX 1
#define A4_SW_MUX_REG SW_MUX_CTL_A1_A2_A3_A4
#define A4_BYTE_IN_SW_MUX 0
#define A5_SW_MUX_REG SW_MUX_CTL_A5_A6_A7_A8
#define A5_BYTE_IN_SW_MUX 3
#define A6_SW_MUX_REG SW_MUX_CTL_A5_A6_A7_A8
#define A6_BYTE_IN_SW_MUX 2
#define A7_SW_MUX_REG SW_MUX_CTL_A5_A6_A7_A8
#define A7_BYTE_IN_SW_MUX 1
#define A8_SW_MUX_REG SW_MUX_CTL_A5_A6_A7_A8
#define A8_BYTE_IN_SW_MUX 0
#define A9_SW_MUX_REG SW_MUX_CTL_A9_A10_MA10_A11
#define A9_BYTE_IN_SW_MUX 3
#define A10_SW_MUX_REG SW_MUX_CTL_A9_A10_MA10_A11
#define A10_BYTE_IN_SW_MUX 2
#define MA10_SW_MUX_REG SW_MUX_CTL_A9_A10_MA10_A11
#define MA10_BYTE_IN_SW_MUX 1
#define A11_SW_MUX_REG SW_MUX_CTL_A9_A10_MA10_A11
#define A11_BYTE_IN_SW_MUX 0
#define A12_SW_MUX_REG SW_MUX_CTL_A12_A13_A14_A15
#define A12_BYTE_IN_SW_MUX 3
#define A13_SW_MUX_REG SW_MUX_CTL_A12_A13_A14_A15
#define A13_BYTE_IN_SW_MUX 2
#define A14_SW_MUX_REG SW_MUX_CTL_A12_A13_A14_A15
#define A14_BYTE_IN_SW_MUX 1
#define A15_SW_MUX_REG SW_MUX_CTL_A12_A13_A14_A15
#define A15_BYTE_IN_SW_MUX 0
#define A16_SW_MUX_REG SW_MUX_CTL_A16_A17_A18_A19
#define A16_BYTE_IN_SW_MUX 3
#define A17_SW_MUX_REG SW_MUX_CTL_A16_A17_A18_A19
#define A17_BYTE_IN_SW_MUX 2
#define A18_SW_MUX_REG SW_MUX_CTL_A16_A17_A18_A19
#define A18_BYTE_IN_SW_MUX 1
#define A19_SW_MUX_REG SW_MUX_CTL_A16_A17_A18_A19
#define A19_BYTE_IN_SW_MUX 0
#define A20_SW_MUX_REG SW_MUX_CTL_A20_A21_A22_A23
#define A20_BYTE_IN_SW_MUX 3
#define A21_SW_MUX_REG SW_MUX_CTL_A20_A21_A22_A23
#define A21_BYTE_IN_SW_MUX 2
#define A22_SW_MUX_REG SW_MUX_CTL_A20_A21_A22_A23
#define A22_BYTE_IN_SW_MUX 1
#define A23_SW_MUX_REG SW_MUX_CTL_A20_A21_A22_A23
#define A23_BYTE_IN_SW_MUX 0
#define A24_SW_MUX_REG SW_MUX_CTL_A24_A25_SDBA1_SDBA0
#define A24_BYTE_IN_SW_MUX 3
#define A25_SW_MUX_REG SW_MUX_CTL_A24_A25_SDBA1_SDBA0
#define A25_BYTE_IN_SW_MUX 2
#define SDBA1_SW_MUX_REG SW_MUX_CTL_A24_A25_SDBA1_SDBA0
#define SDBA1_BYTE_IN_SW_MUX 1
#define SDBA0_SW_MUX_REG SW_MUX_CTL_A24_A25_SDBA1_SDBA0
#define SDBA0_BYTE_IN_SW_MUX 0
#define SD0_SW_MUX_REG SW_MUX_CTL_SD0_SD1_SD2_SD3
#define SD0_BYTE_IN_SW_MUX 3
#define SD1_SW_MUX_REG SW_MUX_CTL_SD0_SD1_SD2_SD3
#define SD1_BYTE_IN_SW_MUX 2
#define SD2_SW_MUX_REG SW_MUX_CTL_SD0_SD1_SD2_SD3
#define SD2_BYTE_IN_SW_MUX 1
#define SD3_SW_MUX_REG SW_MUX_CTL_SD0_SD1_SD2_SD3
#define SD3_BYTE_IN_SW_MUX 0
#define SD4_SW_MUX_REG SW_MUX_CTL_SD4_SD5_SD6_SD7
#define SD4_BYTE_IN_SW_MUX 3
#define SD5_SW_MUX_REG SW_MUX_CTL_SD4_SD5_SD6_SD7
#define SD5_BYTE_IN_SW_MUX 2
#define SD6_SW_MUX_REG SW_MUX_CTL_SD4_SD5_SD6_SD7
#define SD6_BYTE_IN_SW_MUX 1
#define SD7_SW_MUX_REG SW_MUX_CTL_SD4_SD5_SD6_SD7
#define SD7_BYTE_IN_SW_MUX 0
#define SD8_SW_MUX_REG SW_MUX_CTL_SD8_SD9_SD10_SD11
#define SD8_BYTE_IN_SW_MUX 3
#define SD9_SW_MUX_REG SW_MUX_CTL_SD8_SD9_SD10_SD11
#define SD9_BYTE_IN_SW_MUX 2
#define SD10_SW_MUX_REG SW_MUX_CTL_SD8_SD9_SD10_SD11
#define SD10_BYTE_IN_SW_MUX 1
#define SD11_SW_MUX_REG SW_MUX_CTL_SD8_SD9_SD10_SD11
#define SD11_BYTE_IN_SW_MUX 0
#define SD12_SW_MUX_REG SW_MUX_CTL_SD12_SD13_SD14_SD15
#define SD12_BYTE_IN_SW_MUX 3
#define SD13_SW_MUX_REG SW_MUX_CTL_SD12_SD13_SD14_SD15
#define SD13_BYTE_IN_SW_MUX 2
#define SD14_SW_MUX_REG SW_MUX_CTL_SD12_SD13_SD14_SD15
#define SD14_BYTE_IN_SW_MUX 1
#define SD15_SW_MUX_REG SW_MUX_CTL_SD12_SD13_SD14_SD15
#define SD15_BYTE_IN_SW_MUX 0
#define SD16_SW_MUX_REG SW_MUX_CTL_SD16_SD17_SD18_SD19
#define SD16_BYTE_IN_SW_MUX 3
#define SD17_SW_MUX_REG SW_MUX_CTL_SD16_SD17_SD18_SD19
#define SD17_BYTE_IN_SW_MUX 2
#define SD18_SW_MUX_REG SW_MUX_CTL_SD16_SD17_SD18_SD19
#define SD18_BYTE_IN_SW_MUX 1
#define SD19_SW_MUX_REG SW_MUX_CTL_SD16_SD17_SD18_SD19
#define SD19_BYTE_IN_SW_MUX 0
#define SD20_SW_MUX_REG SW_MUX_CTL_SD20_SD21_SD22_SD23
#define SD20_BYTE_IN_SW_MUX 3
#define SD21_SW_MUX_REG SW_MUX_CTL_SD20_SD21_SD22_SD23
#define SD21_BYTE_IN_SW_MUX 2
#define SD22_SW_MUX_REG SW_MUX_CTL_SD20_SD21_SD22_SD23
#define SD22_BYTE_IN_SW_MUX 1
#define SD23_SW_MUX_REG SW_MUX_CTL_SD20_SD21_SD22_SD23
#define SD23_BYTE_IN_SW_MUX 0
#define SD24_SW_MUX_REG SW_MUX_CTL_SD24_SD25_SD26_SD27
#define SD24_BYTE_IN_SW_MUX 3
#define SD25_SW_MUX_REG SW_MUX_CTL_SD24_SD25_SD26_SD27
#define SD25_BYTE_IN_SW_MUX 2
#define SD26_SW_MUX_REG SW_MUX_CTL_SD24_SD25_SD26_SD27
#define SD26_BYTE_IN_SW_MUX 1
#define SD27_SW_MUX_REG SW_MUX_CTL_SD24_SD25_SD26_SD27
#define SD27_BYTE_IN_SW_MUX 0
#define SD28_SW_MUX_REG SW_MUX_CTL_SD28_SD29_SD30_SD31
#define SD28_BYTE_IN_SW_MUX 3
#define SD29_SW_MUX_REG SW_MUX_CTL_SD28_SD29_SD30_SD31
#define SD29_BYTE_IN_SW_MUX 2
#define SD30_SW_MUX_REG SW_MUX_CTL_SD28_SD29_SD30_SD31
#define SD30_BYTE_IN_SW_MUX 1
#define SD31_SW_MUX_REG SW_MUX_CTL_SD28_SD29_SD30_SD31
#define SD31_BYTE_IN_SW_MUX 0
#define DQM0_SW_MUX_REG SW_MUX_CTL_DQM0_DQM1_DQM2_DQM3
#define DQM0_BYTE_IN_SW_MUX 3
#define DQM1_SW_MUX_REG SW_MUX_CTL_DQM0_DQM1_DQM2_DQM3
#define DQM1_BYTE_IN_SW_MUX 2
#define DQM2_SW_MUX_REG SW_MUX_CTL_DQM0_DQM1_DQM2_DQM3
#define DQM2_BYTE_IN_SW_MUX 1
#define DQM3_SW_MUX_REG SW_MUX_CTL_DQM0_DQM1_DQM2_DQM3
#define DQM3_BYTE_IN_SW_MUX 0
#define EB0_SW_MUX_REG SW_MUX_CTL_EB0_EB1_OE_CS0
#define EB0_BYTE_IN_SW_MUX 3
#define EB1_SW_MUX_REG SW_MUX_CTL_EB0_EB1_OE_CS0
#define EB1_BYTE_IN_SW_MUX 2
#define OE_SW_MUX_REG SW_MUX_CTL_EB0_EB1_OE_CS0
#define OE_BYTE_IN_SW_MUX 1
#define CS0_SW_MUX_REG SW_MUX_CTL_EB0_EB1_OE_CS0
#define CS0_BYTE_IN_SW_MUX 0
#define CS1_SW_MUX_REG SW_MUX_CTL_CS1_CS2_CS3_CS4
#define CS1_BYTE_IN_SW_MUX 3
#define CS2_SW_MUX_REG SW_MUX_CTL_CS1_CS2_CS3_CS4
#define CS2_BYTE_IN_SW_MUX 2
#define CS3_SW_MUX_REG SW_MUX_CTL_CS1_CS2_CS3_CS4
#define CS3_BYTE_IN_SW_MUX 1
#define CS4_SW_MUX_REG SW_MUX_CTL_CS1_CS2_CS3_CS4
#define CS4_BYTE_IN_SW_MUX 0
#define CS5_SW_MUX_REG SW_MUX_CTL_CS5_ECB_LBA_BCLK
#define CS5_BYTE_IN_SW_MUX 3
#define ECB_SW_MUX_REG SW_MUX_CTL_CS5_ECB_LBA_BCLK
#define ECB_BYTE_IN_SW_MUX 2
#define LBA_SW_MUX_REG SW_MUX_CTL_CS5_ECB_LBA_BCLK
#define LBA_BYTE_IN_SW_MUX 1
#define BCLK_SW_MUX_REG SW_MUX_CTL_CS5_ECB_LBA_BCLK
#define BCLK_BYTE_IN_SW_MUX 0
#define RW_SW_MUX_REG SW_MUX_CTL_RW_RAS_CAS_SDWE
#define RW_BYTE_IN_SW_MUX 3
#define RAS_SW_MUX_REG SW_MUX_CTL_RW_RAS_CAS_SDWE
#define RAS_BYTE_IN_SW_MUX 2
#define CAS_SW_MUX_REG SW_MUX_CTL_RW_RAS_CAS_SDWE
#define CAS_BYTE_IN_SW_MUX 1
#define SDWE_SW_MUX_REG SW_MUX_CTL_RW_RAS_CAS_SDWE
#define SDWE_BYTE_IN_SW_MUX 0
#define SDCKE0_SW_MUX_REG SW_MUX_CTL_SDCKE0_SDCKE1_SDCLK_SDCLK_B
#define SDCKE0_BYTE_IN_SW_MUX 3
#define SDCKE1_SW_MUX_REG SW_MUX_CTL_SDCKE0_SDCKE1_SDCLK_SDCLK_B
#define SDCKE1_BYTE_IN_SW_MUX 2
#define SDCLK_SW_MUX_REG SW_MUX_CTL_SDCKE0_SDCKE1_SDCLK_SDCLK_B
#define SDCLK_BYTE_IN_SW_MUX 1
#define SDCLK_B_SW_MUX_REG SW_MUX_CTL_SDCKE0_SDCKE1_SDCLK_SDCLK_B
#define SDCLK_B_BYTE_IN_SW_MUX 0
#define SDQS0_SW_MUX_REG SW_MUX_CTL_SDQS0_SDQS1_SDQS2_SDQS3
#define SDQS0_BYTE_IN_SW_MUX 3
#define SDQS1_SW_MUX_REG SW_MUX_CTL_SDQS0_SDQS1_SDQS2_SDQS3
#define SDQS1_BYTE_IN_SW_MUX 2
#define SDQS2_SW_MUX_REG SW_MUX_CTL_SDQS0_SDQS1_SDQS2_SDQS3
#define SDQS2_BYTE_IN_SW_MUX 1
#define SDQS3_SW_MUX_REG SW_MUX_CTL_SDQS0_SDQS1_SDQS2_SDQS3
#define SDQS3_BYTE_IN_SW_MUX 0
#define NFWE_B_SW_MUX_REG SW_MUX_CTL_NFWE_B_NFRE_B_NFALE_NFCLE
#define NFWE_B_BYTE_IN_SW_MUX 3
#define NFRE_B_SW_MUX_REG SW_MUX_CTL_NFWE_B_NFRE_B_NFALE_NFCLE
#define NFRE_B_BYTE_IN_SW_MUX 2
#define NFALE_SW_MUX_REG SW_MUX_CTL_NFWE_B_NFRE_B_NFALE_NFCLE
#define NFALE_BYTE_IN_SW_MUX 1
#define NFCLE_SW_MUX_REG SW_MUX_CTL_NFWE_B_NFRE_B_NFALE_NFCLE
#define NFCLE_BYTE_IN_SW_MUX 0
#define NFWP_B_SW_MUX_REG SW_MUX_CTL_NFWP_B_NFCE_B_NFRB_D15
#define NFWP_B_BYTE_IN_SW_MUX 3
#define NFCE_B_SW_MUX_REG SW_MUX_CTL_NFWP_B_NFCE_B_NFRB_D15
#define NFCE_B_BYTE_IN_SW_MUX 2
#define NFRB_SW_MUX_REG SW_MUX_CTL_NFWP_B_NFCE_B_NFRB_D15
#define NFRB_BYTE_IN_SW_MUX 1
#define D15_SW_MUX_REG SW_MUX_CTL_NFWP_B_NFCE_B_NFRB_D15
#define D15_BYTE_IN_SW_MUX 0
#define D14_SW_MUX_REG SW_MUX_CTL_D14_D13_D12_D11
#define D14_BYTE_IN_SW_MUX 3
#define D13_SW_MUX_REG SW_MUX_CTL_D14_D13_D12_D11
#define D13_BYTE_IN_SW_MUX 2
#define D12_SW_MUX_REG SW_MUX_CTL_D14_D13_D12_D11
#define D12_BYTE_IN_SW_MUX 1
#define D11_SW_MUX_REG SW_MUX_CTL_D14_D13_D12_D11
#define D11_BYTE_IN_SW_MUX 0
#define D10_SW_MUX_REG SW_MUX_CTL_D10_D9_D8_D7
#define D10_BYTE_IN_SW_MUX 3
#define D9_SW_MUX_REG SW_MUX_CTL_D10_D9_D8_D7
#define D9_BYTE_IN_SW_MUX 2
#define D8_SW_MUX_REG SW_MUX_CTL_D10_D9_D8_D7
#define D8_BYTE_IN_SW_MUX 1
#define D7_SW_MUX_REG SW_MUX_CTL_D10_D9_D8_D7
#define D7_BYTE_IN_SW_MUX 0
#define D6_SW_MUX_REG SW_MUX_CTL_D6_D5_D4_D3
#define D6_BYTE_IN_SW_MUX 3
#define D5_SW_MUX_REG SW_MUX_CTL_D6_D5_D4_D3
#define D5_BYTE_IN_SW_MUX 2
#define D4_SW_MUX_REG SW_MUX_CTL_D6_D5_D4_D3
#define D4_BYTE_IN_SW_MUX 1
#define D3_SW_MUX_REG SW_MUX_CTL_D6_D5_D4_D3
#define D3_BYTE_IN_SW_MUX 0
#define D2_SW_MUX_REG SW_MUX_CTL_D2_D1_D0_PC_CD1_B
#define D2_BYTE_IN_SW_MUX 3
#define D1_SW_MUX_REG SW_MUX_CTL_D2_D1_D0_PC_CD1_B
#define D1_BYTE_IN_SW_MUX 2
#define D0_SW_MUX_REG SW_MUX_CTL_D2_D1_D0_PC_CD1_B
#define D0_BYTE_IN_SW_MUX 1
#define PC_CD1_B_SW_MUX_REG SW_MUX_CTL_D2_D1_D0_PC_CD1_B
#define PC_CD1_B_BYTE_IN_SW_MUX 0
#define PC_CD2_B_SW_MUX_REG SW_MUX_CTL_PC_CD2_B_PC_WAIT_B_PC_READY_PC_PWRON
#define PC_CD2_B_BYTE_IN_SW_MUX 3
#define PC_WAIT_B_SW_MUX_REG SW_MUX_CTL_PC_CD2_B_PC_WAIT_B_PC_READY_PC_PWRON
#define PC_WAIT_B_BYTE_IN_SW_MUX 2
#define PC_READY_SW_MUX_REG SW_MUX_CTL_PC_CD2_B_PC_WAIT_B_PC_READY_PC_PWRON
#define PC_READY_BYTE_IN_SW_MUX 1
#define PC_PWRON_SW_MUX_REG SW_MUX_CTL_PC_CD2_B_PC_WAIT_B_PC_READY_PC_PWRON
#define PC_PWRON_BYTE_IN_SW_MUX 0
#define PC_VS1_SW_MUX_REG SW_MUX_CTL_PC_VS1_PC_VS2_PC_BVD1_PC_BVD2
#define PC_VS1_BYTE_IN_SW_MUX 3
#define PC_VS2_SW_MUX_REG SW_MUX_CTL_PC_VS1_PC_VS2_PC_BVD1_PC_BVD2
#define PC_VS2_BYTE_IN_SW_MUX 2
#define PC_BVD1_SW_MUX_REG SW_MUX_CTL_PC_VS1_PC_VS2_PC_BVD1_PC_BVD2
#define PC_BVD1_BYTE_IN_SW_MUX 1
#define PC_BVD2_SW_MUX_REG SW_MUX_CTL_PC_VS1_PC_VS2_PC_BVD1_PC_BVD2
#define PC_BVD2_BYTE_IN_SW_MUX 0