📄 ata.lis
字号:
.module ata.c
.area text(rom, con, rel)
0000 .dbfile C:\DATA\MP3\Player\Code2\ata.c
0000 .dbfunc e init_ata _init_ata fI
0000 ; j -> <dead>
0000 ; i -> <dead>
0000 ; word_read -> <dead>
0000 ; device -> R20
.even
0000 _init_ata::
0000 0E940000 xcall push_gset2
0004 402F mov R20,R16
0006 .dbline -1
0006 .dbline 18
0006 ; #include <iom128v.h>
0006 ; #include <string.h>
0006 ; #include <stdio.h>
0006 ; #include <macros.h>
0006 ; #include "ata.h"
0006 ; #include "generic.h"
0006 ; #include "remote.h"
0006 ;
0006 ; #define debug
0006 ; #define debugport 1
0006 ;
0006 ; //******************************************************************
0006 ; //* INITIALIZE HARDWARE FOR ATA DRIVER
0006 ; //*
0006 ; //*
0006 ; //******************************************************************
0006 ; int init_ata(unsigned char device)
0006 ; {
0006 .dbline 21
0006 ; unsigned int word_read,i,j;
0006 ;
0006 ; ata_databus_in;
0006 2224 clr R2
0008 2ABA out 0x1a,R2
000A .dbline 21
000A 24BA out 0x14,R2
000C .dbline 21
000C .dbline 22
000C ; PORT_ATA_IO_CNTL_DDR = 0xff;
000C 8FEF ldi R24,255
000E 80936100 sts 97,R24
0012 .dbline 23
0012 ; PORT_ATA_IO_CNTL = ATA_IO_HIZ;
0012 80936200 sts 98,R24
0016 .dbline 24
0016 ; PORT_ATA_RST_CNTL_DDR |= ATA_RESET;
0016 80916400 lds R24,100
001A 8260 ori R24,2
001C 80936400 sts 100,R24
0020 .dbline 26
0020 ;
0020 ; ata_hard_reset();
0020 3DD0 xcall _ata_hard_reset
0022 L2:
0022 .dbline 28
0022 L3:
0022 .dbline 28
0022 ;
0022 ; while (!ready & busy);
0022 0DD1 xcall _ata_rdy
0024 0023 tst R16
0026 19F4 brne L5
0028 61E0 ldi R22,1
002A 70E0 ldi R23,0
002C 02C0 xjmp L6
002E L5:
002E 6627 clr R22
0030 7727 clr R23
0032 L6:
0032 0DD1 xcall _ata_bsy
0034 202E mov R2,R16
0036 3324 clr R3
0038 2B01 movw R4,R22
003A 4220 and R4,R2
003C 5320 and R5,R3
003E 4420 tst R4
0040 81F7 brne L2
0042 5520 tst R5
0044 71F7 brne L2
0046 X0:
0046 .dbline 29
0046 ; ata_select_device(device);
0046 042F mov R16,R20
0048 3ED0 xcall _ata_select_device
004A L7:
004A .dbline 30
004A L8:
004A .dbline 30
004A ; while (!ready & busy);
004A F9D0 xcall _ata_rdy
004C 0023 tst R16
004E 19F4 brne L10
0050 61E0 ldi R22,1
0052 70E0 ldi R23,0
0054 02C0 xjmp L11
0056 L10:
0056 6627 clr R22
0058 7727 clr R23
005A L11:
005A F9D0 xcall _ata_bsy
005C 202E mov R2,R16
005E 3324 clr R3
0060 2B01 movw R4,R22
0062 4220 and R4,R2
0064 5320 and R5,R3
0066 4420 tst R4
0068 81F7 brne L7
006A 5520 tst R5
006C 71F7 brne L7
006E X1:
006E .dbline 31
006E ; ata_write_byte(ATA_IO_CMD,CMD_RECALIBRATE);
006E 20E1 ldi R18,16
0070 0DEF ldi R16,253
0072 84D0 xcall _ata_write_byte
0074 L12:
0074 .dbline 32
0074 L13:
0074 .dbline 32
0074 ; while (busy);
0074 ECD0 xcall _ata_bsy
0076 0023 tst R16
0078 E9F7 brne L12
007A .dbline 33
007A ; ata_write_byte(ATA_IO_SECTORCNT,60); // Sleep after 5 min
007A 2CE3 ldi R18,60
007C 05EE ldi R16,229
007E 7ED0 xcall _ata_write_byte
0080 L15:
0080 .dbline 34
0080 L16:
0080 .dbline 34
0080 ; while (busy);
0080 E6D0 xcall _ata_bsy
0082 0023 tst R16
0084 E9F7 brne L15
0086 .dbline 35
0086 ; ata_write_byte(ATA_IO_CMD,CMD_STANDBY2);
0086 26E9 ldi R18,150
0088 0DEF ldi R16,253
008A 78D0 xcall _ata_write_byte
008C L18:
008C .dbline 36
008C L19:
008C .dbline 36
008C ; while (busy);
008C E0D0 xcall _ata_bsy
008E 0023 tst R16
0090 E9F7 brne L18
0092 .dbline 38
0092 ;
0092 ; return 1;
0092 01E0 ldi R16,1
0094 10E0 ldi R17,0
0096 .dbline -2
0096 L1:
0096 0E940000 xcall pop_gset2
009A .dbline 0 ; func end
009A 0895 ret
009C .dbsym l j 1 i
009C .dbsym l i 1 i
009C .dbsym l word_read 1 i
009C .dbsym r device 20 c
009C .dbend
009C .dbfunc e ata_hard_reset _ata_hard_reset fV
.even
009C _ata_hard_reset::
009C .dbline -1
009C .dbline 47
009C ; }
009C ;
009C ; //******************************************************************
009C ; //* PERFORM HARDWARE RESET
009C ; //* This routine toggles ATA RESET line low for 10ms.
009C ; //*
009C ; //******************************************************************
009C ; void ata_hard_reset(void)
009C ; {
009C .dbline 48
009C ; ata_databus_in;
009C 2224 clr R2
009E 2ABA out 0x1a,R2
00A0 .dbline 48
00A0 24BA out 0x14,R2
00A2 .dbline 48
00A2 .dbline 49
00A2 ; PORT_ATA_RST_CNTL &= ~ATA_RESET;
00A2 80916500 lds R24,101
00A6 8D7F andi R24,253
00A8 80936500 sts 101,R24
00AC .dbline 50
00AC ; delay_ms(10);
00AC 0AE0 ldi R16,10
00AE 10E0 ldi R17,0
00B0 0E940000 xcall _delay_ms
00B4 .dbline 51
00B4 ; PORT_ATA_RST_CNTL |= ATA_RESET;
00B4 80916500 lds R24,101
00B8 8260 ori R24,2
00BA 80936500 sts 101,R24
00BE .dbline 52
00BE ; delay_ms(10);
00BE 0AE0 ldi R16,10
00C0 10E0 ldi R17,0
00C2 .dbline -2
00C2 .dbline 53
00C2 ; }
00C2 L21:
00C2 .dbline 0 ; func end
00C2 0C940000 xjmp _delay_ms
00C6 .dbend
00C6 .dbfunc e ata_select_device _ata_select_device fV
00C6 ; device -> R20
.even
00C6 _ata_select_device::
00C6 0E940000 xcall push_gset1
00CA 402F mov R20,R16
00CC .dbline -1
00CC .dbline 61
00CC ;
00CC ; //******************************************************************
00CC ; //* SELECT ATA DEVICE
00CC ; //* This routine defaults to Drive 0 as the target drive.
00CC ; //*
00CC ; //******************************************************************
00CC ; void ata_select_device(unsigned char device)
00CC ; {
00CC .dbline 62
00CC ; switch (device)
00CC 5527 clr R21
00CE 4030 cpi R20,0
00D0 4507 cpc R20,R21
00D2 29F0 breq L26
00D4 X2:
00D4 4130 cpi R20,1
00D6 E0E0 ldi R30,0
00D8 5E07 cpc R21,R30
00DA 29F0 breq L27
00DC 08C0 xjmp L23
00DE X3:
00DE .dbline 63
00DE ; {
00DE L26:
00DE .dbline 65
00DE ; case 0x00:
00DE ; ata_write_byte(ATA_IO_DEVICE_HEAD,ATA_DH_DEV0);
00DE 20EE ldi R18,224
00E0 05EF ldi R16,245
00E2 4CD0 xcall _ata_write_byte
00E4 .dbline 66
00E4 ; break;
00E4 07C0 xjmp L24
00E6 L27:
00E6 .dbline 68
00E6 ; case 0x01:
00E6 ; ata_write_byte(ATA_IO_DEVICE_HEAD,ATA_DH_DEV1);
00E6 20EF ldi R18,240
00E8 05EF ldi R16,245
00EA 48D0 xcall _ata_write_byte
00EC .dbline 69
00EC ; break;
00EC 03C0 xjmp L24
00EE L23:
00EE .dbline 71
00EE 20EE ldi R18,224
00F0 05EF ldi R16,245
00F2 44D0 xcall _ata_write_byte
00F4 .dbline 72
00F4 L24:
00F4 .dbline -2
00F4 .dbline 74
00F4 ; default:
00F4 ; ata_write_byte(ATA_IO_DEVICE_HEAD,ATA_DH_DEV0);
00F4 ; break;
00F4 ; }
00F4 ; }
00F4 L22:
00F4 0E940000 xcall pop_gset1
00F8 .dbline 0 ; func end
00F8 0895 ret
00FA .dbsym r device 20 c
00FA .dbend
00FA .dbfunc e ata_write_word _ata_write_word fV
00FA ; wordout -> R20,R21
00FA ; reg -> R22
.even
00FA _ata_write_word::
00FA 0E940000 xcall push_gset2
00FE A901 movw R20,R18
0100 602F mov R22,R16
0102 .dbline -1
0102 .dbline 83
0102 ;
0102 ; //******************************************************************
0102 ; //* WRITE WORD TO ATA DEVICE
0102 ; //*
0102 ; //* Mapping : D0-PA0,D1-PA2,D2-PA4,D3-PA6,D4-PC7,D5-PC5,D7-PC3,D7-PC1
0102 ; //* D8-PC0,D9-PC2,D10-PC4,D11-PC6,D12-PA7,D13-PA5,D14-PA3,D15-PA1
0102 ; //******************************************************************
0102 ; void ata_write_word(unsigned char reg,unsigned int wordout)
0102 ; {
0102 .dbline 84
0102 ; WDR();
0102 A895 wdr
0104 .dbline 85
0104 ; PORT_ATA_IO_CNTL = reg;
0104 60936200 sts 98,R22
0108 .dbline 87
0108 ;
0108 ; ata_databus_out;
0108 8FEF ldi R24,255
010A 8ABB out 0x1a,R24
010C .dbline 87
010C 84BB out 0x14,R24
010E .dbline 87
010E .dbline 89
010E ;
010E ; PORT_ATA_DATA1_OUT = 0x00;
010E 2224 clr R2
0110 2BBA out 0x1b,R2
0112 .dbline 90
0112 ; PORT_ATA_DATA2_OUT = 0x00;
0112 25BA out 0x15,R2
0114 .dbline 92
0114 ;
0114 ; if (wordout & 0x0001) PORT_ATA_DATA1_OUT |= 0x01;
0114 40FD sbrc R20,0
0116 .dbline 92
0116 D89A sbi 0x1b,0
0118 L29:
0118 .dbline 93
0118 ; if (wordout & 0x0002) PORT_ATA_DATA1_OUT |= 0x04;
0118 41FD sbrc R20,1
011A .dbline 93
011A DA9A sbi 0x1b,2
011C L31:
011C .dbline 94
011C ; if (wordout & 0x0004) PORT_ATA_DATA1_OUT |= 0x10;
011C 42FD sbrc R20,2
011E .dbline 94
011E DC9A sbi 0x1b,4
0120 L33:
0120 .dbline 95
0120 ; if (wordout & 0x0008) PORT_ATA_DATA1_OUT |= 0x40;
0120 43FD sbrc R20,3
0122 .dbline 95
0122 DE9A sbi 0x1b,6
0124 L35:
0124 .dbline 96
0124 ; if (wordout & 0x0010) PORT_ATA_DATA2_OUT |= 0x80;
0124 44FD sbrc R20,4
0126 .dbline 96
0126 AF9A sbi 0x15,7
0128 L37:
0128 .dbline 97
0128 ; if (wordout & 0x0020) PORT_ATA_DATA2_OUT |= 0x20;
0128 45FD sbrc R20,5
012A .dbline 97
012A AD9A sbi 0x15,5
012C L39:
012C .dbline 98
012C ; if (wordout & 0x0040) PORT_ATA_DATA2_OUT |= 0x08;
012C 46FD sbrc R20,6
012E .dbline 98
012E AB9A sbi 0x15,3
0130 L41:
0130 .dbline 99
0130 ; if (wordout & 0x0080) PORT_ATA_DATA2_OUT |= 0x02;
0130 47FD sbrc R20,7
0132 .dbline 99
0132 A99A sbi 0x15,1
0134 L43:
0134 .dbline 100
0134 ; if (wordout & 0x0100) PORT_ATA_DATA2_OUT |= 0x01;
0134 50FD sbrc R21,0
0136 .dbline 100
0136 A89A sbi 0x15,0
0138 L45:
0138 .dbline 101
0138 ; if (wordout & 0x0200) PORT_ATA_DATA2_OUT |= 0x04;
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