📄 t128_bank.a51
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$NOMOD51 NOLINES
$NOCOND
;------------------------------------------------------------------------------
; This file is part of the BL51 / LX51 Banked Linker/Locater package
; Copyright (c) 1988 - 2001 Keil Elektronik GmbH and Keil Software, Inc.
; Version 2.21 (Code and Variable Banking for Classic 8051 Derivatives)
;------------------------------------------------------------------------------
;************************ Configuration Section *******************************
?B_NBANKS EQU 4 ; Define maximum Number of Banks *
; ; following values are allowed: 2, 4, 8, 16, 32, 64 *
; ; for BL51 the maximum value for ?B_BANKS is 32 *
; ; for LX51 the maximum value for ?B_BANKS is 64 *
; *
?B_MODE EQU 4 ; 0 for Bank-Switching via 8051 Port *
; ; 1 for Bank-Switching via XDATA Port *
; ; 4 for user-provided bank switch code *
; *
?B_RTX EQU 0 ; 0 for applications without real-time OS *
; ; 1 for applications using the RTX-51 real-time OS *
; *
?B_VAR_BANKING EQU 0 ; Variable Banking via L51_BANK (far memory support)*
; ; 0 Variable Banking does not use L51_BANK.A51 *
; ; 1 Variable Banking uses this L51_BANK.A51 module *
; Notes: ?B_VAR_BANKING uses the 'far' and 'far const' C51 memory types to *
; extent the space for variables in RAM and/or ROM of classic 8051 *
; device. The same hardware as for code banking is used. Program *
; code banking and variable banking share the same hardware I/O pins. *
; The C51 Compiler must be used with the VARBANKING directive. *
; Variable Banking is only supported with the LX51 linker/locater. *
; *
?B_RST_BANK EQU 0x00 ; specifies the active code bank number after CPU *
; ; Reset. Used to reduce the entries in the *
; ; INTERBANK CALL TABLE. The value 0xFF disables *
; ; this LX51 linker/locater optimization. *
; Note: Interbank Call Table optimization is only possible with LX51. *
; *
;-----------------------------------------------------------------------------*
; *
; *
; *
IF ?B_MODE = 4; *
;-----------------------------------------------------------------------------*
; if ?BANK?MODE is 4 define the following switch macros *
; For bank switching via user-provided bank switch code you must define for *
; each memory bank a own macro which contains the bank switch code. The *
; following example shows how to use the I/O lines P1.4 and P1.7 for bank *
; switching. Since you can select just 4 banks with two address lines, just *
; four macros are defined. The number of macros must conform with the number *
; ?B_NBANKS number, i.e. for an application with 16 memory banks you must *
; define 16 macros. *
; *
; IMPORTANT NOTES: *
; 1. The bank switch logic must be initialized before using it. Therefore *
; add the following lines of code at the end of the STARTUP.A51 file: *
; : *
; EXTRN CODE (?B_SWITCH0) *
; CALL ?B_SWITCH0 ; init bank mechanism to code bank 0 *
; LJMP ?C_START ; line already exits at the end of file *
; : *
; *
; 2. If the bank switch macros and the additional control code generate more *
; than 256 bytes, you need to set the LONG_MACRO flag below. The error *
; message "BANK SWITCH CODE BIGGER THAN 256 BYTES, SET LONG_MACRO TO 1" *
; is generated in case that this is required. *
; *
; 3. The only registers that can be modified in this routines without prior *
; saving are: DPTR and ACC. *
; *
; *
LONG_MACRO EQU 1 ; 0 default, for normal macros and up to 8 banks *
; ; 1 big macro code or many banks *
; *
; *
; *
SWITCH0 MACRO ; Switch to Memory Bank #0 *
; Registers[0xF1F0]=0x0B;
MOV DPTR,#0xF1F0
MOV A,#0x0B
MOVX @DPTR,A
; Registers[0xF1F1]=0x00;
CLR A
INC DPTR
MOVX @DPTR,A
; Registers[0xF1F2]=0x00;
INC DPTR
MOV A,#0x00
MOVX @DPTR,A
; Registers[0xF1F3]=0x00;
INC DPTR
MOV A,#0x00
MOVX @DPTR,A
; Registers[0xF1F5]=0x6C;
MOV DPTR,#0xF1F5
MOV A,#0x6C
MOVX @DPTR,A
; Registers[0xF1F9]=0x00;
CLR A
MOV DPTR,#0xF1F9
MOVX @DPTR,A
; Registers[0xF1FA]=0x00;
INC DPTR
MOV A,#0x80
MOVX @DPTR,A
; Registers[0xF1FB]=0x00;
INC DPTR
MOV A,#0x00
MOVX @DPTR,A
; Registers[0xF1FC]=0xE0;
INC DPTR
MOV A,#0xE0
MOVX @DPTR,A
; Registers[0xF1FD]=0x90;
MOV DPTR,#0xF1FD
MOV A,#0x90
MOVX @DPTR,A
?C0001:
; while(!(Registers[0xF1FC]&0x80));
MOV DPTR,#0xF1FC
MOVX A,@DPTR
JNB ACC.7,?C0001
?C0002:
; Registers[0xF1F0]=0x0B;
MOV DPTR,#0xF1F0
MOV A,#0x0B
MOVX @DPTR,A
; Registers[0xF1F1]=0x00;
CLR A
INC DPTR
MOVX @DPTR,A
; Registers[0xF1F2]=0x20;
INC DPTR
MOV A,#0x20
MOVX @DPTR,A
; Registers[0xF1F3]=0x00;
INC DPTR
MOV A,#0x00
MOVX @DPTR,A
; Registers[0xF1F5]=0x6C;
MOV DPTR,#0xF1F5
MOV A,#0x6C
MOVX @DPTR,A
; Registers[0xF1F9]=0x00;
CLR A
MOV DPTR,#0xF1F9
MOVX @DPTR,A
; Registers[0xF1FA]=0xA0;
INC DPTR
MOV A,#0xA0
MOVX @DPTR,A
; Registers[0xF1FB]=0x00;
INC DPTR
MOV A,#0x00
MOVX @DPTR,A
; Registers[0xF1FC]=0xE0;
INC DPTR
MOV A,#0xE0
MOVX @DPTR,A
; Registers[0xF1FD]=0x90;
MOV DPTR,#0xF1FD
MOV A,#0x90
MOVX @DPTR,A
ENDM
SWITCH1 MACRO ; Switch to Memory Bank #1
; Registers[0xF1F0]=0x0B;
MOV DPTR,#0xF1F0
MOV A,#0x0B
MOVX @DPTR,A
; Registers[0xF1F1]=0x00;
CLR A
INC DPTR
MOVX @DPTR,A
; Registers[0xF1F2]=0x40;
INC DPTR
MOV A,#0x40
MOVX @DPTR,A
; Registers[0xF1F3]=0x00;
INC DPTR
MOV A,#0x00
MOVX @DPTR,A
; Registers[0xF1F5]=0x6C;
MOV DPTR,#0xF1F5
MOV A,#0x6C
MOVX @DPTR,A
; Registers[0xF1F9]=0x00;
CLR A
MOV DPTR,#0xF1F9
MOVX @DPTR,A
; Registers[0xF1FA]=0x00;
INC DPTR
MOV A,#0x80
MOVX @DPTR,A
; Registers[0xF1FB]=0x00;
INC DPTR
MOV A,#0x00
MOVX @DPTR,A
; Registers[0xF1FC]=0xE0;
INC DPTR
MOV A,#0xE0
MOVX @DPTR,A
; Registers[0xF1FD]=0x90;
MOV DPTR,#0xF1FD
MOV A,#0x90
MOVX @DPTR,A
?C0003:
; while(!(Registers[0xF1FC]&0x80));
MOV DPTR,#0xF1FC
MOVX A,@DPTR
JNB ACC.7,?C0003
?C0004:
; Registers[0xF1F0]=0x0B;
MOV DPTR,#0xF1F0
MOV A,#0x0B
MOVX @DPTR,A
; Registers[0xF1F1]=0x00;
CLR A
INC DPTR
MOVX @DPTR,A
; Registers[0xF1F2]=0x60;
INC DPTR
MOV A,#0x60
MOVX @DPTR,A
; Registers[0xF1F3]=0x00;
INC DPTR
MOV A,#0x00
MOVX @DPTR,A
; Registers[0xF1F5]=0x6C;
MOV DPTR,#0xF1F5
MOV A,#0x6C
MOVX @DPTR,A
; Registers[0xF1F9]=0x00;
CLR A
MOV DPTR,#0xF1F9
MOVX @DPTR,A
; Registers[0xF1FA]=0xA0;
INC DPTR
MOV A,#0xA0
MOVX @DPTR,A
; Registers[0xF1FB]=0x00;
INC DPTR
MOV A,#0x00
MOVX @DPTR,A
; Registers[0xF1FC]=0xE0;
INC DPTR
MOV A,#0xE0
MOVX @DPTR,A
; Registers[0xF1FD]=0x90;
MOV DPTR,#0xF1FD
MOV A,#0x90
MOVX @DPTR,A
ENDM
SWITCH2 MACRO ; Switch to Memory Bank #2
; Registers[0xF1F0]=0x0B;
MOV DPTR,#0xF1F0
MOV A,#0x0B
MOVX @DPTR,A
; Registers[0xF1F1]=0x00;
CLR A
INC DPTR
MOVX @DPTR,A
; Registers[0xF1F2]=0x80;
INC DPTR
MOV A,#0x80
MOVX @DPTR,A
; Registers[0xF1F3]=0x00;
INC DPTR
MOV A,#0x00
MOVX @DPTR,A
; Registers[0xF1F5]=0x6C;
MOV DPTR,#0xF1F5
MOV A,#0x6C
MOVX @DPTR,A
; Registers[0xF1F9]=0x00;
CLR A
MOV DPTR,#0xF1F9
MOVX @DPTR,A
; Registers[0xF1FA]=0x80;
INC DPTR
MOV A,#0x80
MOVX @DPTR,A
; Registers[0xF1FB]=0x00;
INC DPTR
MOV A,#0x00
MOVX @DPTR,A
; Registers[0xF1FC]=0xE0;
INC DPTR
MOV A,#0xE0
MOVX @DPTR,A
; Registers[0xF1FD]=0x90;
INC DPTR
MOV A,#0x90
MOVX @DPTR,A
; while(!(Registers[0xF1FC]&0x80));
?C0005:
MOV DPTR,#0xF1FC
MOVX A,@DPTR
JNB ACC.7,?C0005
?C0006:
; Registers[0xF1F0]=0x0B;
MOV DPTR,#0xF1F0
MOV A,#0x0B
MOVX @DPTR,A
; Registers[0xF1F1]=0x00;
CLR A
INC DPTR
MOVX @DPTR,A
; Registers[0xF1F2]=0xA0;
INC DPTR
MOV A,#0xA0
MOVX @DPTR,A
; Registers[0xF1F3]=0x00;
INC DPTR
MOV A,#0x00
MOVX @DPTR,A
; Registers[0xF1F5]=0x6C;
MOV DPTR,#0xF1F5
MOV A,#0x6C
MOVX @DPTR,A
; Registers[0xF1F9]=0x00;
CLR A
MOV DPTR,#0xF1F9
MOVX @DPTR,A
; Registers[0xF1FA]=0xA0;
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