📄 zong.rpt
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-- Equation name is 'A12', type is output
A12 = DFFE( A11 $ GND, !A5, VCC, VCC, VCC);
-- Node name is 'data' = '|clockmgdf:16|74164:14|QA'
-- Equation name is 'data', type is output
data = DFFE( _LC085 $ GND, A5, VCC, VCC, VCC);
-- Node name is '|addrlogic:2|7474:1|:9' = '|addrlogic:2|7474:1|1Q'
-- Equation name is '_LC094', type is buried
_LC094 = DFFE( A12 $ GND, A5, VCC, VCC, VCC);
-- Node name is '|addrlogic:2|7474:1|:10' = '|addrlogic:2|7474:1|2Q'
-- Equation name is '_LC114', type is buried
_LC114 = DFFE( _LC110 $ data, A5, VCC, VCC, VCC);
-- Node name is '|addrlogic:2|7474:17|:9' = '|addrlogic:2|7474:17|1Q'
-- Equation name is '_LC110', type is buried
_LC110 = DFFE( _LC122 $ GND, !A5, VCC, VCC, VCC);
-- Node name is '|addrlogic:2|7474:18|:9' = '|addrlogic:2|7474:18|1Q'
-- Equation name is '_LC122', type is buried
_LC122 = DFFE( data $ GND, A5, VCC, VCC, VCC);
-- Node name is '|clockmgdf:16|74161:4|p74161:sub|:9' = '|clockmgdf:16|74161:4|p74161:sub|QA'
-- Equation name is '_LC125', type is buried
_LC125 = TFFE( VCC, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is '|clockmgdf:16|74161:4|p74161:sub|:8' = '|clockmgdf:16|74161:4|p74161:sub|QB'
-- Equation name is '_LC103', type is buried
_LC103 = DFFE( _EQ006 $ !_LC125, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = _LC111 & _LC112 & _LC125
# !_LC103;
-- Node name is '|clockmgdf:16|74161:4|p74161:sub|:7' = '|clockmgdf:16|74161:4|p74161:sub|QC'
-- Equation name is '_LC112', type is buried
_LC112 = TFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC103 & _LC125;
-- Node name is '|clockmgdf:16|74161:4|p74161:sub|:6' = '|clockmgdf:16|74161:4|p74161:sub|QD'
-- Equation name is '_LC111', type is buried
_LC111 = TFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = _LC103 & !_LC111 & _LC112 & _LC125;
-- Node name is '|clockmgdf:16|74161:16|p74161:sub|:9' = '|clockmgdf:16|74161:16|p74161:sub|QA'
-- Equation name is '_LC124', type is buried
_LC124 = TFFE( VCC, A5, !_LC093, VCC, VCC);
-- Node name is '|clockmgdf:16|74161:16|p74161:sub|:8' = '|clockmgdf:16|74161:16|p74161:sub|QB'
-- Equation name is '_LC116', type is buried
_LC116 = TFFE( _LC124, A5, !_LC093, VCC, VCC);
-- Node name is '|clockmgdf:16|74161:16|p74161:sub|:7' = '|clockmgdf:16|74161:16|p74161:sub|QC'
-- Equation name is '_LC127', type is buried
_LC127 = TFFE( _EQ009, A5, !_LC093, VCC, VCC);
_EQ009 = _LC116 & _LC124;
-- Node name is '|clockmgdf:16|74161:16|p74161:sub|:6' = '|clockmgdf:16|74161:16|p74161:sub|QD'
-- Equation name is '_LC126', type is buried
_LC126 = TFFE( _EQ010, A5, !_LC093, VCC, VCC);
_EQ010 = _LC116 & _LC124 & _LC127;
-- Node name is '|clockmgdf:16|74161:17|p74161:sub|:9' = '|clockmgdf:16|74161:17|p74161:sub|QA'
-- Equation name is '_LC128', type is buried
_LC128 = TFFE( VCC, _EQ011, !_LC093, VCC, VCC);
_EQ011 = _LC116 & _LC124 & _LC126 & _LC127;
-- Node name is '|clockmgdf:16|74161:17|p74161:sub|:8' = '|clockmgdf:16|74161:17|p74161:sub|QB'
-- Equation name is '_LC119', type is buried
_LC119 = TFFE( _LC128, _EQ012, !_LC093, VCC, VCC);
_EQ012 = _LC116 & _LC124 & _LC126 & _LC127;
-- Node name is '|clockmgdf:16|74164:12|:3' = '|clockmgdf:16|74164:12|QA'
-- Equation name is '_LC109', type is buried
_LC109 = DFFE( _EQ013 $ _LC119, A5, VCC, VCC, VCC);
_EQ013 = !_LC113 & _LC121
# _LC113 & !_LC121;
-- Node name is '|clockmgdf:16|74164:12|:4' = '|clockmgdf:16|74164:12|QB'
-- Equation name is '_LC101', type is buried
_LC101 = DFFE( _LC109 $ GND, A5, VCC, VCC, VCC);
-- Node name is '|clockmgdf:16|74164:12|:5' = '|clockmgdf:16|74164:12|QC'
-- Equation name is '_LC100', type is buried
_LC100 = DFFE( _LC101 $ GND, A5, VCC, VCC, VCC);
-- Node name is '|clockmgdf:16|74164:12|:6' = '|clockmgdf:16|74164:12|QD'
-- Equation name is '_LC108', type is buried
_LC108 = DFFE( _LC100 $ GND, A5, VCC, VCC, VCC);
-- Node name is '|clockmgdf:16|74164:12|:7' = '|clockmgdf:16|74164:12|QE'
-- Equation name is '_LC106', type is buried
_LC106 = DFFE( _LC108 $ GND, A5, VCC, VCC, VCC);
-- Node name is '|clockmgdf:16|74164:12|:8' = '|clockmgdf:16|74164:12|QF'
-- Equation name is '_LC090', type is buried
_LC090 = DFFE( _LC106 $ GND, A5, VCC, VCC, VCC);
-- Node name is '|clockmgdf:16|74164:12|:9' = '|clockmgdf:16|74164:12|QG'
-- Equation name is '_LC102', type is buried
_LC102 = DFFE( _LC090 $ GND, A5, VCC, VCC, VCC);
-- Node name is '|clockmgdf:16|74164:12|:10' = '|clockmgdf:16|74164:12|QH'
-- Equation name is '_LC089', type is buried
_LC089 = DFFE( _LC102 $ GND, A5, VCC, VCC, VCC);
-- Node name is '|clockmgdf:16|74164:13|:3' = '|clockmgdf:16|74164:13|QA'
-- Equation name is '_LC084', type is buried
_LC084 = DFFE( _LC089 $ GND, A5, VCC, VCC, VCC);
-- Node name is '|clockmgdf:16|74164:13|:4' = '|clockmgdf:16|74164:13|QB'
-- Equation name is '_LC088', type is buried
_LC088 = DFFE( _LC084 $ GND, A5, VCC, VCC, VCC);
-- Node name is '|clockmgdf:16|74164:13|:5' = '|clockmgdf:16|74164:13|QC'
-- Equation name is '_LC082', type is buried
_LC082 = DFFE( _LC088 $ GND, A5, VCC, VCC, VCC);
-- Node name is '|clockmgdf:16|74164:13|:6' = '|clockmgdf:16|74164:13|QD'
-- Equation name is '_LC081', type is buried
_LC081 = DFFE( _LC082 $ GND, A5, VCC, VCC, VCC);
-- Node name is '|clockmgdf:16|74164:13|:7' = '|clockmgdf:16|74164:13|QE'
-- Equation name is '_LC091', type is buried
_LC091 = DFFE( _LC081 $ GND, A5, VCC, VCC, VCC);
-- Node name is '|clockmgdf:16|74164:13|:8' = '|clockmgdf:16|74164:13|QF'
-- Equation name is '_LC092', type is buried
_LC092 = DFFE( _LC091 $ GND, A5, VCC, VCC, VCC);
-- Node name is '|clockmgdf:16|74164:13|:9' = '|clockmgdf:16|74164:13|QG'
-- Equation name is '_LC096', type is buried
_LC096 = DFFE( _LC092 $ GND, A5, VCC, VCC, VCC);
-- Node name is '|clockmgdf:16|74164:13|:10' = '|clockmgdf:16|74164:13|QH'
-- Equation name is '_LC085', type is buried
_LC085 = DFFE( _LC096 $ GND, A5, VCC, VCC, VCC);
-- Node name is '|clockmgdf:16|74164:14|:4' = '|clockmgdf:16|74164:14|QB'
-- Equation name is '_LC121', type is buried
_LC121 = DFFE( data $ GND, A5, VCC, VCC, VCC);
-- Node name is '|clockmgdf:16|74164:14|:5' = '|clockmgdf:16|74164:14|QC'
-- Equation name is '_LC098', type is buried
_LC098 = DFFE( _LC121 $ GND, A5, VCC, VCC, VCC);
-- Node name is '|clockmgdf:16|74164:14|:6' = '|clockmgdf:16|74164:14|QD'
-- Equation name is '_LC086', type is buried
_LC086 = DFFE( _LC098 $ GND, A5, VCC, VCC, VCC);
-- Node name is '|clockmgdf:16|74164:14|:7' = '|clockmgdf:16|74164:14|QE'
-- Equation name is '_LC087', type is buried
_LC087 = DFFE( _LC086 $ GND, A5, VCC, VCC, VCC);
-- Node name is '|clockmgdf:16|74164:14|:8' = '|clockmgdf:16|74164:14|QF'
-- Equation name is '_LC093', type is buried
_LC093 = DFFE( _LC087 $ GND, A5, VCC, VCC, VCC);
-- Node name is '|clockmgdf:16|74164:14|:9' = '|clockmgdf:16|74164:14|QG'
-- Equation name is '_LC113', type is buried
_LC113 = DFFE( _LC093 $ GND, A5, VCC, VCC, VCC);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\shiyan\gmsk\zong.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,518K
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