📄 zong.rpt
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** BURIED LOGIC **
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Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(61) 94 F DFFE t 0 0 0 0 2 1 0 |addrlogic:2|7474:1|1Q (|addrlogic:2|7474:1|:9)
- 114 H DFFE t 0 0 0 0 3 1 0 |addrlogic:2|7474:1|2Q (|addrlogic:2|7474:1|:10)
- 110 G DFFE t 0 0 0 0 2 0 1 |addrlogic:2|7474:17|1Q (|addrlogic:2|7474:17|:9)
- 122 H DFFE t 0 0 0 0 2 0 1 |addrlogic:2|7474:18|1Q (|addrlogic:2|7474:18|:9)
- 111 G TFFE + t 0 0 0 0 4 3 2 |clockmgdf:16|74161:4|p74161:sub|QD (|clockmgdf:16|74161:4|p74161:sub|:6)
(71) 112 G TFFE + t 0 0 0 0 2 3 2 |clockmgdf:16|74161:4|p74161:sub|QC (|clockmgdf:16|74161:4|p74161:sub|:7)
- 103 G DFFE + t 0 0 0 0 4 3 3 |clockmgdf:16|74161:4|p74161:sub|QB (|clockmgdf:16|74161:4|p74161:sub|:8)
(79) 125 H TFFE + t 0 0 0 0 0 3 3 |clockmgdf:16|74161:4|p74161:sub|QA (|clockmgdf:16|74161:4|p74161:sub|:9)
(80) 126 H TFFE t 0 0 0 0 5 0 2 |clockmgdf:16|74161:16|p74161:sub|QD (|clockmgdf:16|74161:16|p74161:sub|:6)
- 127 H TFFE t 0 0 0 0 4 0 3 |clockmgdf:16|74161:16|p74161:sub|QC (|clockmgdf:16|74161:16|p74161:sub|:7)
- 116 H TFFE t 0 0 0 0 3 0 4 |clockmgdf:16|74161:16|p74161:sub|QB (|clockmgdf:16|74161:16|p74161:sub|:8)
- 124 H TFFE t 0 0 0 0 2 0 5 |clockmgdf:16|74161:16|p74161:sub|QA (|clockmgdf:16|74161:16|p74161:sub|:9)
- 119 H TFFE t 0 0 0 0 6 0 1 |clockmgdf:16|74161:17|p74161:sub|QB (|clockmgdf:16|74161:17|p74161:sub|:8)
(81) 128 H TFFE t 0 0 0 0 5 0 1 |clockmgdf:16|74161:17|p74161:sub|QA (|clockmgdf:16|74161:17|p74161:sub|:9)
(70) 109 G DFFE t 0 0 0 0 4 0 1 |clockmgdf:16|74164:12|QA (|clockmgdf:16|74164:12|:3)
(65) 101 G DFFE t 0 0 0 0 2 0 1 |clockmgdf:16|74164:12|QB (|clockmgdf:16|74164:12|:4)
- 100 G DFFE t 0 0 0 0 2 0 1 |clockmgdf:16|74164:12|QC (|clockmgdf:16|74164:12|:5)
- 108 G DFFE t 0 0 0 0 2 0 1 |clockmgdf:16|74164:12|QD (|clockmgdf:16|74164:12|:6)
- 106 G DFFE t 0 0 0 0 2 0 1 |clockmgdf:16|74164:12|QE (|clockmgdf:16|74164:12|:7)
- 90 F DFFE t 0 0 0 0 2 0 1 |clockmgdf:16|74164:12|QF (|clockmgdf:16|74164:12|:8)
- 102 G DFFE t 0 0 0 0 2 0 1 |clockmgdf:16|74164:12|QG (|clockmgdf:16|74164:12|:9)
- 89 F DFFE t 0 0 0 0 2 0 1 |clockmgdf:16|74164:12|QH (|clockmgdf:16|74164:12|:10)
- 84 F DFFE t 0 0 0 0 2 0 1 |clockmgdf:16|74164:13|QA (|clockmgdf:16|74164:13|:3)
(57) 88 F DFFE t 0 0 0 0 2 0 1 |clockmgdf:16|74164:13|QB (|clockmgdf:16|74164:13|:4)
- 82 F DFFE t 0 0 0 0 2 0 1 |clockmgdf:16|74164:13|QC (|clockmgdf:16|74164:13|:5)
- 81 F DFFE t 0 0 0 0 2 0 1 |clockmgdf:16|74164:13|QD (|clockmgdf:16|74164:13|:6)
(58) 91 F DFFE t 0 0 0 0 2 0 1 |clockmgdf:16|74164:13|QE (|clockmgdf:16|74164:13|:7)
- 92 F DFFE t 0 0 0 0 2 0 1 |clockmgdf:16|74164:13|QF (|clockmgdf:16|74164:13|:8)
(62) 96 F DFFE t 0 0 0 0 2 0 1 |clockmgdf:16|74164:13|QG (|clockmgdf:16|74164:13|:9)
(55) 85 F DFFE t 0 0 0 0 2 1 0 |clockmgdf:16|74164:13|QH (|clockmgdf:16|74164:13|:10)
- 121 H DFFE t 0 0 0 0 2 0 2 |clockmgdf:16|74164:14|QB (|clockmgdf:16|74164:14|:4)
- 98 G DFFE t 0 0 0 0 2 0 1 |clockmgdf:16|74164:14|QC (|clockmgdf:16|74164:14|:5)
(56) 86 F DFFE t 0 0 0 0 2 0 1 |clockmgdf:16|74164:14|QD (|clockmgdf:16|74164:14|:6)
- 87 F DFFE t 0 0 0 0 2 0 1 |clockmgdf:16|74164:14|QE (|clockmgdf:16|74164:14|:7)
(60) 93 F DFFE t 0 0 0 0 2 0 7 |clockmgdf:16|74164:14|QF (|clockmgdf:16|74164:14|:8)
- 113 H DFFE t 0 0 0 0 2 0 1 |clockmgdf:16|74164:14|QG (|clockmgdf:16|74164:14|:9)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\shiyan\gmsk\zong.rpt
zong
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'F':
Logic cells placed in LAB 'F'
+----------------------------- LC94 |addrlogic:2|7474:1|1Q
| +--------------------------- LC83 A7
| | +------------------------- LC90 |clockmgdf:16|74164:12|QF
| | | +----------------------- LC89 |clockmgdf:16|74164:12|QH
| | | | +--------------------- LC84 |clockmgdf:16|74164:13|QA
| | | | | +------------------- LC88 |clockmgdf:16|74164:13|QB
| | | | | | +----------------- LC82 |clockmgdf:16|74164:13|QC
| | | | | | | +--------------- LC81 |clockmgdf:16|74164:13|QD
| | | | | | | | +------------- LC91 |clockmgdf:16|74164:13|QE
| | | | | | | | | +----------- LC92 |clockmgdf:16|74164:13|QF
| | | | | | | | | | +--------- LC96 |clockmgdf:16|74164:13|QG
| | | | | | | | | | | +------- LC85 |clockmgdf:16|74164:13|QH
| | | | | | | | | | | | +----- LC86 |clockmgdf:16|74164:14|QD
| | | | | | | | | | | | | +--- LC87 |clockmgdf:16|74164:14|QE
| | | | | | | | | | | | | | +- LC93 |clockmgdf:16|74164:14|QF
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'F'
LC | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'F':
LC94 -> - * - - - - - - - - - - - - - | - - - - - * - - | <-- |addrlogic:2|7474:1|1Q
LC83 -> - * - - - - - - - - - - - - - | - - - - - * - - | <-- A7
LC89 -> - - - - * - - - - - - - - - - | - - - - - * - - | <-- |clockmgdf:16|74164:12|QH
LC84 -> - - - - - * - - - - - - - - - | - - - - - * - - | <-- |clockmgdf:16|74164:13|QA
LC88 -> - - - - - - * - - - - - - - - | - - - - - * - - | <-- |clockmgdf:16|74164:13|QB
LC82 -> - - - - - - - * - - - - - - - | - - - - - * - - | <-- |clockmgdf:16|74164:13|QC
LC81 -> - - - - - - - - * - - - - - - | - - - - - * - - | <-- |clockmgdf:16|74164:13|QD
LC91 -> - - - - - - - - - * - - - - - | - - - - - * - - | <-- |clockmgdf:16|74164:13|QE
LC92 -> - - - - - - - - - - * - - - - | - - - - - * - - | <-- |clockmgdf:16|74164:13|QF
LC96 -> - - - - - - - - - - - * - - - | - - - - - * - - | <-- |clockmgdf:16|74164:13|QG
LC86 -> - - - - - - - - - - - - - * - | - - - - - * - - | <-- |clockmgdf:16|74164:14|QD
LC87 -> - - - - - - - - - - - - - - * | - - - - - * - - | <-- |clockmgdf:16|74164:14|QE
Pin
83 -> - - - - - - - - - - - - - - - | - - - - - - - - | <-- clk
LC97 -> * * * * * * * * * * * * * * * | - - - - - * * * | <-- A5
LC115-> - * - - - - - - - - - - - - - | - - - - - * - - | <-- A6
LC117-> * - - - - - - - - - - - - - - | - - - - - * - - | <-- A12
LC106-> - - * - - - - - - - - - - - - | - - - - - * - - | <-- |clockmgdf:16|74164:12|QE
LC102-> - - - * - - - - - - - - - - - | - - - - - * - - | <-- |clockmgdf:16|74164:12|QG
LC98 -> - - - - - - - - - - - - * - - | - - - - - * - - | <-- |clockmgdf:16|74164:14|QC
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\shiyan\gmsk\zong.rpt
zong
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+------------------------------- LC110 |addrlogic:2|7474:17|1Q
| +----------------------------- LC105 A3
| | +--------------------------- LC99 A4
| | | +------------------------- LC97 A5
| | | | +----------------------- LC107 A11
| | | | | +--------------------- LC111 |clockmgdf:16|74161:4|p74161:sub|QD
| | | | | | +------------------- LC112 |clockmgdf:16|74161:4|p74161:sub|QC
| | | | | | | +----------------- LC103 |clockmgdf:16|74161:4|p74161:sub|QB
| | | | | | | | +--------------- LC109 |clockmgdf:16|74164:12|QA
| | | | | | | | | +------------- LC101 |clockmgdf:16|74164:12|QB
| | | | | | | | | | +----------- LC100 |clockmgdf:16|74164:12|QC
| | | | | | | | | | | +--------- LC108 |clockmgdf:16|74164:12|QD
| | | | | | | | | | | | +------- LC106 |clockmgdf:16|74164:12|QE
| | | | | | | | | | | | | +----- LC102 |clockmgdf:16|74164:12|QG
| | | | | | | | | | | | | | +--- LC98 |clockmgdf:16|74164:14|QC
| | | | | | | | | | | | | | | +- LC104 data
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'G'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G':
LC105-> - * * * - - - - - - - - - - - - | - - - - - - * - | <-- A3
LC99 -> - - * * - - - - - - - - - - - - | - - - - - - * - | <-- A4
LC97 -> * - - * * - - - * * * * * * * * | - - - - - * * * | <-- A5
LC111-> - * * * - * - * - - - - - - - - | - - - - - - * - | <-- |clockmgdf:16|74161:4|p74161:sub|QD
LC112-> - * * * - * * * - - - - - - - - | - - - - - - * - | <-- |clockmgdf:16|74161:4|p74161:sub|QC
LC103-> - * * * - * * * - - - - - - - - | - - - - - - * - | <-- |clockmgdf:16|74161:4|p74161:sub|QB
LC109-> - - - - - - - - - * - - - - - - | - - - - - - * - | <-- |clockmgdf:16|74164:12|QA
LC101-> - - - - - - - - - - * - - - - - | - - - - - - * - | <-- |clockmgdf:16|74164:12|QB
LC100-> - - - - - - - - - - - * - - - - | - - - - - - * - | <-- |clockmgdf:16|74164:12|QC
LC108-> - - - - - - - - - - - - * - - - | - - - - - - * - | <-- |clockmgdf:16|74164:12|QD
Pin
83 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- clk
LC122-> * - - - - - - - - - - - - - - - | - - - - - - * - | <-- |addrlogic:2|7474:18|1Q
LC120-> - - - - * - - - - - - - - - - - | - - - - - - * - | <-- A10
LC125-> - * * * - * * * - - - - - - - - | - - - - - - * - | <-- |clockmgdf:16|74161:4|p74161:sub|QA
LC119-> - - - - - - - - * - - - - - - - | - - - - - - * - | <-- |clockmgdf:16|74161:17|p74161:sub|QB
LC90 -> - - - - - - - - - - - - - * - - | - - - - - - * - | <-- |clockmgdf:16|74164:12|QF
LC85 -> - - - - - - - - - - - - - - - * | - - - - - - * - | <-- |clockmgdf:16|74164:13|QH
LC121-> - - - - - - - - * - - - - - * - | - - - - - - * - | <-- |clockmgdf:16|74164:14|QB
LC113-> - - - - - - - - * - - - - - - - | - - - - - - * - | <-- |clockmgdf:16|74164:14|QG
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\shiyan\gmsk\zong.rpt
zong
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+------------------------------- LC114 |addrlogic:2|7474:1|2Q
| +----------------------------- LC122 |addrlogic:2|7474:18|1Q
| | +--------------------------- LC115 A6
| | | +------------------------- LC118 A8
| | | | +----------------------- LC123 A9
| | | | | +--------------------- LC120 A10
| | | | | | +------------------- LC117 A12
| | | | | | | +----------------- LC125 |clockmgdf:16|74161:4|p74161:sub|QA
| | | | | | | | +--------------- LC126 |clockmgdf:16|74161:16|p74161:sub|QD
| | | | | | | | | +------------- LC127 |clockmgdf:16|74161:16|p74161:sub|QC
| | | | | | | | | | +----------- LC116 |clockmgdf:16|74161:16|p74161:sub|QB
| | | | | | | | | | | +--------- LC124 |clockmgdf:16|74161:16|p74161:sub|QA
| | | | | | | | | | | | +------- LC119 |clockmgdf:16|74161:17|p74161:sub|QB
| | | | | | | | | | | | | +----- LC128 |clockmgdf:16|74161:17|p74161:sub|QA
| | | | | | | | | | | | | | +--- LC121 |clockmgdf:16|74164:14|QB
| | | | | | | | | | | | | | | +- LC113 |clockmgdf:16|74164:14|QG
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'H'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC114-> - - - * - - - - - - - - - - - - | - - - - - - - * | <-- |addrlogic:2|7474:1|2Q
LC118-> - - - - * - - - - - - - - - - - | - - - - - - - * | <-- A8
LC123-> - - - - - * - - - - - - - - - - | - - - - - - - * | <-- A9
LC126-> - - - - - - - - * - - - * * - - | - - - - - - - * | <-- |clockmgdf:16|74161:16|p74161:sub|QD
LC127-> - - - - - - - - * * - - * * - - | - - - - - - - * | <-- |clockmgdf:16|74161:16|p74161:sub|QC
LC116-> - - - - - - - - * * * - * * - - | - - - - - - - * | <-- |clockmgdf:16|74161:16|p74161:sub|QB
LC124-> - - - - - - - - * * * * * * - - | - - - - - - - * | <-- |clockmgdf:16|74161:16|p74161:sub|QA
LC128-> - - - - - - - - - - - - * * - - | - - - - - - - * | <-- |clockmgdf:16|74161:17|p74161:sub|QA
Pin
83 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- clk
LC110-> * - - - - - - - - - - - - - - - | - - - - - - - * | <-- |addrlogic:2|7474:17|1Q
LC97 -> * * * * * * * - * * * * - - * * | - - - - - * * * | <-- A5
LC107-> - - - - - - * - - - - - - - - - | - - - - - - - * | <-- A11
LC93 -> - - - - - - - - * * * * * * - * | - - - - - - - * | <-- |clockmgdf:16|74164:14|QF
LC104-> * * - - - - - - - - - - - - * - | - - - - - - - * | <-- data
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\shiyan\gmsk\zong.rpt
zong
** EQUATIONS **
clk : INPUT;
-- Node name is 'A3' = '|clockmgdf:16|74161:7|p74161:sub|QA'
-- Equation name is 'A3', type is output
A3 = TFFE( VCC, _EQ001, VCC, VCC, VCC);
_EQ001 = _LC103 & _LC111 & _LC112 & _LC125;
-- Node name is 'A4' = '|clockmgdf:16|74161:7|p74161:sub|QB'
-- Equation name is 'A4', type is output
A4 = TFFE( A3, _EQ002, VCC, VCC, VCC);
_EQ002 = _LC103 & _LC111 & _LC112 & _LC125;
-- Node name is 'A5' = '|clockmgdf:16|74161:7|p74161:sub|QC'
-- Equation name is 'A5', type is output
A5 = TFFE( _EQ003, _EQ004, VCC, VCC, VCC);
_EQ003 = A3 & A4;
_EQ004 = _LC103 & _LC111 & _LC112 & _LC125;
-- Node name is 'A6' = '|addrlogic:2|74169:4|Q0'
-- Equation name is 'A6', type is output
A6 = TFFE( VCC, !A5, VCC, VCC, VCC);
-- Node name is 'A7' = '|addrlogic:2|74169:4|Q1'
-- Equation name is 'A7', type is output
A7 = DFFE( _EQ005 $ _LC094, !A5, VCC, VCC, VCC);
_EQ005 = A6 & A7
# !A6 & !A7;
-- Node name is 'A8' = '|addrlogic:2|74164:9|QA'
-- Equation name is 'A8', type is output
A8 = DFFE( _LC114 $ GND, !A5, VCC, VCC, VCC);
-- Node name is 'A9' = '|addrlogic:2|74164:9|QB'
-- Equation name is 'A9', type is output
A9 = DFFE( A8 $ GND, !A5, VCC, VCC, VCC);
-- Node name is 'A10' = '|addrlogic:2|74164:9|QC'
-- Equation name is 'A10', type is output
A10 = DFFE( A9 $ GND, !A5, VCC, VCC, VCC);
-- Node name is 'A11' = '|addrlogic:2|74164:9|QD'
-- Equation name is 'A11', type is output
A11 = DFFE( A10 $ GND, !A5, VCC, VCC, VCC);
-- Node name is 'A12' = '|addrlogic:2|74164:9|QE'
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