addrlogic.map.qmsg

基于matlab的gmsk信号的调制

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 04 23:00:50 2008 " "Info: Processing started: Wed Jun 04 23:00:50 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off addrlogic -c addrlogic " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off addrlogic -c addrlogic" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "addrlogic.gdf 1 1 " "Warning: Using design file addrlogic.gdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 addrlogic " "Info: Found entity 1: addrlogic" {  } { { "addrlogic.gdf" "" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "addrlogic " "Info: Elaborating entity \"addrlogic\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D0 74169 4 " "Warning: Port \"D0\" of type 74169 and instance \"4\" is missing source signal" {  } { { "addrlogic.gdf" "" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { { 120 496 600 296 "4" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D1 74169 4 " "Warning: Port \"D1\" of type 74169 and instance \"4\" is missing source signal" {  } { { "addrlogic.gdf" "" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { { 120 496 600 296 "4" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D2 74169 4 " "Warning: Port \"D2\" of type 74169 and instance \"4\" is missing source signal" {  } { { "addrlogic.gdf" "" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { { 120 496 600 296 "4" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D3 74169 4 " "Warning: Port \"D3\" of type 74169 and instance \"4\" is missing source signal" {  } { { "addrlogic.gdf" "" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { { 120 496 600 296 "4" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "2PRN 7474 18 " "Warning: Port \"2PRN\" of type 7474 and instance \"18\" is missing source signal" {  } { { "addrlogic.gdf" "" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { { 896 160 280 1056 "18" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "2D 7474 18 " "Warning: Port \"2D\" of type 7474 and instance \"18\" is missing source signal" {  } { { "addrlogic.gdf" "" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { { 896 160 280 1056 "18" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "2CLRN 7474 18 " "Warning: Port \"2CLRN\" of type 7474 and instance \"18\" is missing source signal" {  } { { "addrlogic.gdf" "" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { { 896 160 280 1056 "18" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "2CLK 7474 18 " "Warning: Port \"2CLK\" of type 7474 and instance \"18\" is missing source signal" {  } { { "addrlogic.gdf" "" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { { 896 160 280 1056 "18" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "2PRN 7474 17 " "Warning: Port \"2PRN\" of type 7474 and instance \"17\" is missing source signal" {  } { { "addrlogic.gdf" "" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { { 912 464 584 1072 "17" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "2D 7474 17 " "Warning: Port \"2D\" of type 7474 and instance \"17\" is missing source signal" {  } { { "addrlogic.gdf" "" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { { 912 464 584 1072 "17" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "2CLRN 7474 17 " "Warning: Port \"2CLRN\" of type 7474 and instance \"17\" is missing source signal" {  } { { "addrlogic.gdf" "" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { { 912 464 584 1072 "17" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "2CLK 7474 17 " "Warning: Port \"2CLK\" of type 7474 and instance \"17\" is missing source signal" {  } { { "addrlogic.gdf" "" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { { 912 464 584 1072 "17" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/others/maxplus2/74169.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/others/maxplus2/74169.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74169 " "Info: Found entity 1: 74169" {  } { { "74169.bdf" "" { Schematic "c:/altera/quartus51/libraries/others/maxplus2/74169.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74169 74169:4 " "Info: Elaborating entity \"74169\" for hierarchy \"74169:4\"" {  } { { "addrlogic.gdf" "4" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { { 120 496 600 296 "4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/others/maxplus2/7474.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/others/maxplus2/7474.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 7474 " "Info: Found entity 1: 7474" {  } { { "7474.bdf" "" { Schematic "c:/altera/quartus51/libraries/others/maxplus2/7474.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7474 7474:1 " "Info: Elaborating entity \"7474\" for hierarchy \"7474:1\"" {  } { { "addrlogic.gdf" "1" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { { 120 184 304 280 "1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/others/maxplus2/74164.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/others/maxplus2/74164.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74164 " "Info: Found entity 1: 74164" {  } { { "74164.bdf" "" { Schematic "c:/altera/quartus51/libraries/others/maxplus2/74164.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74164 74164:9 " "Info: Elaborating entity \"74164\" for hierarchy \"74164:9\"" {  } { { "addrlogic.gdf" "9" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { { 464 440 560 640 "9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/others/maxplus2/7404.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/others/maxplus2/7404.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 7404 " "Info: Found entity 1: 7404" {  } { { "7404.bdf" "" { Schematic "c:/altera/quartus51/libraries/others/maxplus2/7404.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7404 7404:16 " "Info: Elaborating entity \"7404\" for hierarchy \"7404:16\"" {  } { { "addrlogic.gdf" "16" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { { 752 448 496 784 "16" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/others/maxplus2/7486.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/others/maxplus2/7486.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 7486 " "Info: Found entity 1: 7486" {  } { { "7486.bdf" "" { Schematic "c:/altera/quartus51/libraries/others/maxplus2/7486.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7486 7486:19 " "Info: Elaborating entity \"7486\" for hierarchy \"7486:19\"" {  } { { "addrlogic.gdf" "19" { Schematic "D:/GMSK课设/别人的GMSK/报告2/VHDL/addrlogic.gdf" { { 944 736 800 984 "19" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clock " "Info: Promoted clock signal driven by pin \"clock\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0}  } {  } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "20 " "Info: Implemented 20 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "7 " "Info: Implemented 7 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_MCELLS" "11 " "Info: Implemented 11 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 13 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 04 23:00:52 2008 " "Info: Processing ended: Wed Jun 04 23:00:52 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}