addrlogic.map.eqn

基于matlab的gmsk信号的调制

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--C1_3 is 74169:4|3
C1_3_reg_input = VCC;
C1_3 = TFFE(C1_3_reg_input, !GLOBAL(clock), , , );


--B3_9 is 7474:18|9
B3_9_or_out = data;
B3_9_reg_input = B3_9_or_out;
B3_9 = DFFE(B3_9_reg_input, GLOBAL(clock), , , );


--B2_9 is 7474:17|9
B2_9_or_out = B3_9;
B2_9_reg_input = B2_9_or_out;
B2_9 = DFFE(B2_9_reg_input, !GLOBAL(clock), , , );


--B1_10 is 7474:1|10
B1_10_or_out = data;
B1_10_reg_input = B2_9 $ B1_10_or_out;
B1_10 = DFFE(B1_10_reg_input, GLOBAL(clock), , , );


--D1_3 is 74164:9|3
D1_3_or_out = B1_10;
D1_3_reg_input = D1_3_or_out;
D1_3 = DFFE(D1_3_reg_input, !GLOBAL(clock), , , );


--D1_4 is 74164:9|4
D1_4_or_out = D1_3;
D1_4_reg_input = D1_4_or_out;
D1_4 = DFFE(D1_4_reg_input, !GLOBAL(clock), , , );


--D1_5 is 74164:9|5
D1_5_or_out = D1_4;
D1_5_reg_input = D1_5_or_out;
D1_5 = DFFE(D1_5_reg_input, !GLOBAL(clock), , , );


--D1_6 is 74164:9|6
D1_6_or_out = D1_5;
D1_6_reg_input = D1_6_or_out;
D1_6 = DFFE(D1_6_reg_input, !GLOBAL(clock), , , );


--D1_7 is 74164:9|7
D1_7_or_out = D1_6;
D1_7_reg_input = D1_7_or_out;
D1_7 = DFFE(D1_7_reg_input, !GLOBAL(clock), , , );


--B1_9 is 7474:1|9
B1_9_or_out = D1_7;
B1_9_reg_input = B1_9_or_out;
B1_9 = DFFE(B1_9_reg_input, GLOBAL(clock), , , );


--C1_15 is 74169:4|15
C1_15_p1_out = C1_3 & !B1_9;
C1_15_p2_out = !C1_3 & B1_9;
C1_15_or_out = C1_15_p1_out # C1_15_p2_out;
C1_15_reg_input = !C1_15_or_out;
C1_15 = TFFE(C1_15_reg_input, !GLOBAL(clock), , , );


--clock is clock
--operation mode is input

clock = INPUT();


--data is data
--operation mode is input

data = INPUT();


--A6 is A6
--operation mode is output

A6 = OUTPUT(C1_3);


--A8 is A8
--operation mode is output

A8 = OUTPUT(D1_3);


--A9 is A9
--operation mode is output

A9 = OUTPUT(D1_4);


--A10 is A10
--operation mode is output

A10 = OUTPUT(D1_5);


--A11 is A11
--operation mode is output

A11 = OUTPUT(D1_6);


--A12 is A12
--operation mode is output

A12 = OUTPUT(D1_7);


--A7 is A7
--operation mode is output

A7 = OUTPUT(C1_15);