addrlogic.tan.rpt

基于matlab的gmsk信号的调制

+-----------------------------------------------------------------+
; tsu                                                             ;
+-------+--------------+------------+------+-----------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To        ; To Clock ;
+-------+--------------+------------+------+-----------+----------+
; N/A   ; None         ; 3.300 ns   ; data ; 7474:18|9 ; clock    ;
; N/A   ; None         ; 3.300 ns   ; data ; 7474:1|10 ; clock    ;
+-------+--------------+------------+------+-----------+----------+


+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+------------+-----+------------+
; Slack ; Required tco ; Actual tco ; From       ; To  ; From Clock ;
+-------+--------------+------------+------------+-----+------------+
; N/A   ; None         ; 2.800 ns   ; 74169:4|15 ; A7  ; clock      ;
; N/A   ; None         ; 2.800 ns   ; 74164:9|7  ; A12 ; clock      ;
; N/A   ; None         ; 2.800 ns   ; 74164:9|6  ; A11 ; clock      ;
; N/A   ; None         ; 2.800 ns   ; 74164:9|5  ; A10 ; clock      ;
; N/A   ; None         ; 2.800 ns   ; 74164:9|4  ; A9  ; clock      ;
; N/A   ; None         ; 2.800 ns   ; 74164:9|3  ; A8  ; clock      ;
; N/A   ; None         ; 2.800 ns   ; 74169:4|3  ; A6  ; clock      ;
+-------+--------------+------------+------------+-----+------------+


+-----------------------------------------------------------------------+
; th                                                                    ;
+---------------+-------------+-----------+------+-----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To        ; To Clock ;
+---------------+-------------+-----------+------+-----------+----------+
; N/A           ; None        ; -0.800 ns ; data ; 7474:18|9 ; clock    ;
; N/A           ; None        ; -0.800 ns ; data ; 7474:1|10 ; clock    ;
+---------------+-------------+-----------+------+-----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Wed Jun 04 23:00:57 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off addrlogic -c addrlogic
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" has Internal fmax of 87.72 MHz between source register "7474:1|9" and destination register "74169:4|15" (period= 11.4 ns)
    Info: + Longest register to register delay is 3.600 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4; Fanout = 2; REG Node = '7474:1|9'
        Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.600 ns; Loc. = LC1; Fanout = 2; REG Node = '74169:4|15'
        Info: Total cell delay = 2.600 ns ( 72.22 % )
        Info: Total interconnect delay = 1.000 ns ( 27.78 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clock" to destination register is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 11; CLK Node = 'clock'
            Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC1; Fanout = 2; REG Node = '74169:4|15'
            Info: Total cell delay = 1.300 ns ( 100.00 % )
        Info: - Longest clock path from clock "clock" to source register is 1.300 ns
            Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 11; CLK Node = 'clock'
            Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC4; Fanout = 2; REG Node = '7474:1|9'
            Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Micro setup delay of destination is 0.800 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: tsu for register "7474:18|9" (data pin = "data", clock pin = "clock") is 3.300 ns
    Info: + Longest pin to register delay is 3.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_21; Fanout = 2; PIN Node = 'data'
        Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC11; Fanout = 1; REG Node = '7474:18|9'
        Info: Total cell delay = 2.800 ns ( 73.68 % )
        Info: Total interconnect delay = 1.000 ns ( 26.32 % )
    Info: + Micro setup delay of destination is 0.800 ns
    Info: - Shortest clock path from clock "clock" to destination register is 1.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 11; CLK Node = 'clock'
        Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC11; Fanout = 1; REG Node = '7474:18|9'
        Info: Total cell delay = 1.300 ns ( 100.00 % )
Info: tco from clock "clock" to destination pin "A7" through register "74169:4|15" is 2.800 ns
    Info: + Longest clock path from clock "clock" to source register is 1.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 11; CLK Node = 'clock'
        Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC1; Fanout = 2; REG Node = '74169:4|15'
        Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.300 ns
    Info: + Longest register to pin delay is 0.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1; Fanout = 2; REG Node = '74169:4|15'
        Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'A7'
        Info: Total cell delay = 0.200 ns ( 100.00 % )
Info: th for register "7474:18|9" (data pin = "data", clock pin = "clock") is -0.800 ns
    Info: + Longest clock path from clock "clock" to destination register is 1.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 11; CLK Node = 'clock'
        Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC11; Fanout = 1; REG Node = '7474:18|9'
        Info: Total cell delay = 1.300 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 1.700 ns
    Info: - Shortest pin to register delay is 3.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_21; Fanout = 2; PIN Node = 'data'
        Info: 2: + IC(1.000 ns) + CELL(2.600 ns) = 3.800 ns; Loc. = LC11; Fanout = 1; REG Node = '7474:18|9'
        Info: Total cell delay = 2.800 ns ( 73.68 % )
        Info: Total interconnect delay = 1.000 ns ( 26.32 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Wed Jun 04 23:00:57 2008
    Info: Elapsed time: 00:00:01