📄 uf32reg.h
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#define QC1SR *(volatile UINT8*)(IQUE_BASE+0x09) /* IQUE ch 1 Status Register */
#define QnESF 5
#define QnFSF 6
#define QC1SZB *(volatile UINT8*)(IQUE_BASE+0x0A) /* IQUE ch 1 Size/base Register */
//.................................................................................
#define QC1REQ *(volatile UINT8*)(IQUE_BASE+0x0B) /* IQUE ch 1 Request Mapping Register */
#define kQCREQUSBRx 0
#define kQCREQUSBTx 1
#define kQCREQATARx 2
#define kQCREQATATx 3
#define kQCREQCFRx 4
#define kQCREQCFTx 5
#define kQCREQNone 0xff
#define QC2DR *(volatile UINT16*)(IQUE_BASE+0x0C) /* IQUE ch 2 data Register */
#define QC2DR_H *(volatile UINT8*)(IQUE_BASE+0x0C)
#define QC2BP *(volatile UINT16*)(IQUE_BASE+0x0E) /* IQUE ch 2 Begin pointer Register */
#define QC2EP *(volatile UINT16*)(IQUE_BASE+0x10) /* IQUE ch 2 End pointer Register */
#define QC2CR *(volatile UINT8*)(IQUE_BASE+0x12) /* IQUE ch 2 Control Register */
#define QC2SR *(volatile UINT8*)(IQUE_BASE+0x13) /* IQUE ch 2 Status Register */
#define QC2SZB *(volatile UINT8*)(IQUE_BASE+0x14) /* IQUE ch 2 Size/base Register */
#define QC2REQ *(volatile UINT8*)(IQUE_BASE+0x15) /* IQUE ch 2 Request Mapping Register */
#define QC3DR *(volatile UINT16*)(IQUE_BASE+0x16) /* IQUE ch 3 data Register */
#define QC3BP *(volatile UINT16*)(IQUE_BASE+0x18) /* IQUE ch 3 Begin pointer Register */
#define QC3EP *(volatile UINT16*)(IQUE_BASE+0x1A) /* IQUE ch 3 End pointer Register */
#define QC3CR *(volatile UINT8*)(IQUE_BASE+0x1C) /* IQUE ch 3 Control Register */
#define QC3SR *(volatile UINT8*)(IQUE_BASE+0x1D) /* IQUE ch 3 Status Register */
#define QC3SZB *(volatile UINT8*)(IQUE_BASE+0x1E) /* IQUE ch 3 Size/base Register */
#define QC3REQ *(volatile UINT8*)(IQUE_BASE+0x1F) /* IQUE ch 3 Request Mapping Register */
#define QC4DR *(volatile UINT16*)(IQUE_BASE+0x20) /* IQUE ch 4 data Register */
#define QC4BP *(volatile UINT16*)(IQUE_BASE+0x22) /* IQUE ch 4 Begin pointer Register */
#define QC4EP *(volatile UINT16*)(IQUE_BASE+0x24) /* IQUE ch 4 End pointer Register */
#define QC4CR *(volatile UINT8*)(IQUE_BASE+0x26) /* IQUE ch 4 Control Register */
#define QC4SR *(volatile UINT8*)(IQUE_BASE+0x27) /* IQUE ch 4 Status Register */
#define QC4SZB *(volatile UINT8*)(IQUE_BASE+0x28) /* IQUE ch 4 Size/base Register */
#define QC4REQ *(volatile UINT8*)(IQUE_BASE+0x29) /* IQUE ch 4 Request Mapping Register */
//.................................................................................
#define QC12DCR *(volatile UINT8*)(IQUE_BASE+0x2A) /* QC12 double buffer control Register */
#define SBTE 4
#define DBTIE 3
#define DBEIE 2
#define DBFIE 1
#define DBRST 0
#define QC34DCR *(volatile UINT8*)(IQUE_BASE+0x2B) /* QC34 double buffer control Register */
#define QC12DSR *(volatile UINT8*)(IQUE_BASE+0x2C) /* QC12 double buffer status Register */
#define DBEIF 6
#define QC34DSR *(volatile UINT8*)(IQUE_BASE+0x2D) /* QC34 double buffer status Register */
#define QCDCT34 *(volatile UINT8*)(IQUE_BASE+0x2E) /* QC double buffer counter Register */
#define QCDCT12 *(volatile UINT8*)(IQUE_BASE+0x2F) /* QC double buffer counter Register */
//.................................................................................
#define QC12DTR *(volatile UINT8*)(IQUE_BASE+0x30) /* QC double buffer Test Register */
#define RXRD 7 // Receive Resend
#define RXDA 6 // Receive acknowledge
#define TXRD 5 // Transmit Resend
#define TXDA 4 // Transmit acknowledge
#define DRHE 1 // Receive handshake Enable
#define DTHE 0 // Transmit handshake Enable
#define QC34DTR *(volatile UINT8*)(IQUE_BASE+0x31) /* QC double buffer Test Register */
/*USB section*/
#define UMCR *(volatile UINT16*)(USB2_BASE+0x00) /* USB Module Control Register */
#define UMCRH *(volatile UINT8*)(USB2_BASE+0x00) /* USB Module Control Register */
//.................................................................................
#define UMCRL *(volatile UINT8*)(USB2_BASE+0x01) /* USB Module Control Register */
#define MCE 14 // Module Clock Enable
#define MRST 13 // Module Reset
#define RESUME 12 // Remote wakeup request
#define SPHY 11 // Suspend PHY
#define SDSUP 4 // Set descriptor support
#define EXSPD 3 // Expected Speed
#define RWUC 2 // Remote wakeup capable
#define SPWR 1 // Self Powered
#define SCSUP 0 // Synch Frame command support
//.................................................................................
#define UMSR1 *(volatile UINT16*)(USB2_BASE+0x02) /* USB Module Status Register */
#define USSC 12 // Suspend status change
#define URSC 11 // Reset status change
#define ENUMD 10 // Enumeration Done
#define PHYCP 8 // PHY clock present
#define SPD_h 7 // Speed Field High
#define FULLSPD 6 // Speed Field Low
#define SYSCS 5 // System Clock Select
#define USD 4 // USB Suspend detected
#define URD 3 // USB Reset detected
#define SOF 2 // Start of Frame detected
#define SETOVR 1 // USB setup command overrun
#define SETUP 0 // USB Setup Command Detected
//.................................................................................
#define UIMR *(volatile UINT16*)(USB2_BASE+0x04) /* USB Module Interrupt Mask Register */
#define RESUMEIE 14 // Set RESUME interrupt mask
#define SETECRIE 13 // Set endpoint config request mask
#define USSCIE 12 // Suspend status change mask
#define URSCIE 11 // Reset status change mask
#define SOFIE 2 // Start of Frame mask
#define SETOVRIE 1 // Setup Command overrun mask
#define SETUPIE 0 // Setup Command mask
#define UTR *(volatile UINT16*)(USB2_BASE+0x08) /* USB Module Test Register */
#define UTSR *(volatile UINT16*)(USB2_BASE+0x0A) /* USB Module TimeStamp Register */
//.................................................................................
#define UCCSR *(volatile UINT16*)(USB2_BASE+0x0C) /* USB Module Configuration Control status Register */
#define CFGVALID 15 // Configuration Valid
#define INTFVALID 14 // Interface/alternative setting valid
#define SETECR 13 // SET CONFIGURATION command request
#define DONEECRU 12 // Done CONFIGURATION update
#define UEPCSELR *(volatile UINT16*)(USB2_BASE+0x0E) /* USB Module Endpoint Configuration selection Register */
#define UEPCSELR_h *(volatile UINT8*)(USB2_BASE+0x0E) /* USB Module Endpoint Configuration selection Register */
#define UEPCSELR_l *(volatile UINT8*)(USB2_BASE+0x0F) /* USB Module Endpoint Configuration selection Register */
#define UPECFGR *(volatile muint32*)(USB2_BASE+0x10) /* USB Module UDC Configuration Register */
#define UPECFGR_h *(volatile UINT16*)(USB2_BASE+0x10) /* USB Module UDC Configuration Register */
#define UPECFGR_l *(volatile UINT16*)(USB2_BASE+0x12) /* USB Module UDC Configuration Register */
#define UNCIR_h *(volatile UINT16*)(USB2_BASE+0x10) /* USB Module number of configuration/interface Register */
#define UNCIR_l *(volatile UINT16*)(USB2_BASE+0x12) /* USB Module number of configuration/interface Register */
#define UNASR_h *(volatile UINT16*)(USB2_BASE+0x10) /* USB Module number of alternative setting Register */
#define UNASR_l *(volatile UINT16*)(USB2_BASE+0x12) /* USB Module number of alternative setting Register */
//.................................................................................
#define UEPCSR0 *(volatile UINT16*)(USB2_BASE+0x14) /* USB Module Endpoint Control status Register 0 */
#define STALL 15 // STALL enable
#define DVALID 14 // Data Valid
#define TFRC 13 // Transfer complete
#define UEPCSR1 *(volatile UINT16*)(USB2_BASE+0x16) /* USB Module Endpoint Control status Register 1 */
#define UEPCSR2 *(volatile UINT16*)(USB2_BASE+0x18) /* USB Module Endpoint Control status Register 2 */
#define UEPCSR3 *(volatile UINT16*)(USB2_BASE+0x1A) /* USB Module Endpoint Control status Register 3 */
//.................................................................................
#define UEPCSR4A *(volatile UINT16*)(USB2_BASE+0x1C) /* USB Module Endpoint Control status Register 4A */
#define STALL 15 // defined in UEPCSR0
#define SNAK 14 // Send NACK
#define TFRC 13
#define USBTCIE 12
#define CTERR 11 // Continous transfer error
//.................................................................................
#define UEPCSR4B *(volatile UINT16*)(USB2_BASE+0x1E) /* USB Module Endpoint Control status Register 4B */
#define SPKT 15 // Short Packet
#define SPKTIE 14 // short packet interrupt
#define TFRERR 13 // Transfer Error
#define UEPCSR5A *(volatile UINT16*)(USB2_BASE+0x20) /* USB Module Endpoint Control status Register 5A */
#define UEPCSR5B *(volatile UINT16*)(USB2_BASE+0x22) /* USB Module Endpoint Control status Register 5B */
#define UEPCSR6 *(volatile UINT16*)(USB2_BASE+0x24) /* USB Module Endpoint Control status Register 6 */
#define USTB *(volatile UINT8*)(USB2_BASE+0x38) /* USB Module Setup Data Buffer */
#define UEPLB0 *(volatile UINT8*)(USB2_BASE+0x80) /* USB Module Endpoint local Data Buffer 0 */
#define UEPLB1 *(volatile UINT8*)(USB2_BASE+0xc0) /* USB Module Endpoint local Data Buffer 1 */
/*CF section*/
#define CF_PMR *(volatile UINT16*)(CF_BASE+0x0E) /* Power Management Register */
#define CF_PMR_L *(volatile UINT8*)(CF_BASE+0x0F)
#define CPE 1 // 1 = power on
#define CVS 0 // 1 = 5V, 0 = 3V
/*SM Registers Address definitions */
#define SMREG_BASE REG_BANK+0x02B0 // Base Address of SMHC Module
#define SM_SMCR *(volatile UINT8*)(SMREG_BASE+0x00) /* SMHC Control Register */
#define SM_SMHS *(volatile UINT8*)(SMREG_BASE+0x01) /* SMHC Status Register */ //(Read only bit)
#define SM_SMDATA *(volatile UINT16*)(SMREG_BASE+0x02) /* SM Transmit data register */
#define SM_SMISR *(volatile UINT8*)(SMREG_BASE+0x04) /* SM Interrupt Status Register */
#define SM_SMIMR *(volatile UINT8*)(SMREG_BASE+0x05) /* SM Interrupt Mask Register */
#define SM_SMSR *(volatile UINT8*)(SMREG_BASE+0x06) /* SM Status Register */
#define SM_SMFCSR *(volatile UINT8*)(SMREG_BASE+0x07) /* SM FIFO Control/Status Register */
#define SM_SMCLKR *(volatile UINT8*)(SMREG_BASE+0x08) /* SM Clock Rate Register */
/* Break section*/
#define BRKH *(volatile UINT8*)(0xfe0c) /* Break Address High register */
#define BRKL *(volatile UINT8*)(0xfe0d) /* Break Address Low register */
#define BRKSCR *(volatile UINT8*)(0xfe0e) /* Break Status and Control register */
#define WBIT15 0x8000
#define WBIT14 0x4000
#define WBIT13 0x2000
#define WBIT12 0x1000
#define WBIT11 0x0800
#define WBIT10 0x0400
#define WBIT9 0x0200
#define WBIT8 0x0100
#define BBIT7 0x80
#define BBIT6 0x40
#define BBIT5 0x20
#define BBIT4 0x10
#define BBIT3 0x08
#define BBIT2 0x04
#define BBIT1 0x02
#define BBIT0 0x01
#define ENABLE 1
#define DISABLE 0
#define QC1SR_Q1EIF_MASK 4
#define QC1SR_Q1FIF_MASK 8
#define QC1SR_Q1VIF_MASK 16
#define QC1SR_Q1ESF_MASK 32
#define QC1SR_Q1FSF_MASK 64
#define QC1SR_Q1VSF_MASK 128
#define QC34DSHR_DTHE_34_MASK 1
#define QC34DSHR_DRHE_34_MASK 2
#define QC34DSHR_TXDA_34_MASK 16
#define QC34DSHR_TXRD_34_MASK 32
#define QC34DSHR_RXDA_34_MASK 64
#define QC34DSHR_RXDF_34_MASK 128
#define QC3CR_Q3PRST_MASK 1
#define QC3CR_Q3THRU_MASK 2
#define QC3CR_Q316EN_MASK 4
#define QC3CR_Q3SML_MASK 8
#define QC3CR_Q3EN_MASK 16
#define QC3CR_Q3FIE_MASK 32
#define QC3CR_Q3EIE_MASK 64
#define QC3CR_Q3VIE_MASK 128
//#define QC34DSHR *(volatile UINT8*)(0x00000231)
//#define UUCFGR *(volatile UINT8*)(0x00000310)
#endif _H_UF32REG_
// uf32reg.h 头文件结束
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