📄 uf32reg.h
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#define PAOVI 1 // Pulse Accumulator A Overflow Interrupt
#define PAI 0 // Pulse Accumulator A IRQ Enable
//...................................................................................
#define PAFLG *(volatile UINT8*)(ECT_BASE+0x21) /* Pulse Accumulator Control register */
#define PAOVF 1 // Pulse Accumulator A Overflow Flag
#define PAIF 0 // Pulse Accumulator A Interrupt Flag
//...................................................................................
#define PACN3 *(volatile UINT8*)(ECT_BASE+0x22) /* Pulse Accmulator A Counter #3 register */
#define PACN2 *(volatile UINT8*)(ECT_BASE+0x23) /* Pulse Accmulator A Counter #2 register */
//...................................................................................
#define PACN1 *(volatile UINT8*)(ECT_BASE+0x24) /* Pulse Accmulator A Counter #1 register */
#define PACN0 *(volatile UINT8*)(ECT_BASE+0x25) /* Pulse Accmulator A Counter #0 register */
//...................................................................................
#define MCCTL *(volatile UINT8*)(ECT_BASE+0x26) /* Modulus Counter Control register */
#define MCZI 7 // 1= Modulus Counter Underflow IRQ Enable
#define MODMC 6 // 1= Modulus Mode Enable (re-load when MCCNT=0x0000)
// 0= Down-Count MCCNT to 0x0000 and stops.
#define RDMCL 5 // 1= Read Modulus Counter Load Reg. (0= MCCNT reg)
#define ICLAT 4 // 1= Input Capture Force Latch
#define FLMC 3 // 1= Force to load Load reg. ==> Modulus reg.
#define MCEN 2 // 1= Modulus Counter Enable
#define MCPR1 1 // Modulus Counter Prescaler selection
#define MCPR0 0 // Modulus Counter Prescaler selection
//...................................................................................
#define MCFLG *(volatile UINT8*)(ECT_BASE+0x27) /* Modulus Counter Flags register */
#define MCZF 7 // Modulus Counter Underflow Flag
#define POLF3 3 // The first input capture Polarity Status (1=rising edge)
#define POLF2 2 // The first input capture Polarity Status (1=rising edge)
#define POLF1 1 // The first input capture Polarity Status (1=rising edge)
#define POLF0 0 // The first input capture Polarity Status (1=rising edge)
//...................................................................................
#define ICPAR *(volatile UINT8*)(ECT_BASE+0x28) /* I/C Pulse Accumulator register */
#define PA3EN 3 // Pulse Accumulator A #3 Enable
#define PA2EN 2 // Pulse Accumulator A #2 Enable
#define PA1EN 1 // Pulse Accumulator A #1 Enable
#define PA0EN 0 // Pulse Accumulator A #0 Enable
//...................................................................................
#define DLYCT *(volatile UINT8*)(ECT_BASE+0x29) /* Delay Counter setting register */
#define DLY1 1 // Delay Counter Setting bit 1
#define DLY0 0 // Delay Counter Setting bit 0
//...................................................................................
#define ICOVW *(volatile UINT8*)(ECT_BASE+0x2A) /* Input Control OverWrite register */
#define NOVW7 7 // 1= No OverWrite to the Holding reg. before it's read
#define NOVW6 6 // 1= No OverWrite to the Holding reg. before it's read
#define NOVW5 5 // 1= No OverWrite to the Holding reg. before it's read.
#define NOVW4 4 // 1= No OverWrite to the Holding reg. before it's read
#define NOVW3 3 // 1= No OverWrite to the Holding reg. before it's read
#define NOVW2 2 // 1= No OverWrite to the Holding reg. before it's read
#define NOVW1 1 // 1= No OverWrite to the Holding reg. before it's read
#define NOVW0 0 // 1= No OverWrite to the Holding reg. before it's read
//...................................................................................
#define ICSYS *(volatile UINT8*)(ECT_BASE+0x2B) /* Input Control System register */
#define SH37 7 // 1= Channel #3 & #7 Share the Input Action
#define SH26 6 // 1= Channel #2 & #6 Share the Input Action
#define SH15 5 // 1= Channel #1 & #5 Share the Input Action
#define SH04 4 // 1= Channel #0 & #4 Share the Input Action
#define TFMOD 3 // Timer Flag-setting Mode.
#define PACMX 2 // 1= Stop 8-bit Pulse Accumulator Counting when it's 0xFF
#define BUFEN 1 // 1= Input/Capture Buffer Enable
#define LATQ 0 // 1= Input Control or Queue Mode Enable.
//...................................................................................
#define TIMTST *(volatile UINT8*)(ECT_BASE+0x2D) /* Timer Test register */
#define TCBYP 1 // 1= Timer Divider Bypassed
//...................................................................................
#define PBCTL *(volatile UINT8*)(ECT_BASE+0x30) /* Pulse Accumulator B Control register */
#define PBEN 6 // 1= Pulse Accumulator B Enable
#define PBOVI 1 // 1= Pulse Accumulator B Overflow IRQ Enable
//...................................................................................
#define PBFLG *(volatile UINT8*)(ECT_BASE+0x31) /* Pulse Accumulator B Flags register */
#define PBOVF 1 // 1= Pulse Accumulator B Overflow IRQ Flag
/*The followings are Latched Holding Regs for Pulse Accumulator*/
//...................................................................................
#define PA3H *(volatile UINT8*)(E CT_BASE+0x32) /* Pulse Accumulator Holding register */
#define PA2H *(volatile UINT8*)(ECT_BASE+0x33) /* Pulse Accumulator Holding register */
#define PA1H *(volatile UINT8*)(ECT_BASE+0x34) /* Pulse Accumulator Holding register */
#define PA0H *(volatile UINT8*)(ECT_BASE+0x35) /* Pulse Accumulator Holding register */
//...................................................................................
#define MCCNT *(volatile UINT16*)(ECT_BASE+0x36) /* Modulus Counter count 16-bit register */
#define MCCNT_H *(volatile UINT8*)(ECT_BASE+0x36) /* Modulus Counter count high register */
#define MCCNT_L *(volatile UINT8*)(ECT_BASE+0x37) /* Modulus Counter count low register */
/*The following are the Latched Registers for InputCapture channels*/
//...................................................................................
#define TC0H *(volatile UINT16*)(ECT_BASE+0x38) /* Timer I/C Holding 16-bit register */
#define TC0H_H *(volatile UINT8*)(ECT_BASE+0x38) /* Timer I/C Holding high register */
#define TC0H_L *(volatile UINT8*)(ECT_BASE+0x39) /* Timer I/C Holding low register */
//...................................................................................
#define TC1H *(volatile UINT16*)(ECT_BASE+0x3A) /* Timer I/C Holding 16-bit register */
#define TC1H_H *(volatile UINT8*)(ECT_BASE+0x3A) /* Timer I/C Holding high register */
#define TC1H_L *(volatile UINT8*)(ECT_BASE+0x3B) /* Timer I/C Holding low register */
//...................................................................................
#define TC2H *(volatile UINT16*)(ECT_BASE+0x3C) /* Timer I/C Holding 16-bit register */
#define TC2H_H *(volatile UINT8*)(ECT_BASE+0x3C) /* Timer I/C Holding high register */
#define TC2H_L *(volatile UINT8*)(ECT_BASE+0x3D) /* Timer I/C Holding low register */
//...................................................................................
#define TC3H *(volatile UINT16*)(ECT_BASE+0x3E) /* Timer I/C Holding 16-bit register */
#define TC3H_H *(volatile UINT8*)(ECT_BASE+0x3E) /* Timer I/C Holding high register */
#define TC3H_L *(volatile UINT8*)(ECT_BASE+0x3F) /* Timer I/C Holding low register */
/*SCI section */
// SCI Baud Rate register Baud Rate = SCI Module Clk / (16* SCIBD)
#define SCIBD_offset 0x00
#define SCIBDH_offset 0x00 /* SCI0 Baud Rate high reg. */
#define SCIBDL_offset 0x01 /* SCI0 Baud Rate low reg. */
//.................................................................................
#define SCICR1_offset 0x02 /* SCI0 Control Reg. #1 */
#define LOOPS 7 // 1= Loop Operation is Enabled
#define SCISWAI 6 // 1= SCI0 is stopped in CPU WAIT mode
#define RSRC 5 // 1= Ext. wire loop back connection (0= internal loop back)
#define M 4 // 1= 1 start, 9 data, 1 stop bits, (0= 1, 8, 1)
#define WAKE 3 // 1= Address mark Wakeup(Rx Data MSB=1). 0= Idle Line Wakeup
#define ILT 2 // 1= Idle count begins after Stop bit, (0= after Start bit)
#define PE 1 // 1= Parity function Enable
#define PT 0 // 1= Parity Odd, 0= Parity Even
//.................................................................................
#define SCICR2_offset 0x03 /* SCI0 Control Reg. #2 */
#define TDREIE 7 // 1= Tx Data Empty IRQ Enable
#define TCIE 6 // 1= Tx Complete IRQ Enable
#define RDRFIE 5 // 1= Rx Data Full IRQ Enable
#define ILIE 4 // 1= Idle Line IRQ Enable
#define TXE 3 // 1= Tx Enable
#define RXE 2 // 1= Rx Enable
#define RWU 1 // 1= Normal mode (0= Wakeup function enable, Rx IRQ disabled)
#define SBK 0 // 1= Continuously Send Break characters. (0= Stop)
//.................................................................................
#define SCISR1_offset 0x04 /* SCI0 Status Reg. #1 */
#define TDRE 7 // 1= Tx Data Register Empty Flag
#define TC 6 // 1= Tx Complete Flag
#define RDRF 5 // 1= Rx Data Register Full Flag
#define IDLE 4 // 1= Idle Line Flag = Continuous 10 or 11 logic 1's on Rx line
#define OR 3 // 1= Rx Over-Run (no read before the next Rx)
#define NF 2 // 1= Noise Flag (Noise on Rx line)
#define FE 1 // 1= Framing Error Flag (when Stop bit = 0)
#define PF 0 // 1= Parity Error Flag
//.................................................................................
#define SCISR2_offset 0x05 /* SCI0 Status Reg. #2 */
#define BRK13 2 // 1= Break Char. length = 13 or 14 (0= 10 or 11)
#define TXDIR 1 // 1= TxD pin is output mode, 0= TxD pin is input mode
// (This is used only in Single-Wire Mode)
#define RAF 0 // 1= Got Start bit from RxD, 0= Got Idle character
//.................................................................................
#define SCIDRH_offset 0x06 /* SCI0 Data high Register */
#define R8 7 // Rx Data bit 8 (used M=1, 9 Data bit mode)
#define T8 6 // Tx Data bit 8 (used M=1, 9 Data bit mode)
#define SCIDRL_offset 0x07 /* SCI0 Data low Register */
//.................................................................................
/*32K EEPROM section */
//.................................................................................
#define ECLKDIV *(volatile UINT8*)(EEPROM_BASE+0x00) /* EEPROM Clock Divider register */
#define EDIVLD 7 // 1= Indicate Clk. has been written to (loaded) after Reset.
#define PRDIV8 6 // 1= Enable Prescaler by 8
#define EDIV5 5 // EEPROM Clock Divider bit-5
#define EDIV4 4 // EEPROM Clock Divider bit-4
#define EDIV3 3 // EEPROM Clock Divider bit-3
#define EDIV2 2 // EEPROM Clock Divider bit-2
#define EDIV1 1 // EEPROM Clock Divider bit-1
#define EDIV0 0 // EEPROM Clock Divider bit-0
//.................................................................................
#define ECNFG *(volatile UINT8*)(EEPROM_BASE+0x03) /* EEPROM CONFIG register */
#define CBEIE 7 // 1= Command Buffer Empty IRQ Enable.
#define CCIE 6 // 1= Command Complete IRQ Enable
//.................................................................................
#define EPROT *(volatile UINT8*)(EEPROM_BASE+0x04) /* EEPROM Protection register */
#define EPOPEN 7 // 1= EEPROM is opened for Program & Erase.
#define EPDIS 3 // 1= EEPROM Protection Disabled
#define EP2 2 // EEPROM Protection Address Size bit-2
#define EP1 1 // EEPROM Protection Address Size bit-1
#define EP0 0 // EEPROM Protection Address Size bit-0
//-------------------------------------------------------------------------------
#define ESTAT *(volatile UINT8*)(EEPROM_BASE+0x05) /* EEPROM Status register */
#define CBEIF 7 // 1= Command Buffer Empty IRQ Flag.
#define CCIF 6 // 1= Command Complete IRQ Flag
#define PVIOL 5 // 1= Protection Violation Flag
#define ACCERR 4 // 1= Access Error
#define BLANK 2 // 1= EEPROM block is fully erased
//.................................................................................
#define ECMD *(volatile UINT8*)(EEPROM_BASE+0x06) /* EEPROM Command register */
#define ERASE 6 // 1= Sector Erasing
#define PROG 5 // 1= Word Programming
#define ERVER 2 // 1= Enable to perform a verify after mass erasing
#define MASS 0 // 1= Enable the Mass erasing
//.................................................................................
/*VREG section*/
#define VREGR *(volatile UINT8*)(VREG_BASE+0x00) /* VREG Register */
/*IQUE section*/
#define IQUECR *(volatile UINT8*)(IQUE_BASE+0x00) /* IQUE Control Register */
#define CH34DBE 4 // CH3+4 Double Buffer Enable
#define CH12DBE 3 // CH1+2 Double Buffer Enable
#define IQUERST 1 // IQUE Module Reset
#define IQUEEN 0 // IQUE Module Enable
#define QC1DR *(volatile UINT16*)(IQUE_BASE+0x02) /* IQUE ch 1 data Register */
#define QC1DR_H *(volatile UINT8*)(IQUE_BASE+0x02)
#define QC1BP *(volatile UINT16*)(IQUE_BASE+0x04) /* IQUE ch 1 Begin pointer Register */
#define QC1EP *(volatile UINT16*)(IQUE_BASE+0x06) /* IQUE ch 1 End pointer Register */
//.................................................................................
#define QC1CR *(volatile UINT8*)(IQUE_BASE+0x08) /* IQUE ch 1 Control Register */
#define QnVIE 7
#define QnEIE 6
#define QnFIE 5
#define QnEN 4
#define QnSML 3
#define Qn16EN 2
#define QnTHRU 1
#define QnPRST 0 // QUE Pointer Reset
//.................................................................................
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