📄 uf32reg.h
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/*USB用到的寄存器定义和宏定义*/
#include "frDefs.h"
#ifndef _H_UF32REG_
#define _H_UF32REG_
/*中断向量定义*/
#define kVectNum_RESET 0x00 //地址:0xFFFE - 0xFFFF
#define kVectNum_Unimplemented 0x01 //地址:0xFFFC - 0xFFFD
#define kVectNum_COPFail 0x02 //地址:0xFFFA - 0xFFFB
#define kVectNum_BadInstruc 0x03 //地址:0xFFF8 - 0xFFF9
#define kVectNum_SWI 0x04 //地址:0xFFF6 - 0xFFF7
#define kVectNum_XIRQ 0x05 //地址:0xFFF4 - 0xFFF5
#define kVectNum_IRQ 0x06 //地址:0xFFF2 - 0xFFF3
#define kVectNum_RealTimeIrq 0x07 //地址:0xFFF0 - 0xFFF1
#define kVectNum_TimCh0 0x08 //地址:0xFFEE - 0xFFEF
#define kVectNum_TimCh1 0x09 //地址:0xFFEC - 0xFFED
#define kVectNum_TimCh2 0x0A //地址:0xFFEA - 0xFFEB
#define kVectNum_TimCh3 0x0B //地址:0xFFE8 - 0xFFE9
#define kVectNum_TimCh4 0x0C //地址:0xFFE6 - 0xFFE7
#define kVectNum_TimCh5 0x0D //地址:0xFFE4 - 0xFFE5
#define kVectNum_TimCh6 0x0E //地址:0xFFE2 - 0xFFE3
#define kVectNum_TimCh7 0x0F //地址:0xFFE0 - 0xFFE1
#define kVectNum_TimerOvr 0x10 //地址:0xFFDE - 0xFFDF
#define kVectNum_PulseAccAOvr 0x11 //地址:0xFFDC - 0xFFDD
#define kVectNum_PulseAccInput 0x12 //地址:0xFFDA - 0xFFDB
#define kVectNum_SCI_0 0x13 //地址:0xFFD8 - 0xFFD9
#define kVectNum_USBStatusChg 0x15 //地址:0xFFD4 - 0xFFD5
#define kVectNum_USBSetup 0x16 //地址:0xFFD2 - 0xFFD3
#define kVectNum_USBEndCfg 0x17 //地址:0xFFD0 - 0xFFD1
#define kVectNum_USBEnd0IN 0x18 //地址:0xFFCE - 0xFFCF
#define kVectNum_USBEnd0OUT 0x19 //地址:0xFFCC - 0xFFCD
#define kVectNum_USBEnd2 0x1A //地址:0xFFCA - 0xFFCB
#define kVectNum_USBEnd3 0x1B //地址:0xFFC8 - 0xFFC9
#define kVectNum_PLL 0x1C //地址:0xFFC6 - 0xFFC7
#define kVectNum_USBEnd4 0x1D //地址:0xFFC4 - 0xFFC5
#define kVectNum_USBEnd5 0x1E //地址:0xFFC2 - 0xFFC3
#define kVectNum_USBEnd6 0ex1F //地址:0xFFC0 - 0xFFC1
#define kVectNum_USBFrame 0x20 //地址:0xFFBE - 0xFFBF
#define kVectNum_FLASH 0x23 //地址:0xFFB8 - 0xFFB9
#define kVectNum_IQUE1_Full 0x24 //地址:0xFFB6 - 0xFFB7
#define kVectNum_IQUE1_Empty 0x25 //地址:0xFFB4 - 0xFFB5
#define kVectNum_IQUE1_Valid 0x26 //地址:0xFFB2 - 0xFFB3
#define kVectNum_IQUE2_Full 0x27 //地址:0xFFB0 - 0xFFB1
#define kVectNum_IQUE2_Empty 0x28 //地址:0xFFAE - 0xFFAF
#define kVectNum_IQUE2_Valid 0x29 //地址:0xFFAC - 0xFFAD
#define kVectNum_IQUE3_Full 0x2A //地址:0xFFAA - 0xFFAB
#define kVectNum_IQUE3_Empty 0x2B //地址:0xFFA8 - 0xFFA9
#define kVectNum_IQUE3_Valid 0x2C //地址:0xFFA6 - 0xFFA7
#define kVectNum_IQUE4_Full 0x2D //地址:0xFFA4 - 0xFFA5
#define kVectNum_IQUE4_Empty 0x2E //地址:0xFFA2 - 0xFFA3
#define kVectNum_IQUE4_Valid 0x2F //地址:0xFFA0 - 0xFFA1
#define kVectNum_IQUE12_Full 0x30 //地址:0xFF9E - 0xFF9F
#define kVectNum_IQUE12_Empty 0x31 //地址:0xFF9C - 0xFF9D
#define kVectNum_IQUE12_Compl 0x32 //地址:0xFF9A - 0xFF9B
#define kVectNum_IQUE34_Full 0x33 //地址:0xFF98 - 0xFF99
#define kVectNum_IQUE34_Empty 0x34 //地址:0xFF96 - 0xFF97
#define kVectNum_IQUE34_Compl 0x35 //地址:0xFF94 - 0xFF95
#define kVectNum_ATA5 0x38 //地址:0xFF8E - 0xFF8F
#define kVectNum_CF_Soft 0x39 //地址:0xFF8C - 0xFF8D
#define kVectNum_CF_Hard 0x3A //地址:0xFF8A - 0xFF8B
#define kVectNum_MS 0x3B //地址:0xFF88 - 0xFF89
#define kVectNum_SD 0x3C //地址:0xFF86 - 0xFF87
#define kVectNum_SM_Error 0x3D //地址:0xFF84 - 0xFF85
#define kVectNum_SM_Status 0x3E //地址:0xFF82 - 0xFF83
/*基地址定义*/
//寄存器基地址
#define REG_BANK 0x0000 //0x0000-0x03FF:1K 字节
//QRAM基地址
#define QRAM_BANK 0x2000 //0x2000-0x25FF:1.5K 字节
//SMRAM基地址
#define RAM_BANK 0x1200 //0x1200-0x1FFF:1.5K 字节
//FLASH/ROM基地址
#define ROM_BANK 0x8000 //0x8000-0xFF00:32K 字节
//每个外设基地址.
#define BUSPORT_BASE REG_BANK+0x0000 // 总线和口模块基地址
#define RSRCMAP_BASE REG_BANK+0x0000 // Resource Mapping模块基地址
#define EIRQ_BASE REG_BANK+0x0000 // IRQ模块基地址
#define VREG_BASE REG_BANK+0x0019 // 外部IRQ模块基地址
#define CRG_BASE REG_BANK+0x0034 // 时钟和复位模块基地址
#define ECT_BASE REG_BANK+0x0040 // 扩展时钟捕捉模块基地址
#define SCI0_BASE REG_BANK+0x00C8 // SCI模块基地址
#define PIM_BASE REG_BANK+0x0240 // 口集成模块基地址
#define EEPROM_BASE REG_BANK+0x0100 // 3.5K EEPROM 寄存器模块基地址
#define RAM_BASE REG_BANK+0x011C // SMRAM寄存器模块基地址
#define IQUE_BASE REG_BANK+0x0200 // IQUE寄存器模块基地址
#define ATA_BASE REG_BANK+0x01C0 // ATA5寄存器模块基地址
#define CF_BASE REG_BANK+0x0280 // CFHC寄存器模块基地址
#define MSHC_BASE REG_BANK+0x02A0 // MSHC寄存器模块基地址
#define SMHC_BASE REG_BANK+0x02B0 // SMHC寄存器模块基地址
#define SDHC_BASE REG_BANK+0x02C0 // SDHC寄存器模块基地址
#define USB2_BASE REG_BANK+0x0300 // USB 2.0寄存器模块基地址
#define SMRAMCFG (*((volatile unsigned char*)(RAM_BASE+0)))
/*RAM 分配*/
#define kIQUERAMBegin 0x2000
/*资源分配定义*/
#define kMaxNumSciChnl 1 // SCI最大通道数
/*寄存器地址定义*/
#define PORTA *(volatile UINT8*)(BUSPORT_BASE+0x00) // A 口
#define PORTB *(volatile UINT8*)(BUSPORT_BASE+0x01) // B 口
#define DDRA *(volatile UINT8*)(BUSPORT_BASE+0x02) // A 口数据方向
#define DDRB *(volatile UINT8*)(BUSPORT_BASE+0x03) // B 口数据方向
#define PORTE *(volatile UINT8*)(BUSPORT_BASE+0x08) // E 口
#define DDRE *(volatile UINT8*)(BUSPORT_BASE+0x09) // E 口数据方向
#define PORTT *(volatile UINT8*)(PIM_BASE+0x00) // T 口
#define DDRT *(volatile UINT8*)(PIM_BASE+0x02) // T 口数据方向
#define RDRJ *(volatile UINT8*)(PIM_BASE+0x13) // J 口
#define RDRM *(volatile UINT8*)(PIM_BASE+0x0B) // M 口
#define RDRQ *(volatile UINT8*)(PIM_BASE+0x23) // Q 口
#define MODRR *(volatile UINT8*)(PIM_BASE+0x17) // MODRR
#define PORTS *(volatile UINT8*)(PIM_BASE+0x30) // S 口
#define ATAINTRQ 7
#define DDRS *(volatile UINT8*)(PIM_BASE+0x32) // S 口数据方向
//.............................................................................................
#define PEAR *(volatile UINT8*)(BUSPORT_BASE+0x0A) // E 口寄存器
#define NOACCE 7 // CPU No Access Output Enable
#define PIPOE 5 // Pipe status signal Output Enable
#define NECLK 4 // No External Clock
#define LSTRE 3 // Low Strobe Enable
#define RDWE 2 // Read/Write Signal Enable
//.............................................................................................
#define MODE *(volatile UINT8*)(BUSPORT_BASE+0x0B) // CPU 模块选择寄存器
#define MODC 7 // CPU Mode selection #2
#define MODB 6 // CPU Mode selection #1
#define MODA 5 // CPU Mode selection #0
#define IVIS 3 // Internal Operation Visibility on bus
#define EMK 1 // Emulate Port K
#define EME 0 // Emulate Port E
//.............................................................................................
#define PUCR *(volatile UINT8*)(BUSPORT_BASE+0x0C) // 口上拉允许寄存器
#define PUPKE 7 // Pull-Up of Port K Enable
#define PUPEE 4 // Pull-Up of Port E Enable
#define PUPBE 1 // Pull-Up of Port B Enable
#define PUPAE 0 // Pull-Up of Port A Enable
//.............................................................................................
#define RDRIV *(volatile UINT8*)(BUSPORT_BASE+0x0D) //降低I/O口驱动寄存器
#define RDPK 7 // Reduced Driving of Port K Enable
#define RDPE 4 // Reduced Driving of Port E Enable
#define RDPB 1 // Reduced Driving of Port B Enable
#define RDPA 0 // Reduced Driving of Port A Enable
//.............................................................................................
#define EBICTL *(volatile UINT8*)(BUSPORT_BASE+0x0E) //外部总线接口控制寄存器
#define ESTR 0 // E Clock Stretched
/*Resource Mapping*/
//.............................................................................................
#define INITRM *(volatile UINT8*)(RSRCMAP_BASE+0x10) /* Initialization of RAM Position */
#define RAM15 7 // RAM mapping address bit#15
#define RAM14 6 // RAM mapping address bit#14
#define RAM13 5 // RAM mapping address bit#13
#define RAMHAL 0 // RAM Aligned to top address (0xFFFF)
//.............................................................................................
#define INITRG *(volatile UINT8*)(RSRCMAP_BASE+0x11) /* Initialization of REGs Position */
#define REG14 6 // REGs mapping address bit#14
#define REG13 5 // REGs mapping address bit#13
#define REG12 4 // REGs mapping address bit#12
#define REG11 3 // REGs mapping address bit#11
//.............................................................................................
#define INITEE *(volatile UINT8*)(RSRCMAP_BASE+0x12) /* Initialization of EEPROM Position */
#define EE15 7 // EEPROM mapping address bit#15
#define EE14 6 // EEPROM mapping address bit#14
#define EE13 5 // EEPROM mapping address bit#13
#define EE12 4 // EEPROM mapping address bit#12
#define EEON 0 // EEPROM Enable
//.............................................................................................
#define MISC *(volatile UINT8*)(RSRCMAP_BASE+0x13) /* MISC Register */
#define EXSTR1 3 //
#define EXSTR0 2 //
#define ROMHM 1 //
#define ROMON 0 //
//.............................................................................................
#define MEMSIZ0 *(volatile UINT8*)(RSRCMAP_BASE+0x1C) /* Memory Bank Size selection */
#define reg_sw0 7 // Register Bank Selection
#define eep_sw1 5 // EEPROM Bank Selection
#define eep_sw0 4 // EEPROM Bank Selection
#define ram_sw2 2 // RAM Bank Selection
#define ram_sw1 1 // RAM Bank Selection
#define ram_sw0 0 // RAM Bank Selection
//.............................................................................................
#define MEMSIZ1 *(volatile UINT8*)(RSRCMAP_BASE+0x1D) /* Memory Bank Size selection */
#define rom_sw1 7 // ROM Bank Selection
#define rom_sw0 6 // ROM Bank Selection
#define pag_sw1 1 // RAM Bank Selection
#define pag_sw0 0 // RAM Bank Selection
//.............................................................................................
#define PPAGE *(volatile UINT8*)(RSRCMAP_BASE+0x30) /* Page Index of ROM Banks */
/*EXT. INTERRUPT section*/
#define INTCR *(volatile UINT8*)(EIRQ_BASE+0x1E) /* IRQ control register */
#define IRQE 7 // IRQ Signal Edge selection
#define IRQEN 6 // ext. IRQ Enable
//.............................................................................................
/*This is used to promote a selected interrupt vector (low byte)*/
// become the highest priority interrupt.
#define HPRIO *(volatile UINT8*)(EIRQ_BASE+0x1Fs) /* Highest Priority Selection */
//.............................................................................................
/*Clock & Reset Generator section*/
#define SYNR *(volatile UINT8*)(CRG_BASE+0x00) /* Clock Synthesizer Register */
#define REFDV *(volatile UINT8*)(CRG_BASE+0x01) /* Reference Division Register */
#define CTFLG *(volatile UINT8*)(CRG_BASE+0x02) /* CRG Test Flags Register */
//.............................................................................................
#define CRGFLG *(volatile UINT8*)(CRG_BASE+0x03) /* CRG Test Flags Register */
#define RTIF 7 // Real-Time IRQ Flag
#define PORF 6 // Power On Reset Flag
#define LOCKIF 4 // PLL Lock IRQ Flag
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