tn2313def.inc

AVR Assembler 2 compiler

.equ	UCPOL	= 0	; Clock Polarity
.equ	UCSZ0	= 1	; Character Size Bit 0
.equ	UCSZ1	= 2	; Character Size Bit 1
.equ	USBS	= 3	; Stop Bit Select
.equ	UPM0	= 4	; Parity Mode Bit 0
.equ	UPM1	= 5	; Parity Mode Bit 1
.equ	UMSEL	= 6	; USART Mode Select

.equ	UBRR	= UBRRL	; For compatibility

; ***** ANALOG_COMPARATOR ************
; ACSR - Analog Comparator Control And Status Register
.equ	ACIS0	= 0	; Analog Comparator Interrupt Mode Select bit 0
.equ	ACIS1	= 1	; Analog Comparator Interrupt Mode Select bit 1
.equ	ACIC	= 2	; 
.equ	ACIE	= 3	; Analog Comparator Interrupt Enable
.equ	ACI	= 4	; Analog Comparator Interrupt Flag
.equ	ACO	= 5	; Analog Compare Output
.equ	ACBG	= 6	; Analog Comparator Bandgap Select
.equ	ACD	= 7	; Analog Comparator Disable

; DIDR - Digital Input Disable Register 1
.equ	AIN0D	= 0	; AIN0 Digital Input Disable
.equ	AIN1D	= 1	; AIN1 Digital Input Disable


; ***** PORTD ************************
; PORTD - Data Register, Port D
.equ	PORTD0	= 0	; 
.equ	PD0	= 0	; For compatibility
.equ	PORTD1	= 1	; 
.equ	PD1	= 1	; For compatibility
.equ	PORTD2	= 2	; 
.equ	PD2	= 2	; For compatibility
.equ	PORTD3	= 3	; 
.equ	PD3	= 3	; For compatibility
.equ	PORTD4	= 4	; 
.equ	PD4	= 4	; For compatibility
.equ	PORTD5	= 5	; 
.equ	PD5	= 5	; For compatibility
.equ	PORTD6	= 6	; 
.equ	PD6	= 6	; For compatibility

; DDRD - Data Direction Register, Port D
.equ	DDD0	= 0	; 
.equ	DDD1	= 1	; 
.equ	DDD2	= 2	; 
.equ	DDD3	= 3	; 
.equ	DDD4	= 4	; 
.equ	DDD5	= 5	; 
.equ	DDD6	= 6	; 

; PIND - Input Pins, Port D
.equ	PIND0	= 0	; 
.equ	PIND1	= 1	; 
.equ	PIND2	= 2	; 
.equ	PIND3	= 3	; 
.equ	PIND4	= 4	; 
.equ	PIND5	= 5	; 
.equ	PIND6	= 6	; 


; ***** EEPROM ***********************
; EEAR - EEPROM Read/Write Access
.equ	EEARL	= EEAR	; For compatibility
.equ	EEAR0	= 0	; EEPROM Read/Write Access bit 0
.equ	EEAR1	= 1	; EEPROM Read/Write Access bit 1
.equ	EEAR2	= 2	; EEPROM Read/Write Access bit 2
.equ	EEAR3	= 3	; EEPROM Read/Write Access bit 3
.equ	EEAR4	= 4	; EEPROM Read/Write Access bit 4
.equ	EEAR5	= 5	; EEPROM Read/Write Access bit 5
.equ	EEAR6	= 6	; EEPROM Read/Write Access bit 6

; EEDR - EEPROM Data Register
.equ	EEDR0	= 0	; EEPROM Data Register bit 0
.equ	EEDR1	= 1	; EEPROM Data Register bit 1
.equ	EEDR2	= 2	; EEPROM Data Register bit 2
.equ	EEDR3	= 3	; EEPROM Data Register bit 3
.equ	EEDR4	= 4	; EEPROM Data Register bit 4
.equ	EEDR5	= 5	; EEPROM Data Register bit 5
.equ	EEDR6	= 6	; EEPROM Data Register bit 6
.equ	EEDR7	= 7	; EEPROM Data Register bit 7

; EECR - EEPROM Control Register
.equ	EERE	= 0	; EEPROM Read Enable
.equ	EEPE	= 1	; EEPROM Write Enable
.equ	EEWE	= EEPE	; For compatibility
.equ	EEMPE	= 2	; EEPROM Master Write Enable
.equ	EEMWE	= EEMPE	; For compatibility
.equ	EERIE	= 3	; EEProm Ready Interrupt Enable
.equ	EEPM0	= 4	; 
.equ	EEPM1	= 5	; 


; ***** PORTA ************************
; PORTA - Port A Data Register
.equ	PORTA0	= 0	; Port A Data Register bit 0
.equ	PA0	= 0	; For compatibility
.equ	PORTA1	= 1	; Port A Data Register bit 1
.equ	PA1	= 1	; For compatibility
.equ	PORTA2	= 2	; Port A Data Register bit 2
.equ	PA2	= 2	; For compatibility

; DDRA - Port A Data Direction Register
.equ	DDA0	= 0	; Data Direction Register, Port A, bit 0
.equ	DDA1	= 1	; Data Direction Register, Port A, bit 1
.equ	DDA2	= 2	; Data Direction Register, Port A, bit 2

; PINA - Port A Input Pins
.equ	PINA0	= 0	; Input Pins, Port A bit 0
.equ	PINA1	= 1	; Input Pins, Port A bit 1
.equ	PINA2	= 2	; Input Pins, Port A bit 2


; ***** CPU **************************
; SREG - Status Register
.equ	SREG_C	= 0	; Carry Flag
.equ	SREG_Z	= 1	; Zero Flag
.equ	SREG_N	= 2	; Negative Flag
.equ	SREG_V	= 3	; Two's Complement Overflow Flag
.equ	SREG_S	= 4	; Sign Bit
.equ	SREG_H	= 5	; Half Carry Flag
.equ	SREG_T	= 6	; Bit Copy Storage
.equ	SREG_I	= 7	; Global Interrupt Enable

; SPMCSR - Store Program Memory Control and Status register
.equ	SPMEN	= 0	; Store Program Memory Enable
.equ	PGERS	= 1	; Page Erase
.equ	PGWRT	= 2	; Page Write
.equ	RFLB	= 3	; Read Fuse and Lock Bits
.equ	CTPB	= 4	; Clear Temporary Page Buffer

; MCUCR - MCU Control Register
.equ	ISC00	= 0	; Interrupt Sense Control 0 bit 0
.equ	ISC01	= 1	; Interrupt Sense Control 0 bit 1
.equ	ISC10	= 2	; Interrupt Sense Control 1 bit 0
.equ	ISC11	= 3	; Interrupt Sense Control 1 bit 1
.equ	SM0	= 4	; Sleep Mode Select Bit 0
.equ	SM	= SM0	; For compatibility
.equ	SE	= 5	; Sleep Enable
.equ	SM1	= 6	; Sleep Mode Select Bit 1
.equ	PUD	= 7	; Pull-up Disable

; CLKPR - Clock Prescale Register
.equ	CLKPS0	= 0	; Clock Prescaler Select Bit 0
.equ	CLKPS1	= 1	; Clock Prescaler Select Bit 1
.equ	CLKPS2	= 2	; Clock Prescaler Select Bit 2
.equ	CLKPS3	= 3	; Clock Prescaler Select Bit 3
.equ	CLKPCE	= 7	; Clock Prescaler Change Enable

; MCUSR - MCU Status register
.equ	PORF	= 0	; Power-On Reset Flag
.equ	EXTRF	= 1	; External Reset Flag
.equ	BORF	= 2	; Brown-out Reset Flag
.equ	WDRF	= 3	; Watchdog Reset Flag

; OSCCAL - Oscillator Calibration Register
.equ	CAL0	= 0	; Oscillatro Calibration Value Bit 0
.equ	CAL1	= 1	; Oscillatro Calibration Value Bit 1
.equ	CAL2	= 2	; Oscillatro Calibration Value Bit 2
.equ	CAL3	= 3	; Oscillatro Calibration Value Bit 3
.equ	CAL4	= 4	; Oscillatro Calibration Value Bit 4
.equ	CAL5	= 5	; Oscillatro Calibration Value Bit 5
.equ	CAL6	= 6	; Oscillatro Calibration Value Bit 6

; GTCCR - General Timer Counter Control Register
.equ	SFIOR	= GTCCR	; For compatibility
.equ	PSR10	= 0	; 

; PCMSK - Pin-Change Mask register
.equ	PCINT0	= 0	; Pin-Change Interrupt 0
.equ	PCINT1	= 1	; Pin-Change Interrupt 1
.equ	PCINT2	= 2	; Pin-Change Interrupt 2
.equ	PCINT3	= 3	; Pin-Change Interrupt 3
.equ	PCINT4	= 4	; Pin-Change Interrupt 4
.equ	PCINT5	= 5	; Pin-Change Interrupt 5
.equ	PCINT6	= 6	; Pin-Change Interrupt 6
.equ	PCINT7	= 7	; Pin-Change Interrupt 7

; GPIOR2 - General Purpose I/O Register 2
.equ	GPIOR20	= 0	; General Purpose I/O Register 2 bit 0
.equ	GPIOR21	= 1	; General Purpose I/O Register 2 bit 1
.equ	GPIOR22	= 2	; General Purpose I/O Register 2 bit 2
.equ	GPIOR23	= 3	; General Purpose I/O Register 2 bit 3
.equ	GPIOR24	= 4	; General Purpose I/O Register 2 bit 4
.equ	GPIOR25	= 5	; General Purpose I/O Register 2 bit 5
.equ	GPIOR26	= 6	; General Purpose I/O Register 2 bit 6
.equ	GPIOR27	= 7	; General Purpose I/O Register 2 bit 7

; GPIOR1 - General Purpose I/O Register 1
.equ	GPIOR10	= 0	; General Purpose I/O Register 1 bit 0
.equ	GPIOR11	= 1	; General Purpose I/O Register 1 bit 1
.equ	GPIOR12	= 2	; General Purpose I/O Register 1 bit 2
.equ	GPIOR13	= 3	; General Purpose I/O Register 1 bit 3
.equ	GPIOR14	= 4	; General Purpose I/O Register 1 bit 4
.equ	GPIOR15	= 5	; General Purpose I/O Register 1 bit 5
.equ	GPIOR16	= 6	; General Purpose I/O Register 1 bit 6
.equ	GPIOR17	= 7	; General Purpose I/O Register 1 bit 7

; GPIOR0 - General Purpose I/O Register 0
.equ	GPIOR00	= 0	; General Purpose I/O Register 0 bit 0
.equ	GPIOR01	= 1	; General Purpose I/O Register 0 bit 1
.equ	GPIOR02	= 2	; General Purpose I/O Register 0 bit 2
.equ	GPIOR03	= 3	; General Purpose I/O Register 0 bit 3
.equ	GPIOR04	= 4	; General Purpose I/O Register 0 bit 4
.equ	GPIOR05	= 5	; General Purpose I/O Register 0 bit 5
.equ	GPIOR06	= 6	; General Purpose I/O Register 0 bit 6
.equ	GPIOR07	= 7	; General Purpose I/O Register 0 bit 7


; ***** USI **************************
; USIDR - USI Data Register
.equ	USIDR0	= 0	; USI Data Register bit 0
.equ	USIDR1	= 1	; USI Data Register bit 1
.equ	USIDR2	= 2	; USI Data Register bit 2
.equ	USIDR3	= 3	; USI Data Register bit 3
.equ	USIDR4	= 4	; USI Data Register bit 4
.equ	USIDR5	= 5	; USI Data Register bit 5
.equ	USIDR6	= 6	; USI Data Register bit 6
.equ	USIDR7	= 7	; USI Data Register bit 7

; USISR - USI Status Register
.equ	USICNT0	= 0	; USI Counter Value Bit 0
.equ	USICNT1	= 1	; USI Counter Value Bit 1
.equ	USICNT2	= 2	; USI Counter Value Bit 2
.equ	USICNT3	= 3	; USI Counter Value Bit 3
.equ	USIDC	= 4	; Data Output Collision
.equ	USIPF	= 5	; Stop Condition Flag
.equ	USIOIF	= 6	; Counter Overflow Interrupt Flag
.equ	USISIF	= 7	; Start Condition Interrupt Flag

; USICR - USI Control Register
.equ	USITC	= 0	; Toggle Clock Port Pin
.equ	USICLK	= 1	; Clock Strobe
.equ	USICS0	= 2	; USI Clock Source Select Bit 0
.equ	USICS1	= 3	; USI Clock Source Select Bit 1
.equ	USIWM0	= 4	; USI Wire Mode Bit 0
.equ	USIWM1	= 5	; USI Wire Mode Bit 1
.equ	USIOIE	= 6	; Counter Overflow Interrupt Enable
.equ	USISIE	= 7	; Start Condition Interrupt Enable



; ***** LOCKSBITS ********************************************************
.equ	LB1	= 0	; Lockbit
.equ	LB2	= 1	; Lockbit


; ***** FUSES ************************************************************
; LOW fuse bits
.equ	CKSEL0	= 0	; Select Clock Source
.equ	CKSEL1	= 1	; Select Clock Source
.equ	CKSEL2	= 2	; Select Clock Source
.equ	CKSEL3	= 3	; Select Clock Source
.equ	SUT0	= 4	; Select start-up time
.equ	SUT1	= 5	; Select start-up time
.equ	CKOUT	= 6	; Clock output
.equ	CKDIV8	= 7	; Divide clock by 8

; HIGH fuse bits
.equ	BODLEVEL0	= 0	; Brown-out Detector trigger level
.equ	BODLEVEL1	= 1	; Brown-out Detector trigger level
.equ	BODLEVEL2	= 2	; Brown-out Detector trigger level
.equ	EESAVE	= 3	; EEPROM memory is preserved through chip erase
.equ	WDTON	= 4	; Watchdog Timer Always On
.equ	SPIEN	= 5	; Enable Serial programming and Data Downloading
.equ	DWEN	= 6	; debugWIRE Enable
.equ	RSTDISBL	= 7	; External reset disable

; EXTENDED fuse bits
.equ	SELFPRGEN	= 0	; Self Programming Enable



; ***** CPU REGISTER DEFINITIONS *****************************************
.def	XH	= r27
.def	XL	= r26
.def	YH	= r29
.def	YL	= r28
.def	ZH	= r31
.def	ZL	= r30



; ***** DATA MEMORY DECLARATIONS *****************************************
.equ	FLASHEND	= 0x03ff	; Note: Word address
.equ	IOEND	= 0x003f
.equ	SRAM_START	= 0x0060
.equ	SRAM_SIZE	= 128
.equ	RAMEND	= 0x00df
.equ	XRAMEND	= 0x0000
.equ	E2END	= 0x007f
.equ	EEPROMEND	= 0x007f
.equ	EEADRBITS	= 7
#pragma AVRPART MEMORY PROG_FLASH 2048
#pragma AVRPART MEMORY EEPROM 128
#pragma AVRPART MEMORY INT_SRAM SIZE 128
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60



; ***** BOOTLOADER DECLARATIONS ******************************************
.equ	NRWW_START_ADDR	= 0x0
.equ	NRWW_STOP_ADDR	= 0x3ff
.equ	RWW_START_ADDR	= 0x0
.equ	RWW_STOP_ADDR	= 0x0
.equ	PAGESIZE	= 16



; ***** INTERRUPT VECTORS ************************************************
.equ	INT0addr	= 0x0001	; External Interrupt Request 0
.equ	INT1addr	= 0x0002	; External Interrupt Request 1
.equ	ICP1addr	= 0x0003	; Timer/Counter1 Capture Event
.equ	OC1Aaddr	= 0x0004	; Timer/Counter1 Compare Match A
.equ	OC1addr	= 0x0004	; For compatibility
.equ	OVF1addr	= 0x0005	; Timer/Counter1 Overflow
.equ	OVF0addr	= 0x0006	; Timer/Counter0 Overflow
.equ	URXCaddr	= 0x0007	; USART, Rx Complete
.equ	URXC0addr	= 0x0007	; For compatibility
.equ	UDREaddr	= 0x0008	; USART Data Register Empty
.equ	UDRE0addr	= 0x0008	; For compatibility
.equ	UTXCaddr	= 0x0009	; USART, Tx Complete
.equ	UTXC0addr	= 0x0009	; For compatibility
.equ	ACIaddr	= 0x000a	; Analog Comparator
.equ	PCIaddr	= 0x000b	; 
.equ	OC1Baddr	= 0x000c	; 
.equ	OC0Aaddr	= 0x000d	; 
.equ	OC0Baddr	= 0x000e	; 
.equ	USI_STARTaddr	= 0x000f	; USI Start Condition
.equ	USI_OVFaddr	= 0x0010	; USI Overflow
.equ	ERDYaddr	= 0x0011	; 
.equ	WDTaddr	= 0x0012	; Watchdog Timer Overflow

.equ	INT_VECTORS_SIZE	= 19	; size in words

#endif  /* _TN2313DEF_INC_ */

; ***** END OF FILE ******************************************************