📄 usb1286def.inc
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.equ UBRR10 = 2 ; USART Baud Rate Register bit 10
.equ UBRR11 = 3 ; USART Baud Rate Register bit 11
; UBRR1L - USART Baud Rate Register Low Byte
.equ UBRR0 = 0 ; USART Baud Rate Register bit 0
.equ UBRR1 = 1 ; USART Baud Rate Register bit 1
.equ UBRR2 = 2 ; USART Baud Rate Register bit 2
.equ UBRR3 = 3 ; USART Baud Rate Register bit 3
.equ UBRR4 = 4 ; USART Baud Rate Register bit 4
.equ UBRR5 = 5 ; USART Baud Rate Register bit 5
.equ UBRR6 = 6 ; USART Baud Rate Register bit 6
.equ UBRR7 = 7 ; USART Baud Rate Register bit 7
; ***** USB_DEVICE *******************
; UDCON -
.equ DETACH = 0 ;
.equ RMWKUP = 1 ;
.equ LSM = 2 ;
; UDINT -
.equ SUSPI = 0 ;
.equ MSOFI = 1 ;
.equ SOFI = 2 ;
.equ EORSTI = 3 ;
.equ WAKEUPI = 4 ;
.equ EORSMI = 5 ;
.equ UPRSMI = 6 ;
; UDIEN -
.equ SUSPE = 0 ;
.equ MSOFE = 1 ;
.equ SOFE = 2 ;
.equ EORSTE = 3 ;
.equ WAKEUPE = 4 ;
.equ EORSME = 5 ;
.equ UPRSME = 6 ;
; UDADDR -
.equ UDADDR0 = 0 ;
.equ UDADDR1 = 1 ;
.equ UDADDR2 = 2 ;
.equ UDADDR3 = 3 ;
.equ UDADDR4 = 4 ;
.equ UDADDR5 = 5 ;
.equ UDADDR6 = 6 ;
.equ ADDEN = 7 ;
; UDFNUML -
.equ UDFNUML_0 = 0 ;
.equ UDFNUML_1 = 1 ;
.equ UDFNUML_2 = 2 ;
.equ UDFNUML_3 = 3 ;
.equ UDFNUML_4 = 4 ;
.equ UDFNUML_5 = 5 ;
.equ UDFNUML_6 = 6 ;
.equ UDFNUML_7 = 7 ;
; UDFNUMH -
.equ UDFNUMH_0 = 0 ;
.equ UDFNUMH_1 = 1 ;
.equ UDFNUMH_2 = 2 ;
; UDMFN -
.equ FNCERR = 4 ;
; UEINTX -
.equ TXINI = 0 ;
.equ STALLEDI = 1 ;
.equ RXOUTI = 2 ;
.equ RXSTPI = 3 ;
.equ NAKOUTI = 4 ;
.equ RWAL = 5 ;
.equ NAKINI = 6 ;
.equ FIFOCON = 7 ;
; UENUM -
.equ UENUM_0 = 0 ;
.equ UENUM_1 = 1 ;
.equ UENUM_2 = 2 ;
; UERST -
.equ EPRST0 = 0 ;
.equ EPRST1 = 1 ;
.equ EPRST2 = 2 ;
.equ EPRST3 = 3 ;
.equ EPRST4 = 4 ;
.equ EPRST5 = 5 ;
.equ EPRST6 = 6 ;
; UECONX -
.equ EPEN = 0 ;
.equ RSTDT = 3 ;
.equ STALLRQC = 4 ;
.equ STALLRQ = 5 ;
; UECFG0X -
.equ EPDIR = 0 ;
.equ EPTYPE0 = 6 ;
.equ EPTYPE1 = 7 ;
; UECFG1X -
.equ ALLOC = 1 ;
.equ EPBK0 = 2 ;
.equ EPBK1 = 3 ;
.equ EPSIZE0 = 4 ;
.equ EPSIZE1 = 5 ;
.equ EPSIZE2 = 6 ;
; UESTA0X -
.equ NBUSYBK0 = 0 ;
.equ NBUSYBK1 = 1 ;
.equ DTSEQ0 = 2 ;
.equ DTSEQ1 = 3 ;
.equ ZLPSEEN = 4 ;
.equ UNDERFI = 5 ;
.equ OVERFI = 6 ;
.equ CFGOK = 7 ;
; UESTA1X -
.equ CURRBK0 = 0 ;
.equ CURRBK1 = 1 ;
.equ CTRLDIR = 2 ;
; UEIENX -
.equ TXINE = 0 ;
.equ STALLEDE = 1 ;
.equ RXOUTE = 2 ;
.equ RXSTPE = 3 ;
.equ NAKOUTE = 4 ;
.equ NAKINE = 6 ;
.equ FLERRE = 7 ;
; UEDATX -
.equ UEDATX_0 = 0 ;
.equ UEDATX_1 = 1 ;
.equ UEDATX_2 = 2 ;
.equ UEDATX_3 = 3 ;
.equ UEDATX_4 = 4 ;
.equ UEDATX_5 = 5 ;
.equ UEDATX_6 = 6 ;
.equ UEDATX_7 = 7 ;
; UEBCLX -
.equ UEBCLX_0 = 0 ;
.equ UEBCLX_1 = 1 ;
.equ UEBCLX_2 = 2 ;
.equ UEBCLX_3 = 3 ;
.equ UEBCLX_4 = 4 ;
.equ UEBCLX_5 = 5 ;
.equ UEBCLX_6 = 6 ;
.equ UEBCLX_7 = 7 ;
; UEBCHX -
.equ UEBCHX_0 = 0 ;
.equ UEBCHX_1 = 1 ;
.equ UEBCHX_2 = 2 ;
; UEINT -
.equ EPINT0 = 0 ;
.equ EPINT1 = 1 ;
.equ EPINT2 = 2 ;
.equ EPINT3 = 3 ;
.equ EPINT4 = 4 ;
.equ EPINT5 = 5 ;
.equ EPINT6 = 6 ;
; ***** BOOT_LOAD ********************
; SPMCSR - Store Program Memory Control Register
.equ SPMEN = 0 ; Store Program Memory Enable
.equ PGERS = 1 ; Page Erase
.equ PGWRT = 2 ; Page Write
.equ BLBSET = 3 ; Boot Lock Bit Set
.equ RWWSRE = 4 ; Read While Write section read enable
.equ SIGRD = 5 ; Signature Row Read
.equ RWWSB = 6 ; Read While Write Section Busy
.equ SPMIE = 7 ; SPM Interrupt Enable
; ***** EEPROM ***********************
; EEARH - EEPROM Address Register Low Byte
.equ EEAR8 = 0 ; EEPROM Read/Write Access Bit 8
.equ EEAR9 = 1 ; EEPROM Read/Write Access Bit 9
.equ EEAR10 = 2 ; EEPROM Read/Write Access Bit 10
.equ EEAR11 = 3 ; EEPROM Read/Write Access Bit 11
; EEARL - EEPROM Address Register Low Byte
.equ EEAR0 = 0 ; EEPROM Read/Write Access Bit 0
.equ EEAR1 = 1 ; EEPROM Read/Write Access Bit 1
.equ EEAR2 = 2 ; EEPROM Read/Write Access Bit 2
.equ EEAR3 = 3 ; EEPROM Read/Write Access Bit 3
.equ EEAR4 = 4 ; EEPROM Read/Write Access Bit 4
.equ EEAR5 = 5 ; EEPROM Read/Write Access Bit 5
.equ EEAR6 = 6 ; EEPROM Read/Write Access Bit 6
.equ EEAR7 = 7 ; EEPROM Read/Write Access Bit 7
; EEDR - EEPROM Data Register
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
; EECR - EEPROM Control Register
.equ EERE = 0 ; EEPROM Read Enable
.equ EEPE = 1 ; EEPROM Write Enable
.equ EEMPE = 2 ; EEPROM Master Write Enable
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable
.equ EEPM0 = 4 ; EEPROM Programming Mode Bit 0
.equ EEPM1 = 5 ; EEPROM Programming Mode Bit 1
; ***** TIMER_COUNTER_0 **************
; TIMSK0 - Timer/Counter0 Interrupt Mask Register
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable
.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable
; TIFR0 - Timer/Counter0 Interrupt Flag register
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0A
.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B
; TCCR0A - Timer/Counter Control Register A
.equ WGM00 = 0 ; Waveform Generation Mode
.equ WGM01 = 1 ; Waveform Generation Mode
.equ COM0B0 = 4 ; Compare Output Mode, Fast PWm
.equ COM0B1 = 5 ; Compare Output Mode, Fast PWm
.equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode
.equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode
; TCCR0B - Timer/Counter Control Register B
.equ CS00 = 0 ; Clock Select
.equ CS01 = 1 ; Clock Select
.equ CS02 = 2 ; Clock Select
.equ WGM02 = 3 ;
.equ FOC0B = 6 ; Force Output Compare B
.equ FOC0A = 7 ; Force Output Compare A
; TCNT0 - Timer/Counter0
.equ TCNT0_0 = 0 ;
.equ TCNT0_1 = 1 ;
.equ TCNT0_2 = 2 ;
.equ TCNT0_3 = 3 ;
.equ TCNT0_4 = 4 ;
.equ TCNT0_5 = 5 ;
.equ TCNT0_6 = 6 ;
.equ TCNT0_7 = 7 ;
; OCR0A - Timer/Counter0 Output Compare Register
.equ OCROA_0 = 0 ;
.equ OCROA_1 = 1 ;
.equ OCROA_2 = 2 ;
.equ OCROA_3 = 3 ;
.equ OCROA_4 = 4 ;
.equ OCROA_5 = 5 ;
.equ OCROA_6 = 6 ;
.equ OCROA_7 = 7 ;
; OCR0B - Timer/Counter0 Output Compare Register
.equ OCR0B_0 = 0 ;
.equ OCR0B_1 = 1 ;
.equ OCR0B_2 = 2 ;
.equ OCR0B_3 = 3 ;
.equ OCR0B_4 = 4 ;
.equ OCR0B_5 = 5 ;
.equ OCR0B_6 = 6 ;
.equ OCR0B_7 = 7 ;
; GTCCR - General Timer/Counter Control Register
.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0
.equ PSR10 = PSRSYNC ; For compatibility
.equ TSM = 7 ; Timer/Counter Synchronization Mode
; ***** TIMER_COUNTER_2 **************
; TIMSK2 - Timer/Counter Interrupt Mask register
.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable
.equ TOIE2A = TOIE2 ; For compatibility
.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match A Interrupt Enable
.equ OCIE2B = 2 ; Timer/Counter2 Output Compare Match B Interrupt Enable
; TIFR2 - Timer/Counter Interrupt Flag Register
.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag
.equ OCF2A = 1 ; Output Compare Flag 2A
.equ OCF2B = 2 ; Output Compare Flag 2B
; TCCR2A - Timer/Counter2 Control Register A
.equ WGM20 = 0 ; Waveform Genration Mode
.equ WGM21 = 1 ; Waveform Genration Mode
.equ COM2B0 = 4 ; Compare Output Mode bit 0
.equ COM2B1 = 5 ; Compare Output Mode bit 1
.equ COM2A0 = 6 ; Compare Output Mode bit 1
.equ COM2A1 = 7 ; Compare Output Mode bit 1
; TCCR2B - Timer/Counter2 Control Register B
.equ CS20 = 0 ; Clock Select bit 0
.equ CS21 = 1 ; Clock Select bit 1
.equ CS22 = 2 ; Clock Select bit 2
.equ WGM22 = 3 ; Waveform Generation Mode
.equ FOC2B = 6 ; Force Output Compare B
.equ FOC2A = 7 ; Force Output Compare A
; TCNT2 - Timer/Counter2
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7
; OCR2A - Timer/Counter2 Output Compare Register A
.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0
.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1
.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2
.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3
.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4
.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5
.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6
.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7
; OCR2B - Timer/Counter2 Output Compare Register B
;.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0
;.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1
;.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2
;.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3
;.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4
;.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5
;.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6
;.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7
; ASSR - Asynchronous Status Register
.equ TCR2BUB = 0 ; Timer/Counter Control Register2 Update Busy
.equ TCR2AUB = 1 ; Timer/Counter Control Register2 Update Busy
.equ OCR2BUB = 2 ; Output Compare Register 2 Update Busy
.equ OCR2AUB = 3 ; Output Compare Register2 Update Busy
.equ TCN2UB = 4 ; Timer/Counter2 Update Busy
.equ AS2 = 5 ; Asynchronous Timer/Counter2
.equ EXCLK = 6 ; Enable External Clock Input
; GTCCR - General Timer Counter Control register
.equ PSRASY = 1 ; Prescaler Reset Timer/Counter2
.equ PSR2 = PSRASY ; For compatibility
;.equ TSM = 7 ; Timer/Counter Synchronization Mode
; ***** TIMER_COUNTER_3 **************
; TIMSK3 - Timer/Counter3 Interrupt Mask Register
.equ TOIE3 = 0 ; Timer/Counter3 Overflow Interrupt Enable
.equ OCIE3A = 1 ; Timer/Counter3 Output Compare A Match Interrupt Enable
.equ OCIE3B = 2 ; Timer/Counter3 Output Compare B Match Interrupt Enable
.equ OCIE3C = 3 ; Timer/Counter3 Output Compare C Match Interrupt Enable
.equ ICIE3 = 5 ; Timer/Counter3 Input Capture Interrupt Enable
; TIFR3 - Timer/Counter3 Interrupt Flag register
.equ TOV3 = 0 ; Timer/Counter3 Overflow Flag
.equ OCF3A = 1 ; Output Compare Flag 3A
.equ OCF3B = 2 ; Output Compare Flag 3B
.equ OCF3C = 3 ; Output Compare Flag 3C
.equ ICF3 = 5 ; Input Capture Flag 3
; TCCR3A - Timer/Counter3 Control Register A
.equ WGM30 = 0 ; Waveform Generation Mode
.equ WGM31 = 1 ; Waveform Generation Mode
.equ COM3C0 = 2 ; Compare Output Mode 3C, bit 0
.equ COM3C1 = 3 ; Compare Output Mode 3C, bit 1
.equ COM3B0 = 4 ; Compare Output Mode 3B, bit 0
.equ COM3B1 = 5 ; Compare Output Mode 3B, bit 1
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