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📄 pwm3def.inc

📁 AVR Assembler 2 compiler
💻 INC
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.equ	PISEL0A	= 6	; PSC 0 Input Select for Part A
.equ	PCAE0A	= 7	; PSC 0 Capture Enable Input Part A

; PCTL0 - PSC 0 Control Register
.equ	PRUN0	= 0	; PSC 0 Run
.equ	PCCYC0	= 1	; PSC0 Complete Cycle
.equ	PARUN0	= 2	; PSC0 Auto Run
.equ	PAOC0A	= 3	; PSC 0 Asynchronous Output Control A
.equ	PAOC0B	= 4	; PSC 0 Asynchronous Output Control B
.equ	PBFM0	= 5	; PSC 0 Balance Flank Width Modulation
.equ	PPRE00	= 6	; PSC 0 Prescaler Select 0
.equ	PPRE01	= 7	; PSC 0 Prescaler Select 1

; PCNF0 - PSC 0 Configuration Register
.equ	PCLKSEL0	= 1	; PSC 0 Input Clock Select
.equ	POP0	= 2	; PSC 0 Output Polarity
.equ	PMODE00	= 3	; PSC 0 Mode
.equ	PMODE01	= 4	; PSC 0 Mode
.equ	PLOCK0	= 5	; PSC 0 Lock
.equ	PALOCK0	= 6	; PSC 0 Autolock
.equ	PFIFTY0	= 7	; PSC 0 Fifty

; OCR0RBH - Output Compare RB Register High
.equ	OCR0RB_8	= 0	; 
.equ	OCR0RB_9	= 1	; 
.equ	OCR0RB_00	= 2	; 
.equ	OCR0RB_01	= 3	; 
.equ	OCR0RB_02	= 4	; 
.equ	OCR0RB_03	= 5	; 
.equ	OCR0RB_04	= 6	; 
.equ	OCR0RB_05	= 7	; 

; OCR0RBL - Output Compare RB Register Low
.equ	OCR0RB_0	= 0	; 
.equ	OCR0RB_1	= 1	; 
.equ	OCR0RB_2	= 2	; 
.equ	OCR0RB_3	= 3	; 
.equ	OCR0RB_4	= 4	; 
.equ	OCR0RB_5	= 5	; 
.equ	OCR0RB_6	= 6	; 
.equ	OCR0RB_7	= 7	; 

; OCR0SBH - Output Compare SB Register High
.equ	OCR0SB_8	= 0	; 
.equ	OCR0SB_9	= 1	; 
.equ	OCR0SB_00	= 2	; 
.equ	OCR0SB_01	= 3	; 

; OCR0SBL - Output Compare SB Register Low
.equ	OCR0SB_0	= 0	; 
.equ	OCR0SB_1	= 1	; 
.equ	OCR0SB_2	= 2	; 
.equ	OCR0SB_3	= 3	; 
.equ	OCR0SB_4	= 4	; 
.equ	OCR0SB_5	= 5	; 
.equ	OCR0SB_6	= 6	; 
.equ	OCR0SB_7	= 7	; 

; OCR0RAH - Output Compare RA Register High
.equ	OCR0RA_8	= 0	; 
.equ	OCR0RA_9	= 1	; 
.equ	OCR0RA_00	= 2	; 
.equ	OCR0RA_01	= 3	; 

; OCR0RAL - Output Compare RA Register Low
.equ	OCR0RA_0	= 0	; 
.equ	OCR0RA_1	= 1	; 
.equ	OCR0RA_2	= 2	; 
.equ	OCR0RA_3	= 3	; 
.equ	OCR0RA_4	= 4	; 
.equ	OCR0RA_5	= 5	; 
.equ	OCR0RA_6	= 6	; 
.equ	OCR0RA_7	= 7	; 

; OCR0SAH - Output Compare SA Register High
.equ	OCR0SA_8	= 0	; 
.equ	OCR0SA_9	= 1	; 
.equ	OCR0SA_00	= 2	; 
.equ	OCR0SA_01	= 3	; 

; OCR0SAL - Output Compare SA Register Low
.equ	OCR0SA_0	= 0	; 
.equ	OCR0SA_1	= 1	; 
.equ	OCR0SA_2	= 2	; 
.equ	OCR0SA_3	= 3	; 
.equ	OCR0SA_4	= 4	; 
.equ	OCR0SA_5	= 5	; 
.equ	OCR0SA_6	= 6	; 
.equ	OCR0SA_7	= 7	; 

; PSOC0 - PSC0 Synchro and Output Configuration
.equ	POEN0A	= 0	; PSCOUT00 Output Enable
.equ	POEN0B	= 2	; PSCOUT01 Output Enable
.equ	PSYNC00	= 4	; Synchronization Out for ADC Selection
.equ	PSYNC01	= 5	; Synchronization Out for ADC Selection

; PIM0 - PSC0 Interrupt Mask Register
.equ	PEOPE0	= 0	; End of Cycle Interrupt Enable
.equ	PEVE0A	= 3	; External Event A Interrupt Enable
.equ	PEVE0B	= 4	; External Event B Interrupt Enable
.equ	PSEIE0	= 5	; PSC 0 Synchro Error Interrupt Enable

; PIFR0 - PSC0 Interrupt Flag Register
.equ	PEOP0	= 0	; End of PSC0 Interrupt
.equ	PRN00	= 1	; Ramp Number
.equ	PRN01	= 2	; Ramp Number
.equ	PEV0A	= 3	; External Event A Interrupt
.equ	PEV0B	= 4	; External Event B Interrupt
.equ	PSEI0	= 5	; PSC 0 Synchro Error Interrupt


; ***** PSC1 *************************
; PICR1H - PSC 1 Input Capture Register High
.equ	PICR1_8	= 0	; 
.equ	PICR1_9	= 1	; 
.equ	PICR1_10	= 2	; 
.equ	PICR1_11	= 3	; 

; PICR1L - PSC 1 Input Capture Register Low
.equ	PICR1_0	= 0	; 
.equ	PICR1_1	= 1	; 
.equ	PICR1_2	= 2	; 
.equ	PICR1_3	= 3	; 
.equ	PICR1_4	= 4	; 
.equ	PICR1_5	= 5	; 
.equ	PICR1_6	= 6	; 
.equ	PICR1_7	= 7	; 

; PFRC1B - PSC 1 Input B Control
.equ	PRFM1B0	= 0	; PSC 1 Retrigger and Fault Mode for Part B
.equ	PRFM1B1	= 1	; PSC 1 Retrigger and Fault Mode for Part B
.equ	PRFM1B2	= 2	; PSC 1 Retrigger and Fault Mode for Part B
.equ	PRFM1B3	= 3	; PSC 1 Retrigger and Fault Mode for Part B
.equ	PFLTE1B	= 4	; PSC 1 Filter Enable on Input Part B
.equ	PELEV1B	= 5	; PSC 1 Edge Level Selector on Input Part B
.equ	PISEL1B	= 6	; PSC 1 Input Select for Part B
.equ	PCAE1B	= 7	; PSC 1 Capture Enable Input Part B

; PFRC1A - PSC 1 Input B Control
.equ	PRFM1A0	= 0	; PSC 1 Retrigger and Fault Mode for Part A
.equ	PRFM1A1	= 1	; PSC 1 Retrigger and Fault Mode for Part A
.equ	PRFM1A2	= 2	; PSC 1 Retrigger and Fault Mode for Part A
.equ	PRFM1A3	= 3	; PSC 1 Retrigger and Fault Mode for Part A
.equ	PFLTE1A	= 4	; PSC 1 Filter Enable on Input Part A
.equ	PELEV1A	= 5	; PSC 1 Edge Level Selector on Input Part A
.equ	PISEL1A	= 6	; PSC 1 Input Select for Part A
.equ	PCAE1A	= 7	; PSC 1 Capture Enable Input Part A

; PCTL1 - PSC 1 Control Register
.equ	PRUN1	= 0	; PSC 1 Run
.equ	PCCYC1	= 1	; PSC1 Complete Cycle
.equ	PARUN1	= 2	; PSC1 Auto Run
.equ	PAOC1A	= 3	; PSC 1 Asynchronous Output Control A
.equ	PAOC1B	= 4	; PSC 1 Asynchronous Output Control B
.equ	PBFM1	= 5	; Balance Flank Width Modulation
.equ	PPRE10	= 6	; PSC 1 Prescaler Select 0
.equ	PPRE11	= 7	; PSC 1 Prescaler Select 1

; PCNF1 - PSC 1 Configuration Register
.equ	PCLKSEL1	= 1	; PSC 1 Input Clock Select
.equ	POP1	= 2	; PSC 1 Output Polarity
.equ	PMODE10	= 3	; PSC 1 Mode
.equ	PMODE11	= 4	; PSC 1 Mode
.equ	PLOCK1	= 5	; PSC 1 Lock
.equ	PALOCK1	= 6	; PSC 1 Autolock
.equ	PFIFTY1	= 7	; PSC 1 Fifty

; OCR1RBH - Output Compare RB Register High
.equ	OCR1RB_8	= 0	; 
.equ	OCR1RB_9	= 1	; 
.equ	OCR1RB_10	= 2	; 
.equ	OCR1RB_11	= 3	; 
.equ	OCR1RB_12	= 4	; 
.equ	OCR1RB_13	= 5	; 
.equ	OCR1RB_14	= 6	; 
.equ	OCR1RB_15	= 7	; 

; OCR1RBL - Output Compare RB Register Low
.equ	OCR1RB_0	= 0	; 
.equ	OCR1RB_1	= 1	; 
.equ	OCR1RB_2	= 2	; 
.equ	OCR1RB_3	= 3	; 
.equ	OCR1RB_4	= 4	; 
.equ	OCR1RB_5	= 5	; 
.equ	OCR1RB_6	= 6	; 
.equ	OCR1RB_7	= 7	; 

; OCR1SBH - Output Compare SB Register High
.equ	OCR1SB_8	= 0	; 
.equ	OCR1SB_9	= 1	; 
.equ	OCR1SB_10	= 2	; 
.equ	OCR1SB_11	= 3	; 

; OCR1SBL - Output Compare SB Register Low
.equ	OCR1SB_0	= 0	; 
.equ	OCR1SB_1	= 1	; 
.equ	OCR1SB_2	= 2	; 
.equ	OCR1SB_3	= 3	; 
.equ	OCR1SB_4	= 4	; 
.equ	OCR1SB_5	= 5	; 
.equ	OCR1SB_6	= 6	; 
.equ	OCR1SB_7	= 7	; 

; OCR1RAH - Output Compare RA Register High
.equ	OCR1RA_8	= 0	; 
.equ	OCR1RA_9	= 1	; 
.equ	OCR1RA_10	= 2	; 
.equ	OCR1RA_11	= 3	; 

; OCR1RAL - Output Compare RA Register Low
.equ	OCR1RA_0	= 0	; 
.equ	OCR1RA_1	= 1	; 
.equ	OCR1RA_2	= 2	; 
.equ	OCR1RA_3	= 3	; 
.equ	OCR1RA_4	= 4	; 
.equ	OCR1RA_5	= 5	; 
.equ	OCR1RA_6	= 6	; 
.equ	OCR1RA_7	= 7	; 

; OCR1SAH - Output Compare SA Register High
.equ	OCR1SA_8	= 0	; 
.equ	OCR1SA_9	= 1	; 
.equ	OCR1SA_10	= 2	; 
.equ	OCR1SA_11	= 3	; 

; OCR1SAL - Output Compare SA Register Low
.equ	OCR1SA_0	= 0	; 
.equ	OCR1SA_1	= 1	; 
.equ	OCR1SA_2	= 2	; 
.equ	OCR1SA_3	= 3	; 
.equ	OCR1SA_4	= 4	; 
.equ	OCR1SA_5	= 5	; 
.equ	OCR1SA_6	= 6	; 
.equ	OCR1SA_7	= 7	; 

; PSOC1 - PSC1 Synchro and Output Configuration
.equ	POEN1A	= 0	; PSCOUT10 Output Enable
.equ	POEN1B	= 2	; PSCOUT11 Output Enable
.equ	PSYNC1_0	= 4	; Synchronization Out for ADC Selection
.equ	PSYNC1_1	= 5	; Synchronization Out for ADC Selection

; PIM1 - PSC1 Interrupt Mask Register
.equ	PEOPE1	= 0	; End of Cycle Interrupt Enable
.equ	PEVE1A	= 3	; External Event A Interrupt Enable
.equ	PEVE1B	= 4	; External Event B Interrupt Enable
.equ	PSEIE1	= 5	; PSC 1 Synchro Error Interrupt Enable

; PIFR1 - PSC1 Interrupt Flag Register
.equ	PEOP1	= 0	; End of PSC1 Interrupt
.equ	PRN10	= 1	; Ramp Number
.equ	PRN11	= 2	; Ramp Number
.equ	PEV1A	= 3	; External Event A Interrupt
.equ	PEV1B	= 4	; External Event B Interrupt
.equ	PSEI1	= 5	; PSC 1 Synchro Error Interrupt


; ***** PSC2 *************************
; PICR2H - PSC 2 Input Capture Register High
.equ	PICR2_8	= 0	; 
.equ	PICR2_9	= 1	; 
.equ	PICR2_10	= 2	; 
.equ	PICR2_11	= 3	; 

; PICR2L - PSC 2 Input Capture Register Low
.equ	PICR2_0	= 0	; 
.equ	PICR2_1	= 1	; 
.equ	PICR2_2	= 2	; 
.equ	PICR2_3	= 3	; 
.equ	PICR2_4	= 4	; 
.equ	PICR2_5	= 5	; 
.equ	PICR2_6	= 6	; 
.equ	PICR2_7	= 7	; 

; PFRC2B - PSC 2 Input B Control
.equ	PRFM2B0	= 0	; PSC 2 Retrigger and Fault Mode for Part B
.equ	PRFM2B1	= 1	; PSC 2 Retrigger and Fault Mode for Part B
.equ	PRFM2B2	= 2	; PSC 2 Retrigger and Fault Mode for Part B
.equ	PRFM2B3	= 3	; PSC 2 Retrigger and Fault Mode for Part B
.equ	PFLTE2B	= 4	; PSC 2 Filter Enable on Input Part B
.equ	PELEV2B	= 5	; PSC 2 Edge Level Selector on Input Part B
.equ	PISEL2B	= 6	; PSC 2 Input Select for Part B
.equ	PCAE2B	= 7	; PSC 2 Capture Enable Input Part B

; PFRC2A - PSC 2 Input B Control
.equ	PRFM2A0	= 0	; PSC 2 Retrigger and Fault Mode for Part A
.equ	PRFM2A1	= 1	; PSC 2 Retrigger and Fault Mode for Part A
.equ	PRFM2A2	= 2	; PSC 2 Retrigger and Fault Mode for Part A
.equ	PRFM2A3	= 3	; PSC 2 Retrigger and Fault Mode for Part A
.equ	PFLTE2A	= 4	; PSC 2 Filter Enable on Input Part A
.equ	PELEV2A	= 5	; PSC 2 Edge Level Selector on Input Part A
.equ	PISEL2A	= 6	; PSC 2 Input Select for Part A
.equ	PCAE2A	= 7	; PSC 2 Capture Enable Input Part A

; PCTL2 - PSC 2 Control Register
.equ	PRUN2	= 0	; PSC 2 Run
.equ	PCCYC2	= 1	; PSC2 Complete Cycle
.equ	PARUN2	= 2	; PSC2 Auto Run
.equ	PAOC2A	= 3	; PSC 2 Asynchronous Output Control A
.equ	PAOC2B	= 4	; PSC 2 Asynchronous Output Control B
.equ	PBFM2	= 5	; Balance Flank Width Modulation
.equ	PPRE20	= 6	; PSC 2 Prescaler Select 0
.equ	PPRE21	= 7	; PSC 2 Prescaler Select 1

; PCNF2 - PSC 2 Configuration Register
.equ	POME2	= 0	; PSC 2 Output Matrix Enable
.equ	PCLKSEL2	= 1	; PSC 2 Input Clock Select
.equ	POP2	= 2	; PSC 2 Output Polarity
.equ	PMODE20	= 3	; PSC 2 Mode
.equ	PMODE21	= 4	; PSC 2 Mode
.equ	PLOCK2	= 5	; PSC 2 Lock
.equ	PALOCK2	= 6	; PSC 2 Autolock
.equ	PFIFTY2	= 7	; PSC 2 Fifty

; OCR2RBH - Output Compare RB Register High
.equ	OCR2RB_8	= 0	; 
.equ	OCR2RB_9	= 1	; 
.equ	OCR2RB_10	= 2	; 
.equ	OCR2RB_11	= 3	; 
.equ	OCR2RB_12	= 4	; 
.equ	OCR2RB_13	= 5	; 
.equ	OCR2RB_14	= 6	; 
.equ	OCR2RB_15	= 7	; 

; OCR2RBL - Output Compare RB Register Low
.equ	OCR2RB_0	= 0	; 
.equ	OCR2RB_1	= 1	; 
.equ	OCR2RB_2	= 2	; 
.equ	OCR2RB_3	= 3	; 
.equ	OCR2RB_4	= 4	; 
.equ	OCR2RB_5	= 5	; 
.equ	OCR2RB_6	= 6	; 
.equ	OCR2RB_7	= 7	; 

; OCR2SBH - Output Compare SB Register High
.equ	OCR2SB_8	= 0	; 
.equ	OCR2SB_9	= 1	; 
.equ	OCR2SB_10	= 2	; 
.equ	OCR2SB_11	= 3	; 

; OCR2SBL - Output Compare SB Register Low
.equ	OCR2SB_0	= 0	; 
.equ	OCR2SB_1	= 1	; 
.equ	OCR2SB_2	= 2	; 
.equ	OCR2SB_3	= 3	; 
.equ	OCR2SB_4	= 4	; 
.equ	OCR2SB_5	= 5	; 
.equ	OCR2SB_6	= 6	; 
.equ	OCR2SB_7	= 7	; 

; OCR2RAH - Output Compare RA Register High
.equ	OCR2RA_8	= 0	; 
.equ	OCR2RA_9	= 1	; 
.equ	OCR2RA_10	= 2	; 
.equ	OCR2RA_11	= 3	; 

; OCR2RAL - Output Compare RA Register Low
.equ	OCR2RA_0	= 0	; 
.equ	OCR2RA_1	= 1	; 
.equ	OCR2RA_2	= 2	; 
.equ	OCR2RA_3	= 3	; 
.equ	OCR2RA_4	= 4	; 
.equ	OCR2RA_5	= 5	; 
.equ	OCR2RA_6	= 6	; 
.equ	OCR2RA_7	= 7	; 

; OCR2SAH - Output Compare SA Register High
.equ	OCR2SA_8	= 0	; 
.equ	OCR2SA_9	= 1	; 
.equ	OCR2SA_10	= 2	; 
.equ	OCR2SA_11	= 3	; 

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