📄 m32hvbdef.inc
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;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
;***** Created: 2007-12-13 07:27 ******* Source: ATmega32HVB.xml *********
;*************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number : AVR000
;* File Name : "m32HVBdef.inc"
;* Title : Register/Bit Definitions for the ATmega32HVB
;* Date : 2007-12-13
;* Version : 2.24
;* Support E-mail : avr@atmel.com
;* Target MCU : ATmega32HVB
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;* The Register names are represented by their hexadecimal address.
;*
;* The Register Bit names are represented by their bit number (0-7).
;*
;* Please observe the difference in using the bit names with instructions
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
;* (skip if bit in register set/cleared). The following example illustrates
;* this:
;*
;* in r16,PORTB ;read PORTB latch
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
;* out PORTB,r16 ;output to PORTB
;*
;* in r16,TIFR ;read the Timer Interrupt Flag Register
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
;* rjmp TOV0_is_set ;jump if set
;* ... ;otherwise do something else
;*************************************************************************
#ifndef _M32HVBDEF_INC_
#define _M32HVBDEF_INC_
#pragma partinc 0
; ***** SPECIFY DEVICE ***************************************************
.device ATmega32HVB
#pragma AVRPART ADMIN PART_NAME ATmega32HVB
.equ SIGNATURE_000 = 0x1e
.equ SIGNATURE_001 = 0x95
.equ SIGNATURE_002 = 0x10
#pragma AVRPART CORE CORE_VERSION V2E
; ***** I/O REGISTER DEFINITIONS *****************************************
; NOTE:
; Definitions marked "MEMORY MAPPED"are extended I/O ports
; and cannot be used with IN/OUT instructions
.equ BPPLR = 0xfe ; MEMORY MAPPED
.equ BPCR = 0xfd ; MEMORY MAPPED
.equ BPHCTR = 0xfc ; MEMORY MAPPED
.equ BPOCTR = 0xfb ; MEMORY MAPPED
.equ BPSCTR = 0xfa ; MEMORY MAPPED
.equ BPCHCD = 0xf9 ; MEMORY MAPPED
.equ BPDHCD = 0xf8 ; MEMORY MAPPED
.equ BPCOCD = 0xf7 ; MEMORY MAPPED
.equ BPDOCD = 0xf6 ; MEMORY MAPPED
.equ BPSCD = 0xf5 ; MEMORY MAPPED
.equ BPIFR = 0xf3 ; MEMORY MAPPED
.equ BPIMSK = 0xf2 ; MEMORY MAPPED
.equ CBCR = 0xf1 ; MEMORY MAPPED
.equ FCSR = 0xf0 ; MEMORY MAPPED
.equ CADRDC = 0xea ; MEMORY MAPPED
.equ CADRCC = 0xe9 ; MEMORY MAPPED
.equ CADCSRC = 0xe8 ; MEMORY MAPPED
.equ CADCSRB = 0xe7 ; MEMORY MAPPED
.equ CADCSRA = 0xe6 ; MEMORY MAPPED
.equ CADICL = 0xe4 ; MEMORY MAPPED
.equ CADICH = 0xe5 ; MEMORY MAPPED
.equ CADAC3 = 0xe3 ; MEMORY MAPPED
.equ CADAC2 = 0xe2 ; MEMORY MAPPED
.equ CADAC1 = 0xe1 ; MEMORY MAPPED
.equ CADAC0 = 0xe0 ; MEMORY MAPPED
.equ CHGDCSR = 0xd4 ; MEMORY MAPPED
.equ BGCSR = 0xd2 ; MEMORY MAPPED
.equ BGCRR = 0xd1 ; MEMORY MAPPED
.equ BGCCR = 0xd0 ; MEMORY MAPPED
.equ ROCR = 0xc8 ; MEMORY MAPPED
.equ TWBCSR = 0xbe ; MEMORY MAPPED
.equ TWAMR = 0xbd ; MEMORY MAPPED
.equ TWCR = 0xbc ; MEMORY MAPPED
.equ TWDR = 0xbb ; MEMORY MAPPED
.equ TWAR = 0xba ; MEMORY MAPPED
.equ TWSR = 0xb9 ; MEMORY MAPPED
.equ TWBR = 0xb8 ; MEMORY MAPPED
.equ OCR1B = 0x89 ; MEMORY MAPPED
.equ OCR1A = 0x88 ; MEMORY MAPPED
.equ TCNT1L = 0x84 ; MEMORY MAPPED
.equ TCNT1H = 0x85 ; MEMORY MAPPED
.equ TCCR1B = 0x81 ; MEMORY MAPPED
.equ TCCR1A = 0x80 ; MEMORY MAPPED
.equ DIDR0 = 0x7e ; MEMORY MAPPED
.equ VADMUX = 0x7c ; MEMORY MAPPED
.equ VADCSR = 0x7a ; MEMORY MAPPED
.equ VADCL = 0x78 ; MEMORY MAPPED
.equ VADCH = 0x79 ; MEMORY MAPPED
.equ TIMSK1 = 0x6f ; MEMORY MAPPED
.equ TIMSK0 = 0x6e ; MEMORY MAPPED
.equ PCMSK0 = 0x6b ; MEMORY MAPPED
.equ PCMSK1 = 0x6c ; MEMORY MAPPED
.equ EICRA = 0x69 ; MEMORY MAPPED
.equ PCICR = 0x68 ; MEMORY MAPPED
.equ FOSCCAL = 0x66 ; MEMORY MAPPED
.equ PRR0 = 0x64 ; MEMORY MAPPED
.equ CLKPR = 0x61 ; MEMORY MAPPED
.equ WDTCSR = 0x60 ; MEMORY MAPPED
.equ SREG = 0x3f
.equ SPL = 0x3d
.equ SPH = 0x3e
.equ SPMCSR = 0x37
.equ MCUCR = 0x35
.equ MCUSR = 0x34
.equ SMCR = 0x33
.equ DWDR = 0x31
.equ SPDR = 0x2e
.equ SPSR = 0x2d
.equ SPCR = 0x2c
.equ GPIOR2 = 0x2b
.equ GPIOR1 = 0x2a
.equ OCR0B = 0x29
.equ OCR0A = 0x28
.equ TCNT0L = 0x26
.equ TCNT0H = 0x27
.equ TCCR0B = 0x25
.equ TCCR0A = 0x24
.equ GTCCR = 0x23
.equ EEARL = 0x21
.equ EEARH = 0x22
.equ EEDR = 0x20
.equ EECR = 0x1f
.equ GPIOR0 = 0x1e
.equ EIMSK = 0x1d
.equ EIFR = 0x1c
.equ PCIFR = 0x1b
.equ OSICSR = 0x17
.equ TIFR1 = 0x16
.equ TIFR0 = 0x15
.equ PORTC = 0x08
.equ PINC = 0x06
.equ PORTB = 0x05
.equ DDRB = 0x04
.equ PINB = 0x03
.equ PORTA = 0x02
.equ DDRA = 0x01
.equ PINA = 0x00
; ***** BIT DEFINITIONS **************************************************
; ***** AD_CONVERTER *****************
; VADMUX - The VADC multiplexer Selection Register
.equ VADMUX0 = 0 ; Analog Channel and Gain Selection Bits
.equ VADMUX1 = 1 ; Analog Channel and Gain Selection Bits
.equ VADMUX2 = 2 ; Analog Channel and Gain Selection Bits
.equ VADMUX3 = 3 ; Analog Channel and Gain Selection Bits
; VADCSR - The VADC Control and Status register
.equ VADCCIE = 0 ; VADC Conversion Complete Interrupt Enable
.equ VADCCIF = 1 ; VADC Conversion Complete Interrupt Flag
.equ VADSC = 2 ; VADC Satrt Conversion
.equ VADEN = 3 ; VADC Enable
; ***** WATCHDOG *********************
; WDTCSR - Watchdog Timer Control Register
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
.equ WDE = 3 ; Watch Dog Enable
.equ WDCE = 4 ; Watchdog Change Enable
.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3
.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable
.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag
; ***** FET **************************
; FCSR - FET Control and Status Register
.equ CFE = 0 ; Charge FET Enable
.equ DFE = 1 ; Discharge FET Enable
.equ CPS = 2 ; Current Protection Status
.equ DUVRD = 3 ; Deep Under-Voltage Recovery Disable
; ***** SPI **************************
; SPDR - SPI Data Register
.equ SPDR0 = 0 ; SPI Data Register bit 0
.equ SPDR1 = 1 ; SPI Data Register bit 1
.equ SPDR2 = 2 ; SPI Data Register bit 2
.equ SPDR3 = 3 ; SPI Data Register bit 3
.equ SPDR4 = 4 ; SPI Data Register bit 4
.equ SPDR5 = 5 ; SPI Data Register bit 5
.equ SPDR6 = 6 ; SPI Data Register bit 6
.equ SPDR7 = 7 ; SPI Data Register bit 7
; SPSR - SPI Status Register
.equ SPI2X = 0 ; Double SPI Speed Bit
.equ WCOL = 6 ; Write Collision Flag
.equ SPIF = 7 ; SPI Interrupt Flag
; SPCR - SPI Control Register
.equ SPR0 = 0 ; SPI Clock Rate Select 0
.equ SPR1 = 1 ; SPI Clock Rate Select 1
.equ CPHA = 2 ; Clock Phase
.equ CPOL = 3 ; Clock polarity
.equ MSTR = 4 ; Master/Slave Select
.equ DORD = 5 ; Data Order
.equ SPE = 6 ; SPI Enable
.equ SPIE = 7 ; SPI Interrupt Enable
; ***** EEPROM ***********************
; EEDR - EEPROM Data Register
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
; EECR - EEPROM Control Register
.equ EERE = 0 ; EEPROM Read Enable
.equ EEPE = 1 ; EEPROM Write Enable
.equ EEWE = EEPE ; For compatibility
.equ EEMPE = 2 ; EEPROM Master Write Enable
.equ EEMWE = EEMPE ; For compatibility
.equ EERIE = 3 ; EEProm Ready Interrupt Enable
.equ EEPM0 = 4 ;
.equ EEPM1 = 5 ;
; ***** COULOMB_COUNTER **************
; CADCSRA - CC-ADC Control and Status Register A
.equ CADSE = 0 ; When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode.
.equ CADSI0 = 1 ; The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
.equ CADSI1 = 2 ; The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined.
.equ CADAS0 = 3 ; CC_ADC Accumulate Current Select Bit 0
.equ CADAS1 = 4 ; CC_ADC Accumulate Current Select Bit 1
.equ CADUB = 5 ; CC_ADC Update Busy
.equ CADPOL = 6 ;
.equ CADEN = 7 ; When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled.
; CADCSRB - CC-ADC Control and Status Register B
.equ CADICIF = 0 ; CC-ADC Instantaneous Current Interrupt Flag
.equ CADRCIF = 1 ; CC-ADC Accumulate Current Interrupt Flag
.equ CADACIF = 2 ; CC-ADC Accumulate Current Interrupt Flag
.equ CADICIE = 4 ; CAD Instantenous Current Interrupt Enable
.equ CADRCIE = 5 ; Regular Current Interrupt Enable
.equ CADACIE = 6 ;
; CADCSRC - CC-ADC Control and Status Register C
.equ CADVSE = 0 ; CC-ADC Voltage Scaling Enable
; CADAC3 - ADC Accumulate Current
.equ CADAC24 = 0 ;
.equ CADAC25 = 1 ;
.equ CADAC26 = 2 ;
.equ CADAC27 = 3 ;
.equ CADAC28 = 4 ;
.equ CADAC29 = 5 ;
.equ CADAC30 = 6 ;
.equ CADAC31 = 7 ;
; CADAC2 - ADC Accumulate Current
.equ CADAC16 = 0 ;
.equ CADAC17 = 1 ;
.equ CADAC18 = 2 ;
.equ CADAC19 = 3 ;
.equ CADAC20 = 4 ;
.equ CADAC21 = 5 ;
.equ CADAC22 = 6 ;
.equ CADAC23 = 7 ;
; CADAC1 - ADC Accumulate Current
.equ CADAC08 = 0 ;
.equ CADAC09 = 1 ;
.equ CADAC10 = 2 ;
.equ CADAC11 = 3 ;
.equ CADAC12 = 4 ;
.equ CADAC13 = 5 ;
.equ CADAC14 = 6 ;
.equ CADAC15 = 7 ;
; CADAC0 - ADC Accumulate Current
.equ CADAC00 = 0 ;
.equ CADAC01 = 1 ;
.equ CADAC02 = 2 ;
.equ CADAC03 = 3 ;
.equ CADAC04 = 4 ;
.equ CADAC05 = 5 ;
.equ CADAC06 = 6 ;
.equ CADAC07 = 7 ;
; CADRCC - CC-ADC Regular Charge Current
.equ CADRCC0 = 0 ;
.equ CADRCC1 = 1 ;
.equ CADRCC2 = 2 ;
.equ CADRCC3 = 3 ;
.equ CADRCC4 = 4 ;
.equ CADRCC5 = 5 ;
.equ CADRCC6 = 6 ;
.equ CADRCC7 = 7 ;
; CADRDC - CC-ADC Regular Discharge Current
.equ CADRDC0 = 0 ;
.equ CADRDC1 = 1 ;
.equ CADRDC2 = 2 ;
.equ CADRDC3 = 3 ;
.equ CADRDC4 = 4 ;
.equ CADRDC5 = 5 ;
.equ CADRDC6 = 6 ;
.equ CADRDC7 = 7 ;
; ***** TWI **************************
; TWBCSR - TWI Bus Control and Status Register
.equ TWBCIP = 0 ; TWI Bus Connect/Disconnect Interrupt Polarity
.equ TWBDT0 = 1 ; TWI Bus Disconnect Time-out Period
.equ TWBDT1 = 2 ; TWI Bus Disconnect Time-out Period
.equ TWBCIE = 6 ; TWI Bus Connect/Disconnect Interrupt Enable
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