m3250def.inc

AVR Assembler 2 compiler

.equ	GPIOR00	= 0	; General Purpose IO Register 0 bit 0
.equ	GPIOR01	= 1	; General Purpose IO Register 0 bit 1
.equ	GPIOR02	= 2	; General Purpose IO Register 0 bit 2
.equ	GPIOR03	= 3	; General Purpose IO Register 0 bit 3
.equ	GPIOR04	= 4	; General Purpose IO Register 0 bit 4
.equ	GPIOR05	= 5	; General Purpose IO Register 0 bit 5
.equ	GPIOR06	= 6	; General Purpose IO Register 0 bit 6
.equ	GPIOR07	= 7	; General Purpose IO Register 0 bit 7


; ***** USI **************************
; USIDR - USI Data Register
.equ	USIDR0	= 0	; USI Data Register bit 0
.equ	USIDR1	= 1	; USI Data Register bit 1
.equ	USIDR2	= 2	; USI Data Register bit 2
.equ	USIDR3	= 3	; USI Data Register bit 3
.equ	USIDR4	= 4	; USI Data Register bit 4
.equ	USIDR5	= 5	; USI Data Register bit 5
.equ	USIDR6	= 6	; USI Data Register bit 6
.equ	USIDR7	= 7	; USI Data Register bit 7

; USISR - USI Status Register
.equ	USICNT0	= 0	; USI Counter Value Bit 0
.equ	USICNT1	= 1	; USI Counter Value Bit 1
.equ	USICNT2	= 2	; USI Counter Value Bit 2
.equ	USICNT3	= 3	; USI Counter Value Bit 3
.equ	USIDC	= 4	; Data Output Collision
.equ	USIPF	= 5	; Stop Condition Flag
.equ	USIOIF	= 6	; Counter Overflow Interrupt Flag
.equ	USISIF	= 7	; Start Condition Interrupt Flag

; USICR - USI Control Register
.equ	USITC	= 0	; Toggle Clock Port Pin
.equ	USICLK	= 1	; Clock Strobe
.equ	USICS0	= 2	; USI Clock Source Select Bit 0
.equ	USICS1	= 3	; USI Clock Source Select Bit 1
.equ	USIWM0	= 4	; USI Wire Mode Bit 0
.equ	USIWM1	= 5	; USI Wire Mode Bit 1
.equ	USIOIE	= 6	; Counter Overflow Interrupt Enable
.equ	USISIE	= 7	; Start Condition Interrupt Enable


; ***** AD_CONVERTER *****************
; ADMUX - The ADC multiplexer Selection Register
.equ	MUX0	= 0	; Analog Channel and Gain Selection Bits
.equ	MUX1	= 1	; Analog Channel and Gain Selection Bits
.equ	MUX2	= 2	; Analog Channel and Gain Selection Bits
.equ	MUX3	= 3	; Analog Channel and Gain Selection Bits
.equ	MUX4	= 4	; Analog Channel and Gain Selection Bits
.equ	ADLAR	= 5	; Left Adjust Result
.equ	REFS0	= 6	; Reference Selection Bit 0
.equ	REFS1	= 7	; Reference Selection Bit 1

; ADCSRA - The ADC Control and Status register
.equ	ADPS0	= 0	; ADC  Prescaler Select Bits
.equ	ADPS1	= 1	; ADC  Prescaler Select Bits
.equ	ADPS2	= 2	; ADC  Prescaler Select Bits
.equ	ADIE	= 3	; ADC Interrupt Enable
.equ	ADIF	= 4	; ADC Interrupt Flag
.equ	ADATE	= 5	; ADC Auto Trigger Enable
.equ	ADSC	= 6	; ADC Start Conversion
.equ	ADEN	= 7	; ADC Enable

; ADCH - ADC Data Register High Byte
.equ	ADCH0	= 0	; ADC Data Register High Byte Bit 0
.equ	ADCH1	= 1	; ADC Data Register High Byte Bit 1
.equ	ADCH2	= 2	; ADC Data Register High Byte Bit 2
.equ	ADCH3	= 3	; ADC Data Register High Byte Bit 3
.equ	ADCH4	= 4	; ADC Data Register High Byte Bit 4
.equ	ADCH5	= 5	; ADC Data Register High Byte Bit 5
.equ	ADCH6	= 6	; ADC Data Register High Byte Bit 6
.equ	ADCH7	= 7	; ADC Data Register High Byte Bit 7

; ADCL - ADC Data Register Low Byte
.equ	ADCL0	= 0	; ADC Data Register Low Byte Bit 0
.equ	ADCL1	= 1	; ADC Data Register Low Byte Bit 1
.equ	ADCL2	= 2	; ADC Data Register Low Byte Bit 2
.equ	ADCL3	= 3	; ADC Data Register Low Byte Bit 3
.equ	ADCL4	= 4	; ADC Data Register Low Byte Bit 4
.equ	ADCL5	= 5	; ADC Data Register Low Byte Bit 5
.equ	ADCL6	= 6	; ADC Data Register Low Byte Bit 6
.equ	ADCL7	= 7	; ADC Data Register Low Byte Bit 7

; ADCSRB - ADC Control and Status Register B
.equ	ADTS0	= 0	; ADC Auto Trigger Source 0
.equ	ADTS1	= 1	; ADC Auto Trigger Source 1
.equ	ADTS2	= 2	; ADC Auto Trigger Source 2

; DIDR0 - Digital Input Disable Register 0
.equ	ADC0D	= 0	; ADC0 Digital input Disable
.equ	ADC1D	= 1	; ADC1 Digital input Disable
.equ	ADC2D	= 2	; ADC2 Digital input Disable
.equ	ADC3D	= 3	; ADC3 Digital input Disable
.equ	ADC4D	= 4	; ADC4 Digital input Disable
.equ	ADC5D	= 5	; ADC5 Digital input Disable
.equ	ADC6D	= 6	; ADC6 Digital input Disable
.equ	ADC7D	= 7	; ADC7 Digital input Disable


; ***** BOOT_LOAD ********************
; SPMCSR - Store Program Memory Control Register
.equ	SPMCR	= SPMCSR	; For compatibility
.equ	SPMEN	= 0	; Store Program Memory Enable
.equ	PGERS	= 1	; Page Erase
.equ	PGWRT	= 2	; Page Write
.equ	BLBSET	= 3	; Boot Lock Bit Set
.equ	RWWSRE	= 4	; Read While Write section read enable
.equ	ASRE	= RWWSRE	; For compatibility
.equ	RWWSB	= 6	; Read While Write Section Busy
.equ	ASB	= RWWSB	; For compatibility
.equ	SPMIE	= 7	; SPM Interrupt Enable


; ***** USART0 ***********************
; UDR0 - USART I/O Data Register
.equ	UDR	= UDR0	; For compatibility
.equ	UDR00	= 0	; USART I/O Data Register bit 0
.equ	UDR01	= 1	; USART I/O Data Register bit 1
.equ	UDR02	= 2	; USART I/O Data Register bit 2
.equ	UDR03	= 3	; USART I/O Data Register bit 3
.equ	UDR04	= 4	; USART I/O Data Register bit 4
.equ	UDR05	= 5	; USART I/O Data Register bit 5
.equ	UDR06	= 6	; USART I/O Data Register bit 6
.equ	UDR07	= 7	; USART I/O Data Register bit 7

; UCSR0A - USART Control and Status Register A
.equ	UCSRA	= UCSR0A	; For compatibility
.equ	USR	= UCSR0A	; For compatibility
.equ	MPCM0	= 0	; Multi-processor Communication Mode
.equ	MPCM	= MPCM0	; For compatibility
.equ	U2X0	= 1	; Double the USART Transmission Speed
.equ	U2X	= U2X0	; For compatibility
.equ	UPE0	= 2	; USART Parity Error
.equ	UPE	= UPE0	; For compatibility
.equ	DOR0	= 3	; Data OverRun
.equ	DOR	= DOR0	; For compatibility
.equ	FE0	= 4	; Framing Error
.equ	FE	= FE0	; For compatibility
.equ	UDRE0	= 5	; USART Data Register Empty
.equ	UDRE	= UDRE0	; For compatibility
.equ	TXC0	= 6	; USART Transmit Complete
.equ	TXC	= TXC0	; For compatibility
.equ	RXC0	= 7	; USART Receive Complete
.equ	RXC	= RXC0	; For compatibility

; UCSR0B - USART Control and Status Register B
.equ	UCSRB	= UCSR0B	; For compatibility
.equ	UCR	= UCSR0B	; For compatibility
.equ	TXB80	= 0	; Transmit Data Bit 8
.equ	TXB8	= TXB80	; For compatibility
.equ	RXB80	= 1	; Receive Data Bit 8
.equ	RXB8	= RXB80	; For compatibility
.equ	UCSZ02	= 2	; Character Size
.equ	UCSZ2	= UCSZ02	; For compatibility
.equ	TXEN0	= 3	; Transmitter Enable
.equ	TXEN	= TXEN0	; For compatibility
.equ	RXEN0	= 4	; Receiver Enable
.equ	RXEN	= RXEN0	; For compatibility
.equ	UDRIE0	= 5	; USART Data Register Empty Interrupt Enable
.equ	UDRIE	= UDRIE0	; For compatibility
.equ	TXCIE0	= 6	; TX Complete Interrupt Enable
.equ	TXCIE	= TXCIE0	; For compatibility
.equ	RXCIE0	= 7	; RX Complete Interrupt Enable
.equ	RXCIE	= RXCIE0	; For compatibility

; UCSR0C - USART Control and Status Register C
.equ	UCSRC	= UCSR0C	; For compatibility
.equ	UCPOL0	= 0	; Clock Polarity
.equ	UCPOL	= UCPOL0	; For compatibility
.equ	UCSZ00	= 1	; Character Size
.equ	UCSZ0	= UCSZ00	; For compatibility
.equ	UCSZ01	= 2	; Character Size
.equ	UCSZ1	= UCSZ01	; For compatibility
.equ	USBS0	= 3	; Stop Bit Select
.equ	USBS	= USBS0	; For compatibility
.equ	UPM00	= 4	; Parity Mode Bit 0
.equ	UPM0	= UPM00	; For compatibility
.equ	UPM01	= 5	; Parity Mode Bit 1
.equ	UPM1	= UPM01	; For compatibility
.equ	UMSEL0	= 6	; USART Mode Select
.equ	UMSEL	= UMSEL0	; For compatibility

; UBRR0H - USART Baud Rate Register High Byte
.equ	UBRRH	= UBRR0H	; For compatibility
.equ	UBRR8	= 0	; USART Baud Rate Register bit 8
.equ	UBRR9	= 1	; USART Baud Rate Register bit 9
.equ	UBRR10	= 2	; USART Baud Rate Register bit 10
.equ	UBRR11	= 3	; USART Baud Rate Register bit 11

; UBRR0L - USART Baud Rate Register Low Byte
.equ	UBRRL	= UBRR0L	; For compatibility
.equ	UBRR	= UBRR0L	; For compatibility
.equ	UBRR0	= 0	; USART Baud Rate Register bit 0
.equ	UBRR1	= 1	; USART Baud Rate Register bit 1
.equ	UBRR2	= 2	; USART Baud Rate Register bit 2
.equ	UBRR3	= 3	; USART Baud Rate Register bit 3
.equ	UBRR4	= 4	; USART Baud Rate Register bit 4
.equ	UBRR5	= 5	; USART Baud Rate Register bit 5
.equ	UBRR6	= 6	; USART Baud Rate Register bit 6
.equ	UBRR7	= 7	; USART Baud Rate Register bit 7


; ***** PORTH ************************
; PORTH - PORT H Data Register
.equ	PORTH0	= 0	; PORT H Data Register bit 0
.equ	PH0	= 0	; For compatibility
.equ	PORTH1	= 1	; PORT H Data Register bit 1
.equ	PH1	= 1	; For compatibility
.equ	PORTH2	= 2	; PORT H Data Register bit 2
.equ	PH2	= 2	; For compatibility
.equ	PORTH3	= 3	; PORT H Data Register bit 3
.equ	PH3	= 3	; For compatibility
.equ	PORTH4	= 4	; PORT H Data Register bit 4
.equ	PH4	= 4	; For compatibility
.equ	PORTH5	= 5	; PORT H Data Register bit 5
.equ	PH5	= 5	; For compatibility
.equ	PORTH6	= 6	; PORT H Data Register bit 6
.equ	PH6	= 6	; For compatibility
.equ	PORTH7	= 7	; PORT H Data Register bit 7
.equ	PH7	= 7	; For compatibility

; DDRH - PORT H Data Direction Register
.equ	DDH0	= 0	; PORT H Data Direction Register bit 0
.equ	DDH1	= 1	; PORT H Data Direction Register bit 1
.equ	DDH2	= 2	; PORT H Data Direction Register bit 2
.equ	DDH3	= 3	; PORT H Data Direction Register bit 3
.equ	DDH4	= 4	; PORT H Data Direction Register bit 4
.equ	DDH5	= 5	; PORT H Data Direction Register bit 5
.equ	DDH6	= 6	; PORT H Data Direction Register bit 6
.equ	DDH7	= 7	; PORT H Data Direction Register bit 7

; PINH - PORT H Input Pins
.equ	PINH0	= 0	; PORT H Input Pins bit 0
.equ	PINH1	= 1	; PORT H Input Pins bit 1
.equ	PINH2	= 2	; PORT H Input Pins bit 2
.equ	PINH3	= 3	; PORT H Input Pins bit 3
.equ	PINH4	= 4	; PORT H Input Pins bit 4
.equ	PINH5	= 5	; PORT H Input Pins bit 5
.equ	PINH6	= 6	; PORT H Input Pins bit 6
.equ	PINH7	= 7	; PORT H Input Pins bit 7


; ***** PORTJ ************************
; PORTJ - PORT J Data Register
.equ	PORTJ0	= 0	; PORT J Data Register bit 0
.equ	PJ0	= 0	; For compatibility
.equ	PORTJ1	= 1	; PORT J Data Register bit 1
.equ	PJ1	= 1	; For compatibility
.equ	PORTJ2	= 2	; PORT J Data Register bit 2
.equ	PJ2	= 2	; For compatibility
.equ	PORTJ3	= 3	; PORT J Data Register bit 3
.equ	PJ3	= 3	; For compatibility
.equ	PORTJ4	= 4	; PORT J Data Register bit 4
.equ	PJ4	= 4	; For compatibility
.equ	PORTJ5	= 5	; PORT J Data Register bit 5
.equ	PJ5	= 5	; For compatibility
.equ	PORTJ6	= 6	; PORT J Data Register bit 6
.equ	PJ6	= 6	; For compatibility

; DDRJ - PORT J Data Direction Register
.equ	DDJ0	= 0	; PORT J Data Direction Register bit 0
.equ	DDJ1	= 1	; PORT J Data Direction Register bit 1
.equ	DDJ2	= 2	; PORT J Data Direction Register bit 2
.equ	DDJ3	= 3	; PORT J Data Direction Register bit 3
.equ	DDJ4	= 4	; PORT J Data Direction Register bit 4
.equ	DDJ5	= 5	; PORT J Data Direction Register bit 5
.equ	DDJ6	= 6	; PORT J Data Direction Register bit 6

; PINJ - PORT J Input Pins
.equ	PINJ0	= 0	; PORT J Input Pins bit 0
.equ	PINJ1	= 1	; PORT J Input Pins bit 1
.equ	PINJ2	= 2	; PORT J Input Pins bit 2
.equ	PINJ3	= 3	; PORT J Input Pins bit 3
.equ	PINJ4	= 4	; PORT J Input Pins bit 4
.equ	PINJ5	= 5	; PORT J Input Pins bit 5
.equ	PINJ6	= 6	; PORT J Input Pins bit 6



; ***** LOCKSBITS ********************************************************
.equ	LB1	= 0	; Lock bit
.equ	LB2	= 1	; Lock bit
.equ	BLB01	= 2	; Boot Lock bit
.equ	BLB02	= 3	; Boot Lock bit
.equ	BLB11	= 4	; Boot lock bit
.equ	BLB12	= 5	; Boot lock bit


; ***** FUSES ************************************************************
; LOW fuse bits
.equ	CKSEL0	= 0	; Select Clock Source
.equ	CKSEL1	= 1	; Select Clock Source
.equ	CKSEL2	= 2	; Select Clock Source
.equ	CKSEL3	= 3	; Select Clock Source
.equ	SUT0	= 4	; Select start-up time
.equ	SUT1	= 5	; Select start-up time
.equ	CKOUT	= 6	; Oscillator options
.equ	CKDIV8	= 7	; Divide clock by 8

; HIGH fuse bits
.equ	BOOTRST	= 0	; Select Reset Vector
.equ	BOOTSZ0	= 1	; Select Boot Size
.equ	BOOTSZ1	= 2	; Select Boot Size
.equ	EESAVE	= 3	; EEPROM memory is preserved through chip erase
.equ	WDTON	= 4	; Watchdog timer always on
.equ	SPIEN	= 5	; Enable Serial programming and Data Downloading
.equ	JTAGEN	= 6	; Enable JTAG
.equ	OCDEN	= 7	; Enable OCD

; EXTENDED fuse bits
.equ	RSTDISBL	= 0	; Reset disable fuse
.equ	BODLEVEL0	= 1	; Brown-out Detector trigger level
.equ	BODLEVEL1	= 2	; Brown-out Detector trigger level



; ***** CPU REGISTER DEFINITIONS *****************************************
.def	XH	= r27
.def	XL	= r26
.def	YH	= r29
.def	YL	= r28
.def	ZH	= r31
.def	ZL	= r30



; ***** DATA MEMORY DECLARATIONS *****************************************
.equ	FLASHEND	= 0x3fff	; Note: Word address
.equ	IOEND	= 0x00ff
.equ	SRAM_START	= 0x0100
.equ	SRAM_SIZE	= 2048
.equ	RAMEND	= 0x08ff
.equ	XRAMEND	= 0x0000
.equ	E2END	= 0x03ff
.equ	EEPROMEND	= 0x03ff
.equ	EEADRBITS	= 10
#pragma AVRPART MEMORY PROG_FLASH 32768
#pragma AVRPART MEMORY EEPROM 1024
#pragma AVRPART MEMORY INT_SRAM SIZE 2048
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100



; ***** BOOTLOADER DECLARATIONS ******************************************
.equ	NRWW_START_ADDR	= 0x3800
.equ	NRWW_STOP_ADDR	= 0x3fff
.equ	RWW_START_ADDR	= 0x0
.equ	RWW_STOP_ADDR	= 0x37ff
.equ	PAGESIZE	= 64
.equ	FIRSTBOOTSTART	= 0x3f00
.equ	SECONDBOOTSTART	= 0x3e00
.equ	THIRDBOOTSTART	= 0x3c00
.equ	FOURTHBOOTSTART	= 0x3800
.equ	SMALLBOOTSTART	= FIRSTBOOTSTART
.equ	LARGEBOOTSTART	= FOURTHBOOTSTART



; ***** INTERRUPT VECTORS ************************************************
.equ	INT0addr	= 0x0002	; External Interrupt Request 0
.equ	PCI0addr	= 0x0004	; Pin Change Interrupt Request 0
.equ	PCI1addr	= 0x0006	; Pin Change Interrupt Request 1
.equ	OC2addr	= 0x0008	; Timer/Counter2 Compare Match
.equ	OVF2addr	= 0x000a	; Timer/Counter2 Overflow
.equ	ICP1addr	= 0x000c	; Timer/Counter1 Capture Event
.equ	OC1Aaddr	= 0x000e	; Timer/Counter1 Compare Match A
.equ	OC1Baddr	= 0x0010	; Timer/Counter Compare Match B
.equ	OVF1addr	= 0x0012	; Timer/Counter1 Overflow
.equ	OC0addr	= 0x0014	; Timer/Counter0 Compare Match
.equ	OVF0addr	= 0x0016	; Timer/Counter0 Overflow
.equ	SPIaddr	= 0x0018	; SPI Serial Transfer Complete
.equ	URXCaddr	= 0x001a	; USART, Rx Complete
.equ	URXC0addr	= 0x001a	; For compatibility
.equ	UDREaddr	= 0x001c	; USART Data register Empty
.equ	UDRE0addr	= 0x001c	; For compatibility
.equ	UTXC0addr	= 0x001e	; USART0, Tx Complete
.equ	UTXCaddr	= 0x001e	; For compatibility
.equ	USI_STARTaddr	= 0x0020	; USI Start Condition
.equ	USI_OVFaddr	= 0x0022	; USI Overflow
.equ	ACIaddr	= 0x0024	; Analog Comparator
.equ	ADCCaddr	= 0x0026	; ADC Conversion Complete
.equ	ERDYaddr	= 0x0028	; EEPROM Ready
.equ	SPMRaddr	= 0x002a	; Store Program Memory Read
.equ	RESERVEDaddr	= 0x002c	; RESERVED
.equ	PCI2addr	= 0x002e	; Pin Change Interrupt Request 2
.equ	PCI3addr	= 0x0030	; Pin Change Interrupt Request 3

.equ	INT_VECTORS_SIZE	= 50	; size in words

#endif  /* _M3250DEF_INC_ */

; ***** END OF FILE ******************************************************