📄 m640def.inc
字号:
; CLKPR -
.equ CLKPS0 = 0 ;
.equ CLKPS1 = 1 ;
.equ CLKPS2 = 2 ;
.equ CLKPS3 = 3 ;
.equ CLKPCE = 7 ;
; SMCR - Sleep Mode Control Register
.equ SE = 0 ; Sleep Enable
.equ SM0 = 1 ; Sleep Mode Select bit 0
.equ SM1 = 2 ; Sleep Mode Select bit 1
.equ SM2 = 3 ; Sleep Mode Select bit 2
; RAMPZ - RAM Page Z Select Register
.equ RAMPZ0 = 0 ; RAM Page Z Select Register Bit 0
.equ RAMPZ1 = 1 ; RAM Page Z Select Register Bit 1
; EIND - Extended Indirect Register
.equ EIND0 = 0 ; Bit 0
; GPIOR2 - General Purpose IO Register 2
.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0
.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1
.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2
.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3
.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4
.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5
.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6
.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7
; GPIOR1 - General Purpose IO Register 1
.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0
.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1
.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2
.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3
.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4
.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5
.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6
.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7
; GPIOR0 - General Purpose IO Register 0
.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0
.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1
.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2
.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3
.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4
.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5
.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6
.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7
; PRR1 - Power Reduction Register1
.equ PRUSART1 = 0 ; Power Reduction USART1
.equ PRUSART2 = 1 ; Power Reduction USART2
.equ PRUSART3 = 2 ; Power Reduction USART3
.equ PRTIM3 = 3 ; Power Reduction Timer/Counter3
.equ PRTIM4 = 4 ; Power Reduction Timer/Counter4
.equ PRTIM5 = 5 ; Power Reduction Timer/Counter5
; PRR0 - Power Reduction Register0
.equ PRADC = 0 ; Power Reduction ADC
.equ PRUSART0 = 1 ; Power Reduction USART
.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface
.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1
.equ PRTIM0 = 5 ; Power Reduction Timer/Counter0
.equ PRTIM2 = 6 ; Power Reduction Timer/Counter2
.equ PRTWI = 7 ; Power Reduction TWI
; ***** AD_CONVERTER *****************
; ADMUX - The ADC multiplexer Selection Register
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits
.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits
.equ ADLAR = 5 ; Left Adjust Result
.equ REFS0 = 6 ; Reference Selection Bit 0
.equ REFS1 = 7 ; Reference Selection Bit 1
; ADCSRA - The ADC Control and Status register A
.equ ADPS0 = 0 ; ADC Prescaler Select Bits
.equ ADPS1 = 1 ; ADC Prescaler Select Bits
.equ ADPS2 = 2 ; ADC Prescaler Select Bits
.equ ADIE = 3 ; ADC Interrupt Enable
.equ ADIF = 4 ; ADC Interrupt Flag
.equ ADATE = 5 ; ADC Auto Trigger Enable
.equ ADSC = 6 ; ADC Start Conversion
.equ ADEN = 7 ; ADC Enable
; ADCSRB - The ADC Control and Status register B
.equ ADTS0 = 0 ; ADC Auto Trigger Source bit 0
.equ ADTS1 = 1 ; ADC Auto Trigger Source bit 1
.equ ADTS2 = 2 ; ADC Auto Trigger Source bit 2
.equ MUX5 = 3 ; Analog Channel and Gain Selection Bits
;.equ ACME = 6 ;
; ADCH - ADC Data Register High Byte
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7
; ADCL - ADC Data Register Low Byte
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7
; DIDR0 - Digital Input Disable Register
.equ ADC0D = 0 ;
.equ ADC1D = 1 ;
.equ ADC2D = 2 ;
.equ ADC3D = 3 ;
.equ ADC4D = 4 ;
.equ ADC5D = 5 ;
.equ ADC6D = 6 ;
.equ ADC7D = 7 ;
; DIDR2 - Digital Input Disable Register
.equ ADC8D = 0 ;
.equ ADC9D = 1 ;
.equ ADC10D = 2 ;
.equ ADC11D = 3 ;
.equ ADC12D = 4 ;
.equ ADC13D = 5 ;
.equ ADC14D = 6 ;
.equ ADC15D = 7 ;
; ***** BOOT_LOAD ********************
; SPMCSR - Store Program Memory Control Register
.equ SPMEN = 0 ; Store Program Memory Enable
.equ PGERS = 1 ; Page Erase
.equ PGWRT = 2 ; Page Write
.equ BLBSET = 3 ; Boot Lock Bit Set
.equ RWWSRE = 4 ; Read While Write section read enable
.equ SIGRD = 5 ; Signature Row Read
.equ RWWSB = 6 ; Read While Write Section Busy
.equ SPMIE = 7 ; SPM Interrupt Enable
; ***** USART2 ***********************
; UDR2 - USART I/O Data Register
.equ UDR2_0 = 0 ; USART I/O Data Register bit 0
.equ UDR2_1 = 1 ; USART I/O Data Register bit 1
.equ UDR2_2 = 2 ; USART I/O Data Register bit 2
.equ UDR2_3 = 3 ; USART I/O Data Register bit 3
.equ UDR2_4 = 4 ; USART I/O Data Register bit 4
.equ UDR2_5 = 5 ; USART I/O Data Register bit 5
.equ UDR2_6 = 6 ; USART I/O Data Register bit 6
.equ UDR2_7 = 7 ; USART I/O Data Register bit 7
; UCSR2A - USART Control and Status Register A
.equ MPCM2 = 0 ; Multi-processor Communication Mode
.equ U2X2 = 1 ; Double the USART transmission speed
.equ UPE2 = 2 ; Parity Error
.equ DOR2 = 3 ; Data overRun
.equ FE2 = 4 ; Framing Error
.equ UDRE2 = 5 ; USART Data Register Empty
.equ TXC2 = 6 ; USART Transmitt Complete
.equ RXC2 = 7 ; USART Receive Complete
; UCSR2B - USART Control and Status Register B
.equ TXB82 = 0 ; Transmit Data Bit 8
.equ RXB82 = 1 ; Receive Data Bit 8
.equ UCSZ22 = 2 ; Character Size
.equ TXEN2 = 3 ; Transmitter Enable
.equ RXEN2 = 4 ; Receiver Enable
.equ UDRIE2 = 5 ; USART Data register Empty Interrupt Enable
.equ TXCIE2 = 6 ; TX Complete Interrupt Enable
.equ RXCIE2 = 7 ; RX Complete Interrupt Enable
; UCSR2C - USART Control and Status Register C
.equ UCPOL2 = 0 ; Clock Polarity
.equ UCSZ20 = 1 ; Character Size
.equ UCSZ21 = 2 ; Character Size
.equ USBS2 = 3 ; Stop Bit Select
.equ UPM20 = 4 ; Parity Mode Bit 0
.equ UPM21 = 5 ; Parity Mode Bit 1
.equ UMSEL20 = 6 ; USART Mode Select
.equ UMSEL21 = 7 ; USART Mode Select
; UBRR2H - USART Baud Rate Register High Byte
;.equ UBRR8 = 0 ; USART Baud Rate Register bit 8
;.equ UBRR9 = 1 ; USART Baud Rate Register bit 9
;.equ UBRR10 = 2 ; USART Baud Rate Register bit 10
;.equ UBRR11 = 3 ; USART Baud Rate Register bit 11
; UBRR2L - USART Baud Rate Register Low Byte
;.equ UBRR0 = 0 ; USART Baud Rate Register bit 0
;.equ UBRR1 = 1 ; USART Baud Rate Register bit 1
;.equ UBRR2 = 2 ; USART Baud Rate Register bit 2
;.equ UBRR3 = 3 ; USART Baud Rate Register bit 3
;.equ UBRR4 = 4 ; USART Baud Rate Register bit 4
;.equ UBRR5 = 5 ; USART Baud Rate Register bit 5
;.equ UBRR6 = 6 ; USART Baud Rate Register bit 6
;.equ UBRR7 = 7 ; USART Baud Rate Register bit 7
; ***** USART3 ***********************
; UDR3 - USART I/O Data Register
.equ UDR3_0 = 0 ; USART I/O Data Register bit 0
.equ UDR3_1 = 1 ; USART I/O Data Register bit 1
.equ UDR3_2 = 2 ; USART I/O Data Register bit 2
.equ UDR3_3 = 3 ; USART I/O Data Register bit 3
.equ UDR3_4 = 4 ; USART I/O Data Register bit 4
.equ UDR3_5 = 5 ; USART I/O Data Register bit 5
.equ UDR3_6 = 6 ; USART I/O Data Register bit 6
.equ UDR3_7 = 7 ; USART I/O Data Register bit 7
; UCSR3A - USART Control and Status Register A
.equ MPCM3 = 0 ; Multi-processor Communication Mode
.equ U2X3 = 1 ; Double the USART transmission speed
.equ UPE3 = 2 ; Parity Error
.equ DOR3 = 3 ; Data overRun
.equ FE3 = 4 ; Framing Error
.equ UDRE3 = 5 ; USART Data Register Empty
.equ TXC3 = 6 ; USART Transmitt Complete
.equ RXC3 = 7 ; USART Receive Complete
; UCSR3B - USART Control and Status Register B
.equ TXB83 = 0 ; Transmit Data Bit 8
.equ RXB83 = 1 ; Receive Data Bit 8
.equ UCSZ32 = 2 ; Character Size
.equ TXEN3 = 3 ; Transmitter Enable
.equ RXEN3 = 4 ; Receiver Enable
.equ UDRIE3 = 5 ; USART Data register Empty Interrupt Enable
.equ TXCIE3 = 6 ; TX Complete Interrupt Enable
.equ RXCIE3 = 7 ; RX Complete Interrupt Enable
; UCSR3C - USART Control and Status Register C
.equ UCPOL3 = 0 ; Clock Polarity
.equ UCSZ30 = 1 ; Character Size
.equ UCSZ31 = 2 ; Character Size
.equ USBS3 = 3 ; Stop Bit Select
.equ UPM30 = 4 ; Parity Mode Bit 0
.equ UPM31 = 5 ; Parity Mode Bit 1
.equ UMSEL30 = 6 ; USART Mode Select
.equ UMSEL31 = 7 ; USART Mode Select
; UBRR3H - USART Baud Rate Register High Byte
;.equ UBRR8 = 0 ; USART Baud Rate Register bit 8
;.equ UBRR9 = 1 ; USART Baud Rate Register bit 9
;.equ UBRR10 = 2 ; USART Baud Rate Register bit 10
;.equ UBRR11 = 3 ; USART Baud Rate Register bit 11
; UBRR3L - USART Baud Rate Register Low Byte
;.equ UBRR0 = 0 ; USART Baud Rate Register bit 0
;.equ UBRR1 = 1 ; USART Baud Rate Register bit 1
;.equ UBRR2 = 2 ; USART Baud Rate Register bit 2
;.equ UBRR3 = 3 ; USART Baud Rate Register bit 3
;.equ UBRR4 = 4 ; USART Baud Rate Register bit 4
;.equ UBRR5 = 5 ; USART Baud Rate Register bit 5
;.equ UBRR6 = 6 ; USART Baud Rate Register bit 6
;.equ UBRR7 = 7 ; USART Baud Rate Register bit 7
; ***** LOCKSBITS ********************************************************
.equ LB1 = 0 ; Lock bit
.equ LB2 = 1 ; Lock bit
.equ BLB01 = 2 ; Boot Lock bit
.equ BLB02 = 3 ; Boot Lock bit
.equ BLB11 = 4 ; Boot lock bit
.equ BLB12 = 5 ; Boot lock bit
; ***** FUSES ************************************************************
; LOW fuse bits
.equ CKSEL0 = 0 ; Select Clock Source
.equ CKSEL1 = 1 ; Select Clock Source
.equ CKSEL2 = 2 ; Select Clock Source
.equ CKSEL3 = 3 ; Select Clock Source
.equ SUT0 = 4 ; Select start-up time
.equ SUT1 = 5 ; Select start-up time
.equ CKOUT = 6 ; Clock output
.equ CKDIV8 = 7 ; Divide clock by 8
; HIGH fuse bits
.equ BOOTRST = 0 ; Select Reset Vector
.equ BOOTSZ0 = 1 ; Select Boot Size
.equ BOOTSZ1 = 2 ; Select Boot Size
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase
.equ WDTON = 4 ; Watchdog timer always on
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading
.equ JTAGEN = 6 ; Enable JTAG
.equ OCDEN = 7 ; Enable OCD
; EXTENDED fuse bits
.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level
.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level
.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level
; ***** CPU REGISTER DEFINITIONS *****************************************
.def XH = r27
.def XL = r26
.def YH = r29
.def YL = r28
.def ZH = r31
.def ZL = r30
; ***** DATA MEMORY DECLARATIONS *****************************************
.equ FLASHEND = 0x7fff ; Note: Word address
.equ IOEND = 0x01ff
.equ SRAM_START = 0x0200
.equ SRAM_SIZE = 8192
.equ RAMEND = 0x21ff
.equ XRAMEND = 0xffff
.equ E2END = 0x0fff
.equ EEPROMEND = 0x0fff
.equ EEADRBITS = 12
#pragma AVRPART MEMORY PROG_FLASH 65536
#pragma AVRPART MEMORY EEPROM 4096
#pragma AVRPART MEMORY INT_SRAM SIZE 8192
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x200
; ***** BOOTLOADER DECLARATIONS ******************************************
.equ NRWW_START_ADDR = 0x7000
.equ NRWW_STOP_ADDR = 0x7fff
.equ RWW_START_ADDR = 0x0
.equ RWW_STOP_ADDR = 0x6fff
.equ PAGESIZE = 128
.equ FIRSTBOOTSTART = 0x7e00
.equ SECONDBOOTSTART = 0x7c00
.equ THIRDBOOTSTART = 0x7800
.equ FOURTHBOOTSTART = 0x7000
.equ SMALLBOOTSTART = FIRSTBOOTSTART
.equ LARGEBOOTSTART = FOURTHBOOTSTART
; ***** INTERRUPT VECTORS ************************************************
.equ INT0addr = 0x0002 ; External Interrupt Request 0
.equ INT1addr = 0x0004 ; External Interrupt Request 1
.equ INT2addr = 0x0006 ; External Interrupt Request 2
.equ INT3addr = 0x0008 ; External Interrupt Request 3
.equ INT4addr = 0x000a ; External Interrupt Request 4
.equ INT5addr = 0x000c ; External Interrupt Request 5
.equ INT6addr = 0x000e ; External Interrupt Request 6
.equ INT7addr = 0x0010 ; External Interrupt Request 7
.equ PCI0addr = 0x0012 ; Pin Change Interrupt Request 0
.equ PCI1addr = 0x0014 ; Pin Change Interrupt Request 1
.equ PCI2addr = 0x0016 ; Pin Change⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -