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.equ DDH1 = 1 ; PORT H Data Direction Register bit 1
.equ DDH2 = 2 ; PORT H Data Direction Register bit 2
.equ DDH3 = 3 ; PORT H Data Direction Register bit 3
.equ DDH4 = 4 ; PORT H Data Direction Register bit 4
.equ DDH5 = 5 ; PORT H Data Direction Register bit 5
.equ DDH6 = 6 ; PORT H Data Direction Register bit 6
.equ DDH7 = 7 ; PORT H Data Direction Register bit 7
; PINH - PORT H Input Pins
.equ PINH0 = 0 ; PORT H Input Pins bit 0
.equ PINH1 = 1 ; PORT H Input Pins bit 1
.equ PINH2 = 2 ; PORT H Input Pins bit 2
.equ PINH3 = 3 ; PORT H Input Pins bit 3
.equ PINH4 = 4 ; PORT H Input Pins bit 4
.equ PINH5 = 5 ; PORT H Input Pins bit 5
.equ PINH6 = 6 ; PORT H Input Pins bit 6
.equ PINH7 = 7 ; PORT H Input Pins bit 7
; ***** PORTJ ************************
; PORTJ - PORT J Data Register
.equ PORTJ0 = 0 ; PORT J Data Register bit 0
.equ PJ0 = 0 ; For compatibility
.equ PORTJ1 = 1 ; PORT J Data Register bit 1
.equ PJ1 = 1 ; For compatibility
.equ PORTJ2 = 2 ; PORT J Data Register bit 2
.equ PJ2 = 2 ; For compatibility
.equ PORTJ3 = 3 ; PORT J Data Register bit 3
.equ PJ3 = 3 ; For compatibility
.equ PORTJ4 = 4 ; PORT J Data Register bit 4
.equ PJ4 = 4 ; For compatibility
.equ PORTJ5 = 5 ; PORT J Data Register bit 5
.equ PJ5 = 5 ; For compatibility
.equ PORTJ6 = 6 ; PORT J Data Register bit 6
.equ PJ6 = 6 ; For compatibility
.equ PORTJ7 = 7 ; PORT J Data Register bit 7
.equ PJ7 = 7 ; For compatibility
; DDRJ - PORT J Data Direction Register
.equ DDJ0 = 0 ; PORT J Data Direction Register bit 0
.equ DDJ1 = 1 ; PORT J Data Direction Register bit 1
.equ DDJ2 = 2 ; PORT J Data Direction Register bit 2
.equ DDJ3 = 3 ; PORT J Data Direction Register bit 3
.equ DDJ4 = 4 ; PORT J Data Direction Register bit 4
.equ DDJ5 = 5 ; PORT J Data Direction Register bit 5
.equ DDJ6 = 6 ; PORT J Data Direction Register bit 6
.equ DDJ7 = 7 ; PORT J Data Direction Register bit 7
; PINJ - PORT J Input Pins
.equ PINJ0 = 0 ; PORT J Input Pins bit 0
.equ PINJ1 = 1 ; PORT J Input Pins bit 1
.equ PINJ2 = 2 ; PORT J Input Pins bit 2
.equ PINJ3 = 3 ; PORT J Input Pins bit 3
.equ PINJ4 = 4 ; PORT J Input Pins bit 4
.equ PINJ5 = 5 ; PORT J Input Pins bit 5
.equ PINJ6 = 6 ; PORT J Input Pins bit 6
.equ PINJ7 = 7 ; PORT J Input Pins bit 7
; ***** PORTK ************************
; PORTK - PORT K Data Register
.equ PORTK0 = 0 ; PORT K Data Register bit 0
.equ PK0 = 0 ; For compatibility
.equ PORTK1 = 1 ; PORT K Data Register bit 1
.equ PK1 = 1 ; For compatibility
.equ PORTK2 = 2 ; PORT K Data Register bit 2
.equ PK2 = 2 ; For compatibility
.equ PORTK3 = 3 ; PORT K Data Register bit 3
.equ PK3 = 3 ; For compatibility
.equ PORTK4 = 4 ; PORT K Data Register bit 4
.equ PK4 = 4 ; For compatibility
.equ PORTK5 = 5 ; PORT K Data Register bit 5
.equ PK5 = 5 ; For compatibility
.equ PORTK6 = 6 ; PORT K Data Register bit 6
.equ PK6 = 6 ; For compatibility
.equ PORTK7 = 7 ; PORT K Data Register bit 7
.equ PK7 = 7 ; For compatibility
; DDRK - PORT K Data Direction Register
.equ DDK0 = 0 ; PORT K Data Direction Register bit 0
.equ DDK1 = 1 ; PORT K Data Direction Register bit 1
.equ DDK2 = 2 ; PORT K Data Direction Register bit 2
.equ DDK3 = 3 ; PORT K Data Direction Register bit 3
.equ DDK4 = 4 ; PORT K Data Direction Register bit 4
.equ DDK5 = 5 ; PORT K Data Direction Register bit 5
.equ DDK6 = 6 ; PORT K Data Direction Register bit 6
.equ DDK7 = 7 ; PORT K Data Direction Register bit 7
; PINK - PORT K Input Pins
.equ PINK0 = 0 ; PORT K Input Pins bit 0
.equ PINK1 = 1 ; PORT K Input Pins bit 1
.equ PINK2 = 2 ; PORT K Input Pins bit 2
.equ PINK3 = 3 ; PORT K Input Pins bit 3
.equ PINK4 = 4 ; PORT K Input Pins bit 4
.equ PINK5 = 5 ; PORT K Input Pins bit 5
.equ PINK6 = 6 ; PORT K Input Pins bit 6
.equ PINK7 = 7 ; PORT K Input Pins bit 7
; ***** PORTL ************************
; PORTL - PORT L Data Register
.equ PORTL0 = 0 ; PORT L Data Register bit 0
.equ PL0 = 0 ; For compatibility
.equ PORTL1 = 1 ; PORT L Data Register bit 1
.equ PL1 = 1 ; For compatibility
.equ PORTL2 = 2 ; PORT L Data Register bit 2
.equ PL2 = 2 ; For compatibility
.equ PORTL3 = 3 ; PORT L Data Register bit 3
.equ PL3 = 3 ; For compatibility
.equ PORTL4 = 4 ; PORT L Data Register bit 4
.equ PL4 = 4 ; For compatibility
.equ PORTL5 = 5 ; PORT L Data Register bit 5
.equ PL5 = 5 ; For compatibility
.equ PORTL6 = 6 ; PORT L Data Register bit 6
.equ PL6 = 6 ; For compatibility
.equ PORTL7 = 7 ; PORT L Data Register bit 7
.equ PL7 = 7 ; For compatibility
; DDRL - PORT L Data Direction Register
.equ DDL0 = 0 ; PORT L Data Direction Register bit 0
.equ DDL1 = 1 ; PORT L Data Direction Register bit 1
.equ DDL2 = 2 ; PORT L Data Direction Register bit 2
.equ DDL3 = 3 ; PORT L Data Direction Register bit 3
.equ DDL4 = 4 ; PORT L Data Direction Register bit 4
.equ DDL5 = 5 ; PORT L Data Direction Register bit 5
.equ DDL6 = 6 ; PORT L Data Direction Register bit 6
.equ DDL7 = 7 ; PORT L Data Direction Register bit 7
; PINL - PORT L Input Pins
.equ PINL0 = 0 ; PORT L Input Pins bit 0
.equ PINL1 = 1 ; PORT L Input Pins bit 1
.equ PINL2 = 2 ; PORT L Input Pins bit 2
.equ PINL3 = 3 ; PORT L Input Pins bit 3
.equ PINL4 = 4 ; PORT L Input Pins bit 4
.equ PINL5 = 5 ; PORT L Input Pins bit 5
.equ PINL6 = 6 ; PORT L Input Pins bit 6
.equ PINL7 = 7 ; PORT L Input Pins bit 7
; ***** TIMER_COUNTER_0 **************
; TIMSK0 - Timer/Counter0 Interrupt Mask Register
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable
.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable
; TIFR0 - Timer/Counter0 Interrupt Flag register
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0A
.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B
; TCCR0A - Timer/Counter Control Register A
.equ WGM00 = 0 ; Waveform Generation Mode
.equ WGM01 = 1 ; Waveform Generation Mode
.equ COM0B0 = 4 ; Compare Output Mode, Fast PWm
.equ COM0B1 = 5 ; Compare Output Mode, Fast PWm
.equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode
.equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode
; TCCR0B - Timer/Counter Control Register B
.equ CS00 = 0 ; Clock Select
.equ CS01 = 1 ; Clock Select
.equ CS02 = 2 ; Clock Select
.equ WGM02 = 3 ;
.equ FOC0B = 6 ; Force Output Compare B
.equ FOC0A = 7 ; Force Output Compare A
; TCNT0 - Timer/Counter0
.equ TCNT0_0 = 0 ;
.equ TCNT0_1 = 1 ;
.equ TCNT0_2 = 2 ;
.equ TCNT0_3 = 3 ;
.equ TCNT0_4 = 4 ;
.equ TCNT0_5 = 5 ;
.equ TCNT0_6 = 6 ;
.equ TCNT0_7 = 7 ;
; OCR0A - Timer/Counter0 Output Compare Register
.equ OCROA_0 = 0 ;
.equ OCROA_1 = 1 ;
.equ OCROA_2 = 2 ;
.equ OCROA_3 = 3 ;
.equ OCROA_4 = 4 ;
.equ OCROA_5 = 5 ;
.equ OCROA_6 = 6 ;
.equ OCROA_7 = 7 ;
; OCR0B - Timer/Counter0 Output Compare Register
.equ OCR0B_0 = 0 ;
.equ OCR0B_1 = 1 ;
.equ OCR0B_2 = 2 ;
.equ OCR0B_3 = 3 ;
.equ OCR0B_4 = 4 ;
.equ OCR0B_5 = 5 ;
.equ OCR0B_6 = 6 ;
.equ OCR0B_7 = 7 ;
; GTCCR - General Timer/Counter Control Register
.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0
.equ PSR10 = PSRSYNC ; For compatibility
.equ TSM = 7 ; Timer/Counter Synchronization Mode
; ***** TIMER_COUNTER_2 **************
; TIMSK2 - Timer/Counter Interrupt Mask register
.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable
.equ TOIE2A = TOIE2 ; For compatibility
.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match A Interrupt Enable
.equ OCIE2B = 2 ; Timer/Counter2 Output Compare Match B Interrupt Enable
; TIFR2 - Timer/Counter Interrupt Flag Register
.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag
.equ OCF2A = 1 ; Output Compare Flag 2A
.equ OCF2B = 2 ; Output Compare Flag 2B
; TCCR2A - Timer/Counter2 Control Register A
.equ WGM20 = 0 ; Waveform Genration Mode
.equ WGM21 = 1 ; Waveform Genration Mode
.equ COM2B0 = 4 ; Compare Output Mode bit 0
.equ COM2B1 = 5 ; Compare Output Mode bit 1
.equ COM2A0 = 6 ; Compare Output Mode bit 1
.equ COM2A1 = 7 ; Compare Output Mode bit 1
; TCCR2B - Timer/Counter2 Control Register B
.equ CS20 = 0 ; Clock Select bit 0
.equ CS21 = 1 ; Clock Select bit 1
.equ CS22 = 2 ; Clock Select bit 2
.equ WGM22 = 3 ; Waveform Generation Mode
.equ FOC2B = 6 ; Force Output Compare B
.equ FOC2A = 7 ; Force Output Compare A
; TCNT2 - Timer/Counter2
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7
; OCR2A - Timer/Counter2 Output Compare Register A
.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0
.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1
.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2
.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3
.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4
.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5
.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6
.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7
; OCR2B - Timer/Counter2 Output Compare Register B
;.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0
;.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1
;.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2
;.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3
;.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4
;.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5
;.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6
;.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7
; ASSR - Asynchronous Status Register
.equ TCR2BUB = 0 ; Timer/Counter Control Register2 Update Busy
.equ TCR2AUB = 1 ; Timer/Counter Control Register2 Update Busy
.equ OCR2BUB = 2 ; Output Compare Register 2 Update Busy
.equ OCR2AUB = 3 ; Output Compare Register2 Update Busy
.equ TCN2UB = 4 ; Timer/Counter2 Update Busy
.equ AS2 = 5 ; Asynchronous Timer/Counter2
.equ EXCLK = 6 ; Enable External Clock Input
; GTCCR - General Timer Counter Control register
.equ PSRASY = 1 ; Prescaler Reset Timer/Counter2
.equ PSR2 = PSRASY ; For compatibility
;.equ TSM = 7 ; Timer/Counter Synchronization Mode
; ***** WATCHDOG *********************
; WDTCSR - Watchdog Timer Control Register
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
.equ WDE = 3 ; Watch Dog Enable
.equ WDCE = 4 ; Watchdog Change Enable
.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3
.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable
.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag
; ***** USART1 ***********************
; UDR1 - USART I/O Data Register
.equ UDR1_0 = 0 ; USART I/O Data Register bit 0
.equ UDR1_1 = 1 ; USART I/O Data Register bit 1
.equ UDR1_2 = 2 ; USART I/O Data Register bit 2
.equ UDR1_3 = 3 ; USART I/O Data Register bit 3
.equ UDR1_4 = 4 ; USART I/O Data Register bit 4
.equ UDR1_5 = 5 ; USART I/O Data Register bit 5
.equ UDR1_6 = 6 ; USART I/O Data Register bit 6
.equ UDR1_7 = 7 ; USART I/O Data Register bit 7
; UCSR1A - USART Control and Status Register A
.equ MPCM1 = 0 ; Multi-processor Communication Mode
.equ U2X1 = 1 ; Double the USART transmission speed
.equ UPE1 = 2 ; Parity Error
.equ DOR1 = 3 ; Data overRun
.equ FE1 = 4 ; Framing Error
.equ UDRE1 = 5 ; USART Data Register Empty
.equ TXC1 = 6 ; USART Transmitt Complete
.equ RXC1 = 7 ; USART Receive Complete
; UCSR1B - USART Control and Status Register B
.equ TXB81 = 0 ; Transmit Data Bit 8
.equ RXB81 = 1 ; Receive Data Bit 8
.equ UCSZ12 = 2 ; Character Size
.equ TXEN1 = 3 ; Transmitter Enable
.equ RXEN1 = 4 ; Receiver Enable
.equ UDRIE1 = 5 ; USART Data register Empty Interrupt Enable
.equ TXCIE1 = 6 ; TX Complete Interrupt Enable
.equ RXCIE1 = 7 ; RX Complete Interrupt Enable
; UCSR1C - USART Control and Status Register C
.equ UCPOL1 = 0 ; Clock Polarity
.equ UCSZ10 = 1 ; Character Size
.equ UCPHA1 = UCSZ10 ; For compatibility
.equ UCSZ11 = 2 ; Character Size
.equ UDORD1 = UCSZ11 ; For compatibility
.equ USBS1 = 3 ; Stop Bit Select
.equ UPM10 = 4 ; Parity Mode Bit 0
.equ UPM11 = 5 ; Parity Mode Bit 1
.equ UMSEL10 = 6 ; USART Mode Select
.equ UMSEL11 = 7 ; USART Mode Select
; UBRR1H - USART Baud Rate Register High Byte
;.equ UBRR8 = 0 ; USART Baud Rate Register bit 8
;.equ UBRR9 = 1 ; USART Baud Rate Register bit 9
;.equ UBRR10 = 2 ; USART Baud Rate Register bit 10
;.equ UBRR11 = 3 ; USART Baud Rate Register bit 11
; UBRR1L - USART Baud Rate Register Low Byte
;.equ UBRR0 = 0 ; USART Baud Rate Register bit 0
;.equ UBRR1 = 1 ; USART Baud Rate Register bit 1
;.equ UBRR2 = 2 ; USART Baud Rate Register bit 2
;.equ UBRR3 = 3 ; USART Baud Rate Register bit 3
;.equ UBRR4 = 4 ; USART Baud Rate Register bit 4
;.equ UBRR5 = 5 ; USART Baud Rate Register bit 5
;.equ UBRR6 = 6 ; USART Baud Rate Register bit 6
;.equ UBRR7 = 7 ; USART Baud Rate Register bit 7
; ***** EEPROM ***********************
; EEARH - EEPROM Address Register Low Byte
.equ EEAR8 = 0 ; EEPROM Read/Write Access Bit 8
.equ EEAR9 = 1 ; EEPROM Read/Write Access Bit 9
.equ EEAR10 = 2 ; EEPROM Read/Write Access Bit 10
.equ EEAR11 = 3 ; EEPROM Read/Write Access Bit 11
; EEARL - EEPROM Address Register Low Byte
.equ EEAR0 = 0 ; EEPROM Read/Write Access Bit 0
.equ EEAR1 = 1 ; EEPROM Read/Write Access Bit 1
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