pwm2bdef.inc

AVR Assembler 2 compiler

;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
;***** Created: 2007-12-13 07:27 ******* Source: AT90PWM2B.xml ***********
;*************************************************************************
;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
;* 
;* Number            : AVR000
;* File Name         : "pwm2Bdef.inc"
;* Title             : Register/Bit Definitions for the AT90PWM2B
;* Date              : 2007-12-13
;* Version           : 2.24
;* Support E-mail    : [e-mail]
;* Target MCU        : AT90PWM2B
;* 
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register 
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and 
;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
;* SRAM is also defined 
;* 
;* The Register names are represented by their hexadecimal address.
;* 
;* The Register Bit names are represented by their bit number (0-7).
;* 
;* Please observe the difference in using the bit names with instructions
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
;* (skip if bit in register set/cleared). The following example illustrates
;* this:
;* 
;* in    r16,PORTB             ;read PORTB latch
;* sbr   r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
;* out   PORTB,r16             ;output to PORTB
;* 
;* in    r16,TIFR              ;read the Timer Interrupt Flag Register
;* sbrc  r16,TOV0              ;test the overflow flag (use bit#)
;* rjmp  TOV0_is_set           ;jump if set
;* ...                         ;otherwise do something else
;*************************************************************************

#ifndef _PWM2BDEF_INC_
#define _PWM2BDEF_INC_


#pragma partinc 0

; ***** SPECIFY DEVICE ***************************************************
.device AT90PWM2B
#pragma AVRPART ADMIN PART_NAME AT90PWM2B
.equ	SIGNATURE_000	= 0x1e
.equ	SIGNATURE_001	= 0x93
.equ	SIGNATURE_002	= 0x83

#pragma AVRPART CORE CORE_VERSION V2E


; ***** I/O REGISTER DEFINITIONS *****************************************
; NOTE:
; Definitions marked "MEMORY MAPPED"are extended I/O ports
; and cannot be used with IN/OUT instructions
.equ	PICR2H	= 0xff	; MEMORY MAPPED
.equ	PICR2L	= 0xfe	; MEMORY MAPPED
.equ	PFRC2B	= 0xfd	; MEMORY MAPPED
.equ	PFRC2A	= 0xfc	; MEMORY MAPPED
.equ	PCTL2	= 0xfb	; MEMORY MAPPED
.equ	PCNF2	= 0xfa	; MEMORY MAPPED
.equ	OCR2RBH	= 0xf9	; MEMORY MAPPED
.equ	OCR2RBL	= 0xf8	; MEMORY MAPPED
.equ	OCR2SBH	= 0xf7	; MEMORY MAPPED
.equ	OCR2SBL	= 0xf6	; MEMORY MAPPED
.equ	OCR2RAH	= 0xf5	; MEMORY MAPPED
.equ	OCR2RAL	= 0xf4	; MEMORY MAPPED
.equ	OCR2SAH	= 0xf3	; MEMORY MAPPED
.equ	OCR2SAL	= 0xf2	; MEMORY MAPPED
.equ	POM2	= 0xf1	; MEMORY MAPPED
.equ	PSOC2	= 0xf0	; MEMORY MAPPED
.equ	PICR0H	= 0xdf	; MEMORY MAPPED
.equ	PICR0L	= 0xde	; MEMORY MAPPED
.equ	PFRC0B	= 0xdd	; MEMORY MAPPED
.equ	PFRC0A	= 0xdc	; MEMORY MAPPED
.equ	PCTL0	= 0xdb	; MEMORY MAPPED
.equ	PCNF0	= 0xda	; MEMORY MAPPED
.equ	OCR0RBH	= 0xd9	; MEMORY MAPPED
.equ	OCR0RBL	= 0xd8	; MEMORY MAPPED
.equ	OCR0SBH	= 0xd7	; MEMORY MAPPED
.equ	OCR0SBL	= 0xd6	; MEMORY MAPPED
.equ	OCR0RAH	= 0xd5	; MEMORY MAPPED
.equ	OCR0RAL	= 0xd4	; MEMORY MAPPED
.equ	OCR0SAH	= 0xd3	; MEMORY MAPPED
.equ	OCR0SAL	= 0xd2	; MEMORY MAPPED
.equ	PSOC0	= 0xd0	; MEMORY MAPPED
.equ	EUDR	= 0xce	; MEMORY MAPPED
.equ	MUBRRL	= 0xcc	; MEMORY MAPPED
.equ	MUBRRH	= 0xcd	; MEMORY MAPPED
.equ	EUCSRC	= 0xca	; MEMORY MAPPED
.equ	EUCSRB	= 0xc9	; MEMORY MAPPED
.equ	EUCSRA	= 0xc8	; MEMORY MAPPED
.equ	UDR	= 0xc6	; MEMORY MAPPED
.equ	UBRRH	= 0xc5	; MEMORY MAPPED
.equ	UBRRL	= 0xc4	; MEMORY MAPPED
.equ	UCSRC	= 0xc2	; MEMORY MAPPED
.equ	UCSRB	= 0xc1	; MEMORY MAPPED
.equ	UCSRA	= 0xc0	; MEMORY MAPPED
.equ	AC2CON	= 0xaf	; MEMORY MAPPED
.equ	AC1CON	= 0xae	; MEMORY MAPPED
.equ	AC0CON	= 0xad	; MEMORY MAPPED
.equ	DACH	= 0xac	; MEMORY MAPPED
.equ	DACL	= 0xab	; MEMORY MAPPED
.equ	DACON	= 0xaa	; MEMORY MAPPED
.equ	PIM2	= 0xa5	; MEMORY MAPPED
.equ	PIFR2	= 0xa4	; MEMORY MAPPED
.equ	PIM1	= 0xa3	; MEMORY MAPPED
.equ	PIFR1	= 0xa2	; MEMORY MAPPED
.equ	PIM0	= 0xa1	; MEMORY MAPPED
.equ	PIFR0	= 0xa0	; MEMORY MAPPED
.equ	OCR1BL	= 0x8a	; MEMORY MAPPED
.equ	OCR1BH	= 0x8b	; MEMORY MAPPED
.equ	OCR1AL	= 0x88	; MEMORY MAPPED
.equ	OCR1AH	= 0x89	; MEMORY MAPPED
.equ	ICR1L	= 0x86	; MEMORY MAPPED
.equ	ICR1H	= 0x87	; MEMORY MAPPED
.equ	TCNT1L	= 0x84	; MEMORY MAPPED
.equ	TCNT1H	= 0x85	; MEMORY MAPPED
.equ	TCCR1C	= 0x82	; MEMORY MAPPED
.equ	TCCR1B	= 0x81	; MEMORY MAPPED
.equ	TCCR1A	= 0x80	; MEMORY MAPPED
.equ	DIDR1	= 0x7f	; MEMORY MAPPED
.equ	DIDR0	= 0x7e	; MEMORY MAPPED
.equ	ADMUX	= 0x7c	; MEMORY MAPPED
.equ	ADCSRB	= 0x7b	; MEMORY MAPPED
.equ	ADCSRA	= 0x7a	; MEMORY MAPPED
.equ	ADCH	= 0x79	; MEMORY MAPPED
.equ	ADCL	= 0x78	; MEMORY MAPPED
.equ	AMP1CSR	= 0x77	; MEMORY MAPPED
.equ	AMP0CSR	= 0x76	; MEMORY MAPPED
.equ	TIMSK1	= 0x6f	; MEMORY MAPPED
.equ	TIMSK0	= 0x6e	; MEMORY MAPPED
.equ	EICRA	= 0x69	; MEMORY MAPPED
.equ	OSCCAL	= 0x66	; MEMORY MAPPED
.equ	PRR	= 0x64	; MEMORY MAPPED
.equ	CLKPR	= 0x61	; MEMORY MAPPED
.equ	WDTCSR	= 0x60	; MEMORY MAPPED
.equ	SREG	= 0x3f
.equ	SPL	= 0x3d
.equ	SPH	= 0x3e
.equ	SPMCSR	= 0x37
.equ	MCUCR	= 0x35
.equ	MCUSR	= 0x34
.equ	SMCR	= 0x33
.equ	ACSR	= 0x30
.equ	SPDR	= 0x2e
.equ	SPSR	= 0x2d
.equ	SPCR	= 0x2c
.equ	PLLCSR	= 0x29
.equ	OCR0B	= 0x28
.equ	OCR0A	= 0x27
.equ	TCNT0	= 0x26
.equ	TCCR0B	= 0x25
.equ	TCCR0A	= 0x24
.equ	GTCCR	= 0x23
.equ	EEARL	= 0x21
.equ	EEARH	= 0x22
.equ	EEDR	= 0x20
.equ	EECR	= 0x1f
.equ	GPIOR0	= 0x1e
.equ	EIMSK	= 0x1d
.equ	EIFR	= 0x1c
.equ	GPIOR3	= 0x1b
.equ	GPIOR2	= 0x1a
.equ	GPIOR1	= 0x19
.equ	TIFR1	= 0x16
.equ	TIFR0	= 0x15
.equ	PORTE	= 0x0e
.equ	DDRE	= 0x0d
.equ	PINE	= 0x0c
.equ	PORTD	= 0x0b
.equ	DDRD	= 0x0a
.equ	PIND	= 0x09
.equ	PORTC	= 0x08
.equ	DDRC	= 0x07
.equ	PINC	= 0x06
.equ	PORTB	= 0x05
.equ	DDRB	= 0x04
.equ	PINB	= 0x03


; ***** BIT DEFINITIONS **************************************************

; ***** PORTB ************************
; PORTB - Port B Data Register
.equ	PORTB0	= 0	; Port B Data Register bit 0
.equ	PB0	= 0	; For compatibility
.equ	PORTB1	= 1	; Port B Data Register bit 1
.equ	PB1	= 1	; For compatibility
.equ	PORTB2	= 2	; Port B Data Register bit 2
.equ	PB2	= 2	; For compatibility
.equ	PORTB3	= 3	; Port B Data Register bit 3
.equ	PB3	= 3	; For compatibility
.equ	PORTB4	= 4	; Port B Data Register bit 4
.equ	PB4	= 4	; For compatibility
.equ	PORTB5	= 5	; Port B Data Register bit 5
.equ	PB5	= 5	; For compatibility
.equ	PORTB6	= 6	; Port B Data Register bit 6
.equ	PB6	= 6	; For compatibility
.equ	PORTB7	= 7	; Port B Data Register bit 7
.equ	PB7	= 7	; For compatibility

; DDRB - Port B Data Direction Register
.equ	DDB0	= 0	; Port B Data Direction Register bit 0
.equ	DDB1	= 1	; Port B Data Direction Register bit 1
.equ	DDB2	= 2	; Port B Data Direction Register bit 2
.equ	DDB3	= 3	; Port B Data Direction Register bit 3
.equ	DDB4	= 4	; Port B Data Direction Register bit 4
.equ	DDB5	= 5	; Port B Data Direction Register bit 5
.equ	DDB6	= 6	; Port B Data Direction Register bit 6
.equ	DDB7	= 7	; Port B Data Direction Register bit 7

; PINB - Port B Input Pins
.equ	PINB0	= 0	; Port B Input Pins bit 0
.equ	PINB1	= 1	; Port B Input Pins bit 1
.equ	PINB2	= 2	; Port B Input Pins bit 2
.equ	PINB3	= 3	; Port B Input Pins bit 3
.equ	PINB4	= 4	; Port B Input Pins bit 4
.equ	PINB5	= 5	; Port B Input Pins bit 5
.equ	PINB6	= 6	; Port B Input Pins bit 6
.equ	PINB7	= 7	; Port B Input Pins bit 7


; ***** PORTD ************************
; PORTD - Port D Data Register
.equ	PORTD0	= 0	; Port D Data Register bit 0
.equ	PD0	= 0	; For compatibility
.equ	PORTD1	= 1	; Port D Data Register bit 1
.equ	PD1	= 1	; For compatibility
.equ	PORTD2	= 2	; Port D Data Register bit 2
.equ	PD2	= 2	; For compatibility
.equ	PORTD3	= 3	; Port D Data Register bit 3
.equ	PD3	= 3	; For compatibility
.equ	PORTD4	= 4	; Port D Data Register bit 4
.equ	PD4	= 4	; For compatibility
.equ	PORTD5	= 5	; Port D Data Register bit 5
.equ	PD5	= 5	; For compatibility
.equ	PORTD6	= 6	; Port D Data Register bit 6
.equ	PD6	= 6	; For compatibility
.equ	PORTD7	= 7	; Port D Data Register bit 7
.equ	PD7	= 7	; For compatibility

; DDRD - Port D Data Direction Register
.equ	DDD0	= 0	; Port D Data Direction Register bit 0
.equ	DDD1	= 1	; Port D Data Direction Register bit 1
.equ	DDD2	= 2	; Port D Data Direction Register bit 2
.equ	DDD3	= 3	; Port D Data Direction Register bit 3
.equ	DDD4	= 4	; Port D Data Direction Register bit 4
.equ	DDD5	= 5	; Port D Data Direction Register bit 5
.equ	DDD6	= 6	; Port D Data Direction Register bit 6
.equ	DDD7	= 7	; Port D Data Direction Register bit 7

; PIND - Port D Input Pins
.equ	PIND0	= 0	; Port D Input Pins bit 0
.equ	PIND1	= 1	; Port D Input Pins bit 1
.equ	PIND2	= 2	; Port D Input Pins bit 2
.equ	PIND3	= 3	; Port D Input Pins bit 3
.equ	PIND4	= 4	; Port D Input Pins bit 4
.equ	PIND5	= 5	; Port D Input Pins bit 5
.equ	PIND6	= 6	; Port D Input Pins bit 6
.equ	PIND7	= 7	; Port D Input Pins bit 7


; ***** BOOT_LOAD ********************
; SPMCSR - Store Program Memory Control Register
.equ	SPMCR	= SPMCSR	; For compatibility
.equ	SPMEN	= 0	; Store Program Memory Enable
.equ	PGERS	= 1	; Page Erase
.equ	PGWRT	= 2	; Page Write
.equ	BLBSET	= 3	; Boot Lock Bit Set
.equ	RWWSRE	= 4	; Read While Write section read enable
.equ	ASRE	= RWWSRE	; For compatibility
.equ	RWWSB	= 6	; Read While Write Section Busy
.equ	ASB	= RWWSB	; For compatibility
.equ	SPMIE	= 7	; SPM Interrupt Enable


; ***** EUSART ***********************
; EUDR - EUSART I/O Data Register
.equ	EUDR0	= 0	; EUSART I/O Data Register bit 0
.equ	EUDR1	= 1	; EUSART I/O Data Register bit 1
.equ	EUDR2	= 2	; EUSART I/O Data Register bit 2
.equ	EUDR3	= 3	; EUSART I/O Data Register bit 3
.equ	EUDR4	= 4	; EUSART I/O Data Register bit 4
.equ	EUDR5	= 5	; EUSART I/O Data Register bit 5
.equ	EUDR6	= 6	; EUSART I/O Data Register bit 6
.equ	EUDR7	= 7	; EUSART I/O Data Register bit 7

; EUCSRA - EUSART Control and Status Register A
.equ	URxS0	= 0	; EUSART Control and Status Register A Bit 0
.equ	URxS1	= 1	; EUSART Control and Status Register A Bit 1
.equ	URxS2	= 2	; EUSART Control and Status Register A Bit 2
.equ	URxS3	= 3	; EUSART Control and Status Register A Bit 3
.equ	UTxS0	= 4	; EUSART Control and Status Register A Bit 4
.equ	UTxS1	= 5	; EUSART Control and Status Register A Bit 5
.equ	UTxS2	= 6	; EUSART Control and Status Register A Bit 6
.equ	UTxS3	= 7	; EUSART Control and Status Register A Bit 7

; EUCSRB - EUSART Control Register B
.equ	BODR	= 0	; Order Bit
.equ	EMCH	= 1	; Manchester Mode Bit
.equ	EUSBS	= 3	; EUSBS Enable Bit
.equ	EUSART	= 4	; EUSART Enable Bit

; EUCSRC - EUSART Status Register C
.equ	STP0	= 0	; Stop Bit 0
.equ	STP1	= 1	; Stop Bit 1
.equ	F1617	= 2	; F1617 Bit
.equ	FEM	= 3	; Frame Error Manchester Bit

; MUBRRH - Manchester Receiver Baud Rate Register High Byte
.equ	MUBRR8	= 0	; Manchester Receiver Baud Rate Register Bit 8
.equ	MUBRR9	= 1	; Manchester Receiver Baud Rate Register Bit 9
.equ	MUBRR10	= 2	; Manchester Receiver Baud Rate Register Bit 10
.equ	MUBRR11	= 3	; Manchester Receiver Baud Rate Register Bit 11
.equ	MUBRR12	= 4	; Manchester Receiver Baud Rate Register Bit 12
.equ	MUBRR13	= 5	; Manchester Receiver Baud Rate Register Bit 13
.equ	MUBRR14	= 6	; Manchester Receiver Baud Rate Register Bit 14
.equ	MUBRR15	= 7	; Manchester Receiver Baud Rate Register Bit 15

; MUBRRL - Manchester Receiver Baud Rate Register Low Byte
.equ	MUBRR0	= 0	; Manchester Receiver Baud Rate Register Bit 0
.equ	MUBRR1	= 1	; Manchester Receiver Baud Rate Register Bit 1
.equ	MUBRR2	= 2	; Manchester Receiver Baud Rate Register Bit 2
.equ	MUBRR3	= 3	; Manchester Receiver Baud Rate Register Bit 3
.equ	MUBRR4	= 4	; Manchester Receiver Baud Rate Register Bit 4
.equ	MUBRR5	= 5	; Manchester Receiver Baud Rate Register Bit 5
.equ	MUBRR6	= 6	; Manchester Receiver Baud Rate Register Bit 6
.equ	MUBRR7	= 7	; Manchester Receiver Baud Rate Register Bit 7


; ***** ANALOG_COMPARATOR ************
; AC0CON - Analog Comparator 0 Control Register
.equ	AC0M0	= 0	; Analog Comparator 0 Multiplexer Register
.equ	AC0M1	= 1	; Analog Comparator 0 Multiplexer Regsiter
.equ	AC0M2	= 2	; Analog Comparator 0 Multiplexer Register
.equ	AC0IS0	= 4	; Analog Comparator 0 Interrupt Select Bit
.equ	AC0IS1	= 5	; Analog Comparator 0  Interrupt Select Bit
.equ	AC0IE	= 6	; Analog Comparator 0 Interrupt Enable Bit
.equ	AC0EN	= 7	; Analog Comparator 0 Enable Bit

; AC1CON - Analog Comparator 1 Control Register
.equ	AC1M0	= 0	; Analog Comparator 1 Multiplexer Register
.equ	AC1M1	= 1	; Analog Comparator 1 Multiplexer Regsiter
.equ	AC1M2	= 2	; Analog Comparator 1 Multiplexer Register
.equ	AC1ICE	= 3	; Analog Comparator 1 Interrupt Capture Enable Bit
.equ	AC1IS0	= 4	; Analog Comparator 1 Interrupt Select Bit
.equ	AC1IS1	= 5	; Analog Comparator 1  Interrupt Select Bit
.equ	AC1IE	= 6	; Analog Comparator 1 Interrupt Enable Bit
.equ	AC1EN	= 7	; Analog Comparator 1 Enable Bit

; AC2CON - Analog Comparator 2 Control Register
.equ	AC2M0	= 0	; Analog Comparator 2 Multiplexer Register
.equ	AC2M1	= 1	; Analog Comparator 2 Multiplexer Regsiter
.equ	AC2M2	= 2	; Analog Comparator 2 Multiplexer Register
.equ	AC2IS0	= 4	; Analog Comparator 2 Interrupt Select Bit
.equ	AC2IS1	= 5	; Analog Comparator 2  Interrupt Select Bit
.equ	AC2IE	= 6	; Analog Comparator 2 Interrupt Enable Bit
.equ	AC2EN	= 7	; Analog Comparator 2 Enable Bit

; ACSR - Analog Comparator Status Register
.equ	AC0O	= 0	; Analog Comparator 0 Output Bit
.equ	AC1O	= 1	; Analog Comparator 1 Output Bit
.equ	AC2O	= 2	; Analog Comparator 2 Output Bit
.equ	AC0IF	= 4	; Analog Comparator 0 Interrupt Flag Bit
.equ	AC1IF	= 5	; Analog Comparator 1  Interrupt Flag Bit
.equ	AC2IF	= 6	; Analog Comparator 2 Interrupt Flag Bit
.equ	ACCKDIV	= 7	; Analog Comparator Clock Divider


; ***** DA_CONVERTER *****************
; DACH - DAC Data Register High Byte
.equ	DACH0	= 0	; DAC Data Register High Byte Bit 0
.equ	DACH1	= 1	; DAC Data Register High Byte Bit 1
.equ	DACH2	= 2	; DAC Data Register High Byte Bit 2
.equ	DACH3	= 3	; DAC Data Register High Byte Bit 3
.equ	DACH4	= 4	; DAC Data Register High Byte Bit 4
.equ	DACH5	= 5	; DAC Data Register High Byte Bit 5
.equ	DACH6	= 6	; DAC Data Register High Byte Bit 6
.equ	DACH7	= 7	; DAC Data Register High Byte Bit 7

; DACL - DAC Data Register Low Byte
.equ	DACL0	= 0	; DAC Data Register Low Byte Bit 0
.equ	DACL1	= 1	; DAC Data Register Low Byte Bit 1
.equ	DACL2	= 2	; DAC Data Register Low Byte Bit 2
.equ	DACL3	= 3	; DAC Data Register Low Byte Bit 3
.equ	DACL4	= 4	; DAC Data Register Low Byte Bit 4
.equ	DACL5	= 5	; DAC Data Register Low Byte Bit 5
.equ	DACL6	= 6	; DAC Data Register Low Byte Bit 6
.equ	DACL7	= 7	; DAC Data Register Low Byte Bit 7

; DACON - DAC Control Register
.equ	DAEN	= 0	; DAC Enable Bit
.equ	DAOE	= 1	; DAC Output Enable Bit
.equ	DALA	= 2	; DAC Left Adjust
.equ	DATS0	= 4	; DAC Trigger Selection Bit 0
.equ	DATS1	= 5	; DAC Trigger Selection Bit 1
.equ	DATS2	= 6	; DAC Trigger Selection Bit 2
.equ	DAATE	= 7	; DAC Auto Trigger Enable Bit


; ***** CPU **************************
; SREG - Status Register
.equ	SREG_C	= 0	; Carry Flag
.equ	SREG_Z	= 1	; Zero Flag
.equ	SREG_N	= 2	; Negative Flag
.equ	SREG_V	= 3	; Two's Complement Overflow Flag
.equ	SREG_S	= 4	; Sign Bit
.equ	SREG_H	= 5	; Half Carry Flag
.equ	SREG_T	= 6	; Bit Copy Storage
.equ	SREG_I	= 7	; Global Interrupt Enable

; MCUCR - MCU Control Register
.equ	IVCE	= 0	; Interrupt Vector Change Enable
.equ	IVSEL	= 1	; Interrupt Vector Select
.equ	PUD	= 4	; Pull-up disable
.equ	SPIPS	= 7	; SPI Pin Select

; MCUSR - MCU Status Register
.equ	PORF	= 0	; Power-on reset flag
.equ	EXTRF	= 1	; External Reset Flag
.equ	BORF	= 2	; Brown-out Reset Flag
.equ	WDRF	= 3	; Watchdog Reset Flag