pwm316def.inc

AVR Assembler 2 compiler

.equ	ADC10D	= 2	; 
.equ	AMP0ND	= 3	; 
.equ	AMP0PD	= 4	; 
.equ	ACMP0D	= 5	; 

; AMP0CSR - 
.equ	AMP0TS0	= 0	; 
.equ	AMP0TS1	= 1	; 
.equ	AMP0G0	= 4	; 
.equ	AMP0G1	= 5	; 
.equ	AMP0IS	= 6	; 
.equ	AMP0EN	= 7	; 

; AMP1CSR - 
.equ	AMP1TS0	= 0	; 
.equ	AMP1TS1	= 1	; 
.equ	AMP1G0	= 4	; 
.equ	AMP1G1	= 5	; 
.equ	AMP1IS	= 6	; 
.equ	AMP1EN	= 7	; 


; ***** USART ************************
; UDR - USART I/O Data Register
.equ	UDR0	= 0	; USART I/O Data Register bit 0
.equ	UDR1	= 1	; USART I/O Data Register bit 1
.equ	UDR2	= 2	; USART I/O Data Register bit 2
.equ	UDR3	= 3	; USART I/O Data Register bit 3
.equ	UDR4	= 4	; USART I/O Data Register bit 4
.equ	UDR5	= 5	; USART I/O Data Register bit 5
.equ	UDR6	= 6	; USART I/O Data Register bit 6
.equ	UDR7	= 7	; USART I/O Data Register bit 7

; UCSRA - USART Control and Status register A
.equ	MPCM	= 0	; Multi-processor Communication Mode
.equ	U2X	= 1	; Double USART Transmission Bit
.equ	UPE	= 2	; USART Parity Error
.equ	DOR	= 3	; Data Overrun
.equ	FE	= 4	; Framing Error
.equ	UDRE	= 5	; USART Data Register Empty
.equ	TXC	= 6	; USART Transmitt Complete
.equ	RXC	= 7	; USART Receive Complete

; UCSRB - USART Control an Status register B
.equ	TXB8	= 0	; Transmit Data Bit 8
.equ	RXB8	= 1	; Receive Data Bit 8
.equ	UCSZ2	= 2	; Character Size
.equ	TXEN	= 3	; Transmitter Enable
.equ	RXEN	= 4	; Receiver Enable
.equ	UDRIE	= 5	; USART Data Register Empty Interrupt Enable
.equ	TXCIE	= 6	; TX Complete Interrupt Enable
.equ	RXCIE	= 7	; RX Complete Interrupt Enable

; UCSRC - USART Control an Status register C
.equ	UCPOL	= 0	; Clock Polarity
.equ	UCSZ0	= 1	; Character Size Bit 0
.equ	UCSZ1	= 2	; Character Size Bit 1
.equ	USBS	= 3	; Stop Bit Select
.equ	UPM0	= 4	; Parity Mode Bit 0
.equ	UPM1	= 5	; Parity Mode Bit 1
.equ	UMSEL0	= 6	; USART Mode Select

; UBRRH - USART Baud Rate Register High Byte
.equ	UBRR8	= 0	; USART Baud Rate Register Bit 8
.equ	UBRR9	= 1	; USART Baud Rate Register Bit 9
.equ	UBRR10	= 2	; USART Baud Rate Register Bit 10
.equ	UBRR11	= 3	; USART Baud Rate Register Bit 11

; UBRRL - USART Baud Rate Register Low Byte
.equ	UBRR0	= 0	; USART Baud Rate Register bit 0
.equ	UBRR1	= 1	; USART Baud Rate Register bit 1
.equ	UBRR2	= 2	; USART Baud Rate Register bit 2
.equ	UBRR3	= 3	; USART Baud Rate Register bit 3
.equ	UBRR4	= 4	; USART Baud Rate Register bit 4
.equ	UBRR5	= 5	; USART Baud Rate Register bit 5
.equ	UBRR6	= 6	; USART Baud Rate Register bit 6
.equ	UBRR7	= 7	; USART Baud Rate Register bit 7


; ***** SPI **************************
; SPDR - SPI Data Register
.equ	SPDR0	= 0	; SPI Data Register bit 0
.equ	SPDR1	= 1	; SPI Data Register bit 1
.equ	SPDR2	= 2	; SPI Data Register bit 2
.equ	SPDR3	= 3	; SPI Data Register bit 3
.equ	SPDR4	= 4	; SPI Data Register bit 4
.equ	SPDR5	= 5	; SPI Data Register bit 5
.equ	SPDR6	= 6	; SPI Data Register bit 6
.equ	SPDR7	= 7	; SPI Data Register bit 7

; SPSR - SPI Status Register
.equ	SPI2X	= 0	; Double SPI Speed Bit
.equ	WCOL	= 6	; Write Collision Flag
.equ	SPIF	= 7	; SPI Interrupt Flag

; SPCR - SPI Control Register
.equ	SPR0	= 0	; SPI Clock Rate Select 0
.equ	SPR1	= 1	; SPI Clock Rate Select 1
.equ	CPHA	= 2	; Clock Phase
.equ	CPOL	= 3	; Clock polarity
.equ	MSTR	= 4	; Master/Slave Select
.equ	DORD	= 5	; Data Order
.equ	SPE	= 6	; SPI Enable
.equ	SPIE	= 7	; SPI Interrupt Enable


; ***** WATCHDOG *********************
; WDTCSR - Watchdog Timer Control Register
.equ	WDP0	= 0	; Watch Dog Timer Prescaler bit 0
.equ	WDP1	= 1	; Watch Dog Timer Prescaler bit 1
.equ	WDP2	= 2	; Watch Dog Timer Prescaler bit 2
.equ	WDE	= 3	; Watch Dog Enable
.equ	WDCE	= 4	; Watchdog Change Enable
.equ	WDP3	= 5	; Watchdog Timer Prescaler Bit 3
.equ	WDIE	= 6	; Watchdog Timeout Interrupt Enable
.equ	WDIF	= 7	; Watchdog Timeout Interrupt Flag


; ***** EXTERNAL_INTERRUPT ***********
; EICRA - External Interrupt Control Register A
.equ	ISC00	= 0	; External Interrupt Sense Control Bit
.equ	ISC01	= 1	; External Interrupt Sense Control Bit
.equ	ISC10	= 2	; External Interrupt Sense Control Bit
.equ	ISC11	= 3	; External Interrupt Sense Control Bit
.equ	ISC20	= 4	; External Interrupt Sense Control Bit
.equ	ISC21	= 5	; External Interrupt Sense Control Bit
.equ	ISC30	= 6	; External Interrupt Sense Control Bit
.equ	ISC31	= 7	; External Interrupt Sense Control Bit

; EIMSK - External Interrupt Mask Register
.equ	INT0	= 0	; External Interrupt Request 0 Enable
.equ	INT1	= 1	; External Interrupt Request 1 Enable
.equ	INT2	= 2	; External Interrupt Request 2 Enable
.equ	INT3	= 3	; External Interrupt Request 3 Enable

; EIFR - External Interrupt Flag Register
.equ	INTF0	= 0	; External Interrupt Flag 0
.equ	INTF1	= 1	; External Interrupt Flag 1
.equ	INTF2	= 2	; External Interrupt Flag 2
.equ	INTF3	= 3	; External Interrupt Flag 3


; ***** EEPROM ***********************
; EEDR - EEPROM Data Register
.equ	EEDR0	= 0	; EEPROM Data Register bit 0
.equ	EEDR1	= 1	; EEPROM Data Register bit 1
.equ	EEDR2	= 2	; EEPROM Data Register bit 2
.equ	EEDR3	= 3	; EEPROM Data Register bit 3
.equ	EEDR4	= 4	; EEPROM Data Register bit 4
.equ	EEDR5	= 5	; EEPROM Data Register bit 5
.equ	EEDR6	= 6	; EEPROM Data Register bit 6
.equ	EEDR7	= 7	; EEPROM Data Register bit 7

; EECR - EEPROM Control Register
.equ	EERE	= 0	; EEPROM Read Enable
.equ	EEWE	= 1	; EEPROM Write Enable
.equ	EEMWE	= 2	; EEPROM Master Write Enable
.equ	EERIE	= 3	; EEPROM Ready Interrupt Enable


; ***** PSC0 *************************
; PICR0H - PSC 0 Input Capture Register High
.equ	PICR0_8	= 0	; 
.equ	PICR0_9	= 1	; 
.equ	PICR0_10	= 2	; 
.equ	PICR0_11	= 3	; 
.equ	PCST0	= 7	; PSC 0 Capture Software Trigger Bit

; PICR0L - PSC 0 Input Capture Register Low
.equ	PICR0_0	= 0	; 
.equ	PICR0_1	= 1	; 
.equ	PICR0_2	= 2	; 
.equ	PICR0_3	= 3	; 
.equ	PICR0_4	= 4	; 
.equ	PICR0_5	= 5	; 
.equ	PICR0_6	= 6	; 
.equ	PICR0_7	= 7	; 

; PFRC0B - PSC 0 Input B Control
.equ	PRFM0B0	= 0	; PSC 0 Retrigger and Fault Mode for Part B
.equ	PRFM0B1	= 1	; PSC 0 Retrigger and Fault Mode for Part B
.equ	PRFM0B2	= 2	; PSC 0 Retrigger and Fault Mode for Part B
.equ	PRFM0B3	= 3	; PSC 0 Retrigger and Fault Mode for Part B
.equ	PFLTE0B	= 4	; PSC 0 Filter Enable on Input Part B
.equ	PELEV0B	= 5	; PSC 0 Edge Level Selector on Input Part B
.equ	PISEL0B	= 6	; PSC 0 Input Select for Part B
.equ	PCAE0B	= 7	; PSC 0 Capture Enable Input Part B

; PFRC0A - PSC 0 Input A Control
.equ	PRFM0A0	= 0	; PSC 0 Retrigger and Fault Mode for Part A
.equ	PRFM0A1	= 1	; PSC 0 Retrigger and Fault Mode for Part A
.equ	PRFM0A2	= 2	; PSC 0 Retrigger and Fault Mode for Part A
.equ	PRFM0A3	= 3	; PSC 0 Retrigger and Fault Mode for Part A
.equ	PFLTE0A	= 4	; PSC 0 Filter Enable on Input Part A
.equ	PELEV0A	= 5	; PSC 0 Edge Level Selector on Input Part A
.equ	PISEL0A	= 6	; PSC 0 Input Select for Part A
.equ	PCAE0A	= 7	; PSC 0 Capture Enable Input Part A

; PCTL0 - PSC 0 Control Register
.equ	PRUN0	= 0	; PSC 0 Run
.equ	PCCYC0	= 1	; PSC0 Complete Cycle
.equ	PARUN0	= 2	; PSC0 Auto Run
.equ	PAOC0A	= 3	; PSC 0 Asynchronous Output Control A
.equ	PAOC0B	= 4	; PSC 0 Asynchronous Output Control B
.equ	PBFM0	= 5	; PSC 0 Balance Flank Width Modulation
.equ	PPRE00	= 6	; PSC 0 Prescaler Select 0
.equ	PPRE01	= 7	; PSC 0 Prescaler Select 1

; PCNF0 - PSC 0 Configuration Register
.equ	PCLKSEL0	= 1	; PSC 0 Input Clock Select
.equ	POP0	= 2	; PSC 0 Output Polarity
.equ	PMODE00	= 3	; PSC 0 Mode
.equ	PMODE01	= 4	; PSC 0 Mode
.equ	PLOCK0	= 5	; PSC 0 Lock
.equ	PALOCK0	= 6	; PSC 0 Autolock
.equ	PFIFTY0	= 7	; PSC 0 Fifty

; OCR0RBH - Output Compare RB Register High
.equ	OCR0RB_8	= 0	; 
.equ	OCR0RB_9	= 1	; 
.equ	OCR0RB_00	= 2	; 
.equ	OCR0RB_01	= 3	; 
.equ	OCR0RB_02	= 4	; 
.equ	OCR0RB_03	= 5	; 
.equ	OCR0RB_04	= 6	; 
.equ	OCR0RB_05	= 7	; 

; OCR0RBL - Output Compare RB Register Low
.equ	OCR0RB_0	= 0	; 
.equ	OCR0RB_1	= 1	; 
.equ	OCR0RB_2	= 2	; 
.equ	OCR0RB_3	= 3	; 
.equ	OCR0RB_4	= 4	; 
.equ	OCR0RB_5	= 5	; 
.equ	OCR0RB_6	= 6	; 
.equ	OCR0RB_7	= 7	; 

; OCR0SBH - Output Compare SB Register High
.equ	OCR0SB_8	= 0	; 
.equ	OCR0SB_9	= 1	; 
.equ	OCR0SB_00	= 2	; 
.equ	OCR0SB_01	= 3	; 

; OCR0SBL - Output Compare SB Register Low
.equ	OCR0SB_0	= 0	; 
.equ	OCR0SB_1	= 1	; 
.equ	OCR0SB_2	= 2	; 
.equ	OCR0SB_3	= 3	; 
.equ	OCR0SB_4	= 4	; 
.equ	OCR0SB_5	= 5	; 
.equ	OCR0SB_6	= 6	; 
.equ	OCR0SB_7	= 7	; 

; OCR0RAH - Output Compare RA Register High
.equ	OCR0RA_8	= 0	; 
.equ	OCR0RA_9	= 1	; 
.equ	OCR0RA_00	= 2	; 
.equ	OCR0RA_01	= 3	; 

; OCR0RAL - Output Compare RA Register Low
.equ	OCR0RA_0	= 0	; 
.equ	OCR0RA_1	= 1	; 
.equ	OCR0RA_2	= 2	; 
.equ	OCR0RA_3	= 3	; 
.equ	OCR0RA_4	= 4	; 
.equ	OCR0RA_5	= 5	; 
.equ	OCR0RA_6	= 6	; 
.equ	OCR0RA_7	= 7	; 

; OCR0SAH - Output Compare SA Register High
.equ	OCR0SA_8	= 0	; 
.equ	OCR0SA_9	= 1	; 
.equ	OCR0SA_00	= 2	; 
.equ	OCR0SA_01	= 3	; 

; OCR0SAL - Output Compare SA Register Low
.equ	OCR0SA_0	= 0	; 
.equ	OCR0SA_1	= 1	; 
.equ	OCR0SA_2	= 2	; 
.equ	OCR0SA_3	= 3	; 
.equ	OCR0SA_4	= 4	; 
.equ	OCR0SA_5	= 5	; 
.equ	OCR0SA_6	= 6	; 
.equ	OCR0SA_7	= 7	; 

; PSOC0 - PSC0 Synchro and Output Configuration
.equ	POEN0A	= 0	; PSCOUT00 Output Enable
.equ	POEN0B	= 2	; PSCOUT01 Output Enable
.equ	PSYNC00	= 4	; Synchronization Out for ADC Selection
.equ	PSYNC01	= 5	; Synchronization Out for ADC Selection

; PIM0 - PSC0 Interrupt Mask Register
.equ	PEOPE0	= 0	; End of Cycle Interrupt Enable
.equ	PEVE0A	= 3	; External Event A Interrupt Enable
.equ	PEVE0B	= 4	; External Event B Interrupt Enable
.equ	PSEIE0	= 5	; PSC 0 Synchro Error Interrupt Enable

; PIFR0 - PSC0 Interrupt Flag Register
.equ	PEOP0	= 0	; End of PSC0 Interrupt
.equ	PRN00	= 1	; Ramp Number
.equ	PRN01	= 2	; Ramp Number
.equ	PEV0A	= 3	; External Event A Interrupt
.equ	PEV0B	= 4	; External Event B Interrupt
.equ	PSEI0	= 5	; PSC 0 Synchro Error Interrupt
.equ	POAC0A	= 6	; PSC 0 Output A Activity
.equ	POAC0B	= 7	; PSC 0 Output A Activity


; ***** PSC1 *************************
; PICR1H - PSC 1 Input Capture Register High
.equ	PICR1_8	= 0	; 
.equ	PICR1_9	= 1	; 
.equ	PICR1_10	= 2	; 
.equ	PICR1_11	= 3	; 
.equ	PCST1	= 7	; PSC 1 Capture Software Trigger Bit

; PICR1L - PSC 1 Input Capture Register Low
.equ	PICR1_0	= 0	; 
.equ	PICR1_1	= 1	; 
.equ	PICR1_2	= 2	; 
.equ	PICR1_3	= 3	; 
.equ	PICR1_4	= 4	; 
.equ	PICR1_5	= 5	; 
.equ	PICR1_6	= 6	; 
.equ	PICR1_7	= 7	; 

; PFRC1B - PSC 1 Input B Control
.equ	PRFM1B0	= 0	; PSC 1 Retrigger and Fault Mode for Part B
.equ	PRFM1B1	= 1	; PSC 1 Retrigger and Fault Mode for Part B
.equ	PRFM1B2	= 2	; PSC 1 Retrigger and Fault Mode for Part B
.equ	PRFM1B3	= 3	; PSC 1 Retrigger and Fault Mode for Part B
.equ	PFLTE1B	= 4	; PSC 1 Filter Enable on Input Part B
.equ	PELEV1B	= 5	; PSC 1 Edge Level Selector on Input Part B
.equ	PISEL1B	= 6	; PSC 1 Input Select for Part B
.equ	PCAE1B	= 7	; PSC 1 Capture Enable Input Part B

; PFRC1A - PSC 1 Input B Control
.equ	PRFM1A0	= 0	; PSC 1 Retrigger and Fault Mode for Part A
.equ	PRFM1A1	= 1	; PSC 1 Retrigger and Fault Mode for Part A
.equ	PRFM1A2	= 2	; PSC 1 Retrigger and Fault Mode for Part A
.equ	PRFM1A3	= 3	; PSC 1 Retrigger and Fault Mode for Part A
.equ	PFLTE1A	= 4	; PSC 1 Filter Enable on Input Part A
.equ	PELEV1A	= 5	; PSC 1 Edge Level Selector on Input Part A
.equ	PISEL1A	= 6	; PSC 1 Input Select for Part A
.equ	PCAE1A	= 7	; PSC 1 Capture Enable Input Part A

; PCTL1 - PSC 1 Control Register
.equ	PRUN1	= 0	; PSC 1 Run
.equ	PCCYC1	= 1	; PSC1 Complete Cycle
.equ	PARUN1	= 2	; PSC1 Auto Run
.equ	PAOC1A	= 3	; PSC 1 Asynchronous Output Control A
.equ	PAOC1B	= 4	; PSC 1 Asynchronous Output Control B
.equ	PBFM1	= 5	; Balance Flank Width Modulation
.equ	PPRE10	= 6	; PSC 1 Prescaler Select 0
.equ	PPRE11	= 7	; PSC 1 Prescaler Select 1

; PCNF1 - PSC 1 Configuration Register
.equ	PCLKSEL1	= 1	; PSC 1 Input Clock Select
.equ	POP1	= 2	; PSC 1 Output Polarity
.equ	PMODE10	= 3	; PSC 1 Mode
.equ	PMODE11	= 4	; PSC 1 Mode
.equ	PLOCK1	= 5	; PSC 1 Lock
.equ	PALOCK1	= 6	; PSC 1 Autolock
.equ	PFIFTY1	= 7	; PSC 1 Fifty

; OCR1RBH - Output Compare RB Register High
.equ	OCR1RB_8	= 0	; 
.equ	OCR1RB_9	= 1	; 
.equ	OCR1RB_10	= 2	; 
.equ	OCR1RB_11	= 3	; 
.equ	OCR1RB_12	= 4	; 
.equ	OCR1RB_13	= 5	;