pwm3bdef.inc

AVR Assembler 2 compiler

.equ	OCR1RB_14	= 6	; 
.equ	OCR1RB_15	= 7	; 

; OCR1RBL - Output Compare RB Register Low
.equ	OCR1RB_0	= 0	; 
.equ	OCR1RB_1	= 1	; 
.equ	OCR1RB_2	= 2	; 
.equ	OCR1RB_3	= 3	; 
.equ	OCR1RB_4	= 4	; 
.equ	OCR1RB_5	= 5	; 
.equ	OCR1RB_6	= 6	; 
.equ	OCR1RB_7	= 7	; 

; OCR1SBH - Output Compare SB Register High
.equ	OCR1SB_8	= 0	; 
.equ	OCR1SB_9	= 1	; 
.equ	OCR1SB_10	= 2	; 
.equ	OCR1SB_11	= 3	; 

; OCR1SBL - Output Compare SB Register Low
.equ	OCR1SB_0	= 0	; 
.equ	OCR1SB_1	= 1	; 
.equ	OCR1SB_2	= 2	; 
.equ	OCR1SB_3	= 3	; 
.equ	OCR1SB_4	= 4	; 
.equ	OCR1SB_5	= 5	; 
.equ	OCR1SB_6	= 6	; 
.equ	OCR1SB_7	= 7	; 

; OCR1RAH - Output Compare RA Register High
.equ	OCR1RA_8	= 0	; 
.equ	OCR1RA_9	= 1	; 
.equ	OCR1RA_10	= 2	; 
.equ	OCR1RA_11	= 3	; 

; OCR1RAL - Output Compare RA Register Low
.equ	OCR1RA_0	= 0	; 
.equ	OCR1RA_1	= 1	; 
.equ	OCR1RA_2	= 2	; 
.equ	OCR1RA_3	= 3	; 
.equ	OCR1RA_4	= 4	; 
.equ	OCR1RA_5	= 5	; 
.equ	OCR1RA_6	= 6	; 
.equ	OCR1RA_7	= 7	; 

; OCR1SAH - Output Compare SA Register High
.equ	OCR1SA_8	= 0	; 
.equ	OCR1SA_9	= 1	; 
.equ	OCR1SA_10	= 2	; 
.equ	OCR1SA_11	= 3	; 

; OCR1SAL - Output Compare SA Register Low
.equ	OCR1SA_0	= 0	; 
.equ	OCR1SA_1	= 1	; 
.equ	OCR1SA_2	= 2	; 
.equ	OCR1SA_3	= 3	; 
.equ	OCR1SA_4	= 4	; 
.equ	OCR1SA_5	= 5	; 
.equ	OCR1SA_6	= 6	; 
.equ	OCR1SA_7	= 7	; 

; PSOC1 - PSC1 Synchro and Output Configuration
.equ	POEN1A	= 0	; PSCOUT10 Output Enable
.equ	POEN1B	= 2	; PSCOUT11 Output Enable
.equ	PSYNC1_0	= 4	; Synchronization Out for ADC Selection
.equ	PSYNC1_1	= 5	; Synchronization Out for ADC Selection

; PIM1 - PSC1 Interrupt Mask Register
.equ	PEOPE1	= 0	; End of Cycle Interrupt Enable
.equ	PEVE1A	= 3	; External Event A Interrupt Enable
.equ	PEVE1B	= 4	; External Event B Interrupt Enable
.equ	PSEIE1	= 5	; PSC 1 Synchro Error Interrupt Enable

; PIFR1 - PSC1 Interrupt Flag Register
.equ	PEOP1	= 0	; End of PSC1 Interrupt
.equ	PRN10	= 1	; Ramp Number
.equ	PRN11	= 2	; Ramp Number
.equ	PEV1A	= 3	; External Event A Interrupt
.equ	PEV1B	= 4	; External Event B Interrupt
.equ	PSEI1	= 5	; PSC 1 Synchro Error Interrupt
.equ	POAC1A	= 6	; PSC 1 Output A Activity
.equ	POAC1B	= 7	; PSC 1 Output B Activity


; ***** PSC2 *************************
; PICR2H - PSC 2 Input Capture Register High
.equ	PICR2_8	= 0	; 
.equ	PICR2_9	= 1	; 
.equ	PICR2_10	= 2	; 
.equ	PICR2_11	= 3	; 
.equ	PCST2	= 7	; PSC 2 Capture Software Trigger Bit

; PICR2L - PSC 2 Input Capture Register Low
.equ	PICR2_0	= 0	; 
.equ	PICR2_1	= 1	; 
.equ	PICR2_2	= 2	; 
.equ	PICR2_3	= 3	; 
.equ	PICR2_4	= 4	; 
.equ	PICR2_5	= 5	; 
.equ	PICR2_6	= 6	; 
.equ	PICR2_7	= 7	; 

; PFRC2B - PSC 2 Input B Control
.equ	PRFM2B0	= 0	; PSC 2 Retrigger and Fault Mode for Part B
.equ	PRFM2B1	= 1	; PSC 2 Retrigger and Fault Mode for Part B
.equ	PRFM2B2	= 2	; PSC 2 Retrigger and Fault Mode for Part B
.equ	PRFM2B3	= 3	; PSC 2 Retrigger and Fault Mode for Part B
.equ	PFLTE2B	= 4	; PSC 2 Filter Enable on Input Part B
.equ	PELEV2B	= 5	; PSC 2 Edge Level Selector on Input Part B
.equ	PISEL2B	= 6	; PSC 2 Input Select for Part B
.equ	PCAE2B	= 7	; PSC 2 Capture Enable Input Part B

; PFRC2A - PSC 2 Input B Control
.equ	PRFM2A0	= 0	; PSC 2 Retrigger and Fault Mode for Part A
.equ	PRFM2A1	= 1	; PSC 2 Retrigger and Fault Mode for Part A
.equ	PRFM2A2	= 2	; PSC 2 Retrigger and Fault Mode for Part A
.equ	PRFM2A3	= 3	; PSC 2 Retrigger and Fault Mode for Part A
.equ	PFLTE2A	= 4	; PSC 2 Filter Enable on Input Part A
.equ	PELEV2A	= 5	; PSC 2 Edge Level Selector on Input Part A
.equ	PISEL2A	= 6	; PSC 2 Input Select for Part A
.equ	PCAE2A	= 7	; PSC 2 Capture Enable Input Part A

; PCTL2 - PSC 2 Control Register
.equ	PRUN2	= 0	; PSC 2 Run
.equ	PCCYC2	= 1	; PSC2 Complete Cycle
.equ	PARUN2	= 2	; PSC2 Auto Run
.equ	PAOC2A	= 3	; PSC 2 Asynchronous Output Control A
.equ	PAOC2B	= 4	; PSC 2 Asynchronous Output Control B
.equ	PBFM2	= 5	; Balance Flank Width Modulation
.equ	PPRE20	= 6	; PSC 2 Prescaler Select 0
.equ	PPRE21	= 7	; PSC 2 Prescaler Select 1

; PCNF2 - PSC 2 Configuration Register
.equ	POME2	= 0	; PSC 2 Output Matrix Enable
.equ	PCLKSEL2	= 1	; PSC 2 Input Clock Select
.equ	POP2	= 2	; PSC 2 Output Polarity
.equ	PMODE20	= 3	; PSC 2 Mode
.equ	PMODE21	= 4	; PSC 2 Mode
.equ	PLOCK2	= 5	; PSC 2 Lock
.equ	PALOCK2	= 6	; PSC 2 Autolock
.equ	PFIFTY2	= 7	; PSC 2 Fifty

; OCR2RBH - Output Compare RB Register High
.equ	OCR2RB_8	= 0	; 
.equ	OCR2RB_9	= 1	; 
.equ	OCR2RB_10	= 2	; 
.equ	OCR2RB_11	= 3	; 
.equ	OCR2RB_12	= 4	; 
.equ	OCR2RB_13	= 5	; 
.equ	OCR2RB_14	= 6	; 
.equ	OCR2RB_15	= 7	; 

; OCR2RBL - Output Compare RB Register Low
.equ	OCR2RB_0	= 0	; 
.equ	OCR2RB_1	= 1	; 
.equ	OCR2RB_2	= 2	; 
.equ	OCR2RB_3	= 3	; 
.equ	OCR2RB_4	= 4	; 
.equ	OCR2RB_5	= 5	; 
.equ	OCR2RB_6	= 6	; 
.equ	OCR2RB_7	= 7	; 

; OCR2SBH - Output Compare SB Register High
.equ	OCR2SB_8	= 0	; 
.equ	OCR2SB_9	= 1	; 
.equ	OCR2SB_10	= 2	; 
.equ	OCR2SB_11	= 3	; 

; OCR2SBL - Output Compare SB Register Low
.equ	OCR2SB_0	= 0	; 
.equ	OCR2SB_1	= 1	; 
.equ	OCR2SB_2	= 2	; 
.equ	OCR2SB_3	= 3	; 
.equ	OCR2SB_4	= 4	; 
.equ	OCR2SB_5	= 5	; 
.equ	OCR2SB_6	= 6	; 
.equ	OCR2SB_7	= 7	; 

; OCR2RAH - Output Compare RA Register High
.equ	OCR2RA_8	= 0	; 
.equ	OCR2RA_9	= 1	; 
.equ	OCR2RA_10	= 2	; 
.equ	OCR2RA_11	= 3	; 

; OCR2RAL - Output Compare RA Register Low
.equ	OCR2RA_0	= 0	; 
.equ	OCR2RA_1	= 1	; 
.equ	OCR2RA_2	= 2	; 
.equ	OCR2RA_3	= 3	; 
.equ	OCR2RA_4	= 4	; 
.equ	OCR2RA_5	= 5	; 
.equ	OCR2RA_6	= 6	; 
.equ	OCR2RA_7	= 7	; 

; OCR2SAH - Output Compare SA Register High
.equ	OCR2SA_8	= 0	; 
.equ	OCR2SA_9	= 1	; 
.equ	OCR2SA_10	= 2	; 
.equ	OCR2SA_11	= 3	; 

; OCR2SAL - Output Compare SA Register Low
.equ	OCR2SA_0	= 0	; 
.equ	OCR2SA_1	= 1	; 
.equ	OCR2SA_2	= 2	; 
.equ	OCR2SA_3	= 3	; 
.equ	OCR2SA_4	= 4	; 
.equ	OCR2SA_5	= 5	; 
.equ	OCR2SA_6	= 6	; 
.equ	OCR2SA_7	= 7	; 

; POM2 - PSC 2 Output Matrix
.equ	POMV2A0	= 0	; Output Matrix Output A Ramp 0
.equ	POMV2A1	= 1	; Output Matrix Output A Ramp 1
.equ	POMV2A2	= 2	; Output Matrix Output A Ramp 2
.equ	POMV2A3	= 3	; Output Matrix Output A Ramp 3
.equ	POMV2B0	= 4	; Output Matrix Output B Ramp 0
.equ	POMV2B1	= 5	; Output Matrix Output B Ramp 2
.equ	POMV2B2	= 6	; Output Matrix Output B Ramp 2
.equ	POMV2B3	= 7	; Output Matrix Output B Ramp 3

; PSOC2 - PSC2 Synchro and Output Configuration
.equ	POEN2A	= 0	; PSCOUT20 Output Enable
.equ	POEN2C	= 1	; PSCOUT22 Output Enable
.equ	POEN2B	= 2	; PSCOUT21 Output Enable
.equ	POEN2D	= 3	; PSCOUT23 Output Enable
.equ	PSYNC2_0	= 4	; Synchronization Out for ADC Selection
.equ	PSYNC2_1	= 5	; Synchronization Out for ADC Selection
.equ	POS22	= 6	; PSC 2 Output 22 Select
.equ	POS23	= 7	; PSC 2 Output 23 Select

; PIM2 - PSC2 Interrupt Mask Register
.equ	PEOPE2	= 0	; End of Cycle Interrupt Enable
.equ	PEVE2A	= 3	; External Event A Interrupt Enable
.equ	PEVE2B	= 4	; External Event B Interrupt Enable
.equ	PSEIE2	= 5	; PSC 2 Synchro Error Interrupt Enable

; PIFR2 - PSC2 Interrupt Flag Register
.equ	PEOP2	= 0	; End of PSC2 Interrupt
.equ	PRN20	= 1	; Ramp Number
.equ	PRN21	= 2	; Ramp Number
.equ	PEV2A	= 3	; External Event A Interrupt
.equ	PEV2B	= 4	; External Event B Interrupt
.equ	PSEI2	= 5	; PSC 2 Synchro Error Interrupt
.equ	POAC2A	= 6	; PSC 2 Output A Activity
.equ	POAC2B	= 7	; PSC 2 Output A Activity



; ***** LOCKSBITS ********************************************************
.equ	LB1	= 0	; Lock bit
.equ	LB2	= 1	; Lock bit
.equ	BLB01	= 2	; Boot Lock bit
.equ	BLB02	= 3	; Boot Lock bit
.equ	BLB11	= 4	; Boot lock bit
.equ	BLB12	= 5	; Boot lock bit


; ***** FUSES ************************************************************
; LOW fuse bits
.equ	CKSEL0	= 0	; Select Clock Source
.equ	CKSEL1	= 1	; Select Clock Source
.equ	CKSEL2	= 2	; Select Clock Source
.equ	CKSEL3	= 3	; Select Clock Source
.equ	SUT0	= 4	; Select start-up time
.equ	SUT1	= 5	; Select start-up time
.equ	CKOUT	= 6	; Oscillator output option
.equ	CKDIV8	= 7	; Divide clock by 8

; HIGH fuse bits
.equ	BODLEVEL0	= 0	; Brown-out Detector trigger level
.equ	BODLEVEL1	= 1	; Brown-out Detector trigger level
.equ	BODLEVEL2	= 2	; Brown out detector trigger level
.equ	EESAVE	= 3	; EEPROM memory is preserved through chip erase
.equ	WDTON	= 4	; Watchdog timer always on
.equ	SPIEN	= 5	; Enable Serial programming and Data Downloading
.equ	DWEN	= 6	; debugWIRE Enable
.equ	RSTDISBL	= 7	; External Reset Disable

; EXTENDED fuse bits
.equ	BOOTRST	= 0	; Select Reset Vector
.equ	BOOTSZ0	= 1	; Select Boot Size
.equ	BOOTSZ1	= 2	; Select Boot Size
.equ	PSCRV	= 4	; PSCOUT Reset Value
.equ	PSC0RB	= 5	; PSC0 Reset Behaviour
.equ	PSC1RB	= 6	; PSC1 Reset Behaviour
.equ	PSC2RB	= 7	; PSC2 Reset Behaviour



; ***** CPU REGISTER DEFINITIONS *****************************************
.def	XH	= r27
.def	XL	= r26
.def	YH	= r29
.def	YL	= r28
.def	ZH	= r31
.def	ZL	= r30



; ***** DATA MEMORY DECLARATIONS *****************************************
.equ	FLASHEND	= 0x0fff	; Note: Word address
.equ	IOEND	= 0x00ff
.equ	SRAM_START	= 0x0100
.equ	SRAM_SIZE	= 512
.equ	RAMEND	= 0x02ff
.equ	XRAMEND	= 0x0000
.equ	E2END	= 0x01ff
.equ	EEPROMEND	= 0x01ff
.equ	EEADRBITS	= 9
#pragma AVRPART MEMORY PROG_FLASH 8192
#pragma AVRPART MEMORY EEPROM 512
#pragma AVRPART MEMORY INT_SRAM SIZE 512
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100



; ***** BOOTLOADER DECLARATIONS ******************************************
.equ	NRWW_START_ADDR	= 0xc00
.equ	NRWW_STOP_ADDR	= 0xfff
.equ	RWW_START_ADDR	= 0x0
.equ	RWW_STOP_ADDR	= 0xbff
.equ	PAGESIZE	= 32
.equ	FIRSTBOOTSTART	= 0xf80
.equ	SECONDBOOTSTART	= 0xf00
.equ	THIRDBOOTSTART	= 0xe00
.equ	FOURTHBOOTSTART	= 0xc00
.equ	SMALLBOOTSTART	= FIRSTBOOTSTART
.equ	LARGEBOOTSTART	= FOURTHBOOTSTART



; ***** INTERRUPT VECTORS ************************************************
.equ	PSC2_CAPTaddr	= 0x0001	; PSC2 Capture Event
.equ	PSC2_ECaddr	= 0x0002	; PSC2 End Cycle
.equ	PSC1_CAPTaddr	= 0x0003	; PSC1 Capture Event
.equ	PSC1_ECaddr	= 0x0004	; PSC1 End Cycle
.equ	PSC0_CAPTaddr	= 0x0005	; PSC0 Capture Event
.equ	PSC0_ECaddr	= 0x0006	; PSC0 End Cycle
.equ	ACI0addr	= 0x0007	; Analog Comparator 0
.equ	ACI1addr	= 0x0008	; Analog Comparator 1
.equ	ACI2addr	= 0x0009	; Analog Comparator 2
.equ	INT0addr	= 0x000a	; External Interrupt Request 0
.equ	ICP1addr	= 0x000b	; Timer/Counter1 Capture Event
.equ	OC1Aaddr	= 0x000c	; Timer/Counter1 Compare Match A
.equ	OC1Baddr	= 0x000d	; Timer/Counter Compare Match B
.equ	RESERVED15addr	= 0x000e	; 
.equ	OVF1addr	= 0x000f	; Timer/Counter1 Overflow
.equ	OC0Aaddr	= 0x0010	; Timer/Counter0 Compare Match A
.equ	OVF0addr	= 0x0011	; Timer/Counter0 Overflow
.equ	ADCCaddr	= 0x0012	; ADC Conversion Complete
.equ	INT1addr	= 0x0013	; External Interrupt Request 1
.equ	SPIaddr	= 0x0014	; SPI Serial Transfer Complete
.equ	URXCaddr	= 0x0015	; USART, Rx Complete
.equ	UDREaddr	= 0x0016	; USART Data Register Empty
.equ	UTXCaddr	= 0x0017	; USART, Tx Complete
.equ	INT2addr	= 0x0018	; External Interrupt Request 2
.equ	WDTaddr	= 0x0019	; Watchdog Timeout Interrupt
.equ	ERDYaddr	= 0x001a	; EEPROM Ready
.equ	OC0Baddr	= 0x001b	; Timer Counter 0 Compare Match B
.equ	INT3addr	= 0x001c	; External Interrupt Request 3
.equ	RESERVED30addr	= 0x001d	; 
.equ	RESERVED31addr	= 0x001e	; 
.equ	SPMRaddr	= 0x001f	; Store Program Memory Read

.equ	INT_VECTORS_SIZE	= 32	; size in words

#endif  /* _PWM3BDEF_INC_ */

; ***** END OF FILE ******************************************************