📄 pwm3bdef.inc
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.equ MUBRR10 = 2 ; Manchester Receiver Baud Rate Register Bit 10
.equ MUBRR11 = 3 ; Manchester Receiver Baud Rate Register Bit 11
.equ MUBRR12 = 4 ; Manchester Receiver Baud Rate Register Bit 12
.equ MUBRR13 = 5 ; Manchester Receiver Baud Rate Register Bit 13
.equ MUBRR14 = 6 ; Manchester Receiver Baud Rate Register Bit 14
.equ MUBRR15 = 7 ; Manchester Receiver Baud Rate Register Bit 15
; MUBRRL - Manchester Receiver Baud Rate Register Low Byte
.equ MUBRR0 = 0 ; Manchester Receiver Baud Rate Register Bit 0
.equ MUBRR1 = 1 ; Manchester Receiver Baud Rate Register Bit 1
.equ MUBRR2 = 2 ; Manchester Receiver Baud Rate Register Bit 2
.equ MUBRR3 = 3 ; Manchester Receiver Baud Rate Register Bit 3
.equ MUBRR4 = 4 ; Manchester Receiver Baud Rate Register Bit 4
.equ MUBRR5 = 5 ; Manchester Receiver Baud Rate Register Bit 5
.equ MUBRR6 = 6 ; Manchester Receiver Baud Rate Register Bit 6
.equ MUBRR7 = 7 ; Manchester Receiver Baud Rate Register Bit 7
; ***** ANALOG_COMPARATOR ************
; AC0CON - Analog Comparator 0 Control Register
.equ AC0M0 = 0 ; Analog Comparator 0 Multiplexer Register
.equ AC0M1 = 1 ; Analog Comparator 0 Multiplexer Regsiter
.equ AC0M2 = 2 ; Analog Comparator 0 Multiplexer Register
.equ AC0IS0 = 4 ; Analog Comparator 0 Interrupt Select Bit
.equ AC0IS1 = 5 ; Analog Comparator 0 Interrupt Select Bit
.equ AC0IE = 6 ; Analog Comparator 0 Interrupt Enable Bit
.equ AC0EN = 7 ; Analog Comparator 0 Enable Bit
; AC1CON - Analog Comparator 1 Control Register
.equ AC1M0 = 0 ; Analog Comparator 1 Multiplexer Register
.equ AC1M1 = 1 ; Analog Comparator 1 Multiplexer Regsiter
.equ AC1M2 = 2 ; Analog Comparator 1 Multiplexer Register
.equ AC1ICE = 3 ; Analog Comparator 1 Interrupt Capture Enable Bit
.equ AC1IS0 = 4 ; Analog Comparator 1 Interrupt Select Bit
.equ AC1IS1 = 5 ; Analog Comparator 1 Interrupt Select Bit
.equ AC1IE = 6 ; Analog Comparator 1 Interrupt Enable Bit
.equ AC1EN = 7 ; Analog Comparator 1 Enable Bit
; AC2CON - Analog Comparator 2 Control Register
.equ AC2M0 = 0 ; Analog Comparator 2 Multiplexer Register
.equ AC2M1 = 1 ; Analog Comparator 2 Multiplexer Regsiter
.equ AC2M2 = 2 ; Analog Comparator 2 Multiplexer Register
.equ AC2IS0 = 4 ; Analog Comparator 2 Interrupt Select Bit
.equ AC2IS1 = 5 ; Analog Comparator 2 Interrupt Select Bit
.equ AC2IE = 6 ; Analog Comparator 2 Interrupt Enable Bit
.equ AC2EN = 7 ; Analog Comparator 2 Enable Bit
; ACSR - Analog Comparator Status Register
.equ AC0O = 0 ; Analog Comparator 0 Output Bit
.equ AC1O = 1 ; Analog Comparator 1 Output Bit
.equ AC2O = 2 ; Analog Comparator 2 Output Bit
.equ AC0IF = 4 ; Analog Comparator 0 Interrupt Flag Bit
.equ AC1IF = 5 ; Analog Comparator 1 Interrupt Flag Bit
.equ AC2IF = 6 ; Analog Comparator 2 Interrupt Flag Bit
.equ ACCKDIV = 7 ; Analog Comparator Clock Divider
; ***** DA_CONVERTER *****************
; DACH - DAC Data Register High Byte
.equ DACH0 = 0 ; DAC Data Register High Byte Bit 0
.equ DACH1 = 1 ; DAC Data Register High Byte Bit 1
.equ DACH2 = 2 ; DAC Data Register High Byte Bit 2
.equ DACH3 = 3 ; DAC Data Register High Byte Bit 3
.equ DACH4 = 4 ; DAC Data Register High Byte Bit 4
.equ DACH5 = 5 ; DAC Data Register High Byte Bit 5
.equ DACH6 = 6 ; DAC Data Register High Byte Bit 6
.equ DACH7 = 7 ; DAC Data Register High Byte Bit 7
; DACL - DAC Data Register Low Byte
.equ DACL0 = 0 ; DAC Data Register Low Byte Bit 0
.equ DACL1 = 1 ; DAC Data Register Low Byte Bit 1
.equ DACL2 = 2 ; DAC Data Register Low Byte Bit 2
.equ DACL3 = 3 ; DAC Data Register Low Byte Bit 3
.equ DACL4 = 4 ; DAC Data Register Low Byte Bit 4
.equ DACL5 = 5 ; DAC Data Register Low Byte Bit 5
.equ DACL6 = 6 ; DAC Data Register Low Byte Bit 6
.equ DACL7 = 7 ; DAC Data Register Low Byte Bit 7
; DACON - DAC Control Register
.equ DAEN = 0 ; DAC Enable Bit
.equ DAOE = 1 ; DAC Output Enable Bit
.equ DALA = 2 ; DAC Left Adjust
.equ DATS0 = 4 ; DAC Trigger Selection Bit 0
.equ DATS1 = 5 ; DAC Trigger Selection Bit 1
.equ DATS2 = 6 ; DAC Trigger Selection Bit 2
.equ DAATE = 7 ; DAC Auto Trigger Enable Bit
; ***** CPU **************************
; SREG - Status Register
.equ SREG_C = 0 ; Carry Flag
.equ SREG_Z = 1 ; Zero Flag
.equ SREG_N = 2 ; Negative Flag
.equ SREG_V = 3 ; Two's Complement Overflow Flag
.equ SREG_S = 4 ; Sign Bit
.equ SREG_H = 5 ; Half Carry Flag
.equ SREG_T = 6 ; Bit Copy Storage
.equ SREG_I = 7 ; Global Interrupt Enable
; MCUCR - MCU Control Register
.equ IVCE = 0 ; Interrupt Vector Change Enable
.equ IVSEL = 1 ; Interrupt Vector Select
.equ PUD = 4 ; Pull-up disable
.equ SPIPS = 7 ; SPI Pin Select
; MCUSR - MCU Status Register
.equ PORF = 0 ; Power-on reset flag
.equ EXTRF = 1 ; External Reset Flag
.equ BORF = 2 ; Brown-out Reset Flag
.equ WDRF = 3 ; Watchdog Reset Flag
; OSCCAL - Oscillator Calibration Value
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6
; CLKPR -
.equ CLKPS0 = 0 ;
.equ CLKPS1 = 1 ;
.equ CLKPS2 = 2 ;
.equ CLKPS3 = 3 ;
.equ CLKPCE = 7 ;
; SMCR - Sleep Mode Control Register
.equ SE = 0 ; Sleep Enable
.equ SM0 = 1 ; Sleep Mode Select bit 0
.equ SM1 = 2 ; Sleep Mode Select bit 1
.equ SM2 = 3 ; Sleep Mode Select bit 2
; GPIOR3 - General Purpose IO Register 3
.equ GPIOR30 = 0 ; General Purpose IO Register 3 bit 0
.equ GPIOR31 = 1 ; General Purpose IO Register 3 bit 1
.equ GPIOR32 = 2 ; General Purpose IO Register 3 bit 2
.equ GPIOR33 = 3 ; General Purpose IO Register 3 bit 3
.equ GPIOR34 = 4 ; General Purpose IO Register 3 bit 4
.equ GPIOR35 = 5 ; General Purpose IO Register 3 bit 5
.equ GPIOR36 = 6 ; General Purpose IO Register 3 bit 6
.equ GPIOR37 = 7 ; General Purpose IO Register 3 bit 7
; GPIOR2 - General Purpose IO Register 2
.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0
.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1
.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2
.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3
.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4
.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5
.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6
.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7
; GPIOR1 - General Purpose IO Register 1
.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0
.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1
.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2
.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3
.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4
.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5
.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6
.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7
; GPIOR0 - General Purpose IO Register 0
.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0
.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1
.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2
.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3
.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4
.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5
.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6
.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7
; PLLCSR - PLL Control And Status Register
.equ PLOCK = 0 ; PLL Lock Detector
.equ PLLE = 1 ; PLL Enable
.equ PLLF = 2 ; PLL Factor
; PRR - Power Reduction Register
.equ PRADC = 0 ; Power Reduction ADC
.equ PRUSART0 = 1 ; Power Reduction USART
.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface
.equ PRTIM0 = 3 ; Power Reduction Timer/Counter0
.equ PRTIM1 = 4 ; Power Reduction Timer/Counter1
.equ PRPSC0 = 5 ; Power Reduction PSC0
.equ PRPSC1 = 6 ; Power Reduction PSC1
.equ PRPSC2 = 7 ; Power Reduction PSC2
; ***** PORTE ************************
; PORTE - Port E Data Register
.equ PORTE0 = 0 ;
.equ PE0 = 0 ; For compatibility
.equ PORTE1 = 1 ;
.equ PE1 = 1 ; For compatibility
.equ PORTE2 = 2 ;
.equ PE2 = 2 ; For compatibility
; DDRE - Port E Data Direction Register
.equ DDE0 = 0 ;
.equ DDE1 = 1 ;
.equ DDE2 = 2 ;
; PINE - Port E Input Pins
.equ PINE0 = 0 ;
.equ PINE1 = 1 ;
.equ PINE2 = 2 ;
; ***** TIMER_COUNTER_0 **************
; TIMSK0 - Timer/Counter0 Interrupt Mask Register
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable
.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable
; TIFR0 - Timer/Counter0 Interrupt Flag register
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0A
.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B
; TCCR0A - Timer/Counter Control Register A
.equ WGM00 = 0 ; Waveform Generation Mode
.equ WGM01 = 1 ; Waveform Generation Mode
.equ COM0B0 = 4 ; Compare Output Mode, Fast PWm
.equ COM0B1 = 5 ; Compare Output Mode, Fast PWm
.equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode
.equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode
; TCCR0B - Timer/Counter Control Register B
.equ CS00 = 0 ; Clock Select
.equ CS01 = 1 ; Clock Select
.equ CS02 = 2 ; Clock Select
.equ WGM02 = 3 ;
.equ FOC0B = 6 ; Force Output Compare B
.equ FOC0A = 7 ; Force Output Compare A
; TCNT0 - Timer/Counter0
.equ TCNT0_0 = 0 ;
.equ TCNT0_1 = 1 ;
.equ TCNT0_2 = 2 ;
.equ TCNT0_3 = 3 ;
.equ TCNT0_4 = 4 ;
.equ TCNT0_5 = 5 ;
.equ TCNT0_6 = 6 ;
.equ TCNT0_7 = 7 ;
; OCR0A - Timer/Counter0 Output Compare Register
.equ OCR0_0 = 0 ;
.equ OCR0_1 = 1 ;
.equ OCR0_2 = 2 ;
.equ OCR0_3 = 3 ;
.equ OCR0_4 = 4 ;
.equ OCR0_5 = 5 ;
.equ OCR0_6 = 6 ;
.equ OCR0_7 = 7 ;
; OCR0B - Timer/Counter0 Output Compare Register
;.equ OCR0_0 = 0 ;
;.equ OCR0_1 = 1 ;
;.equ OCR0_2 = 2 ;
;.equ OCR0_3 = 3 ;
;.equ OCR0_4 = 4 ;
;.equ OCR0_5 = 5 ;
;.equ OCR0_6 = 6 ;
;.equ OCR0_7 = 7 ;
; GTCCR - General Timer/Counter Control Register
.equ PSR10 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0
.equ ICPSEL1 = 6 ; Timer1 Input Capture Selection Bit
.equ TSM = 7 ; Timer/Counter Synchronization Mode
; ***** TIMER_COUNTER_1 **************
; TIMSK1 - Timer/Counter Interrupt Mask Register
.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable
.equ OCIE1A = 1 ; Timer/Counter1 Output CompareA Match Interrupt Enable
.equ OCIE1B = 2 ; Timer/Counter1 Output CompareB Match Interrupt Enable
.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable
; TIFR1 - Timer/Counter Interrupt Flag register
.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag
.equ OCF1A = 1 ; Output Compare Flag 1A
.equ OCF1B = 2 ; Output Compare Flag 1B
.equ ICF1 = 5 ; Input Capture Flag 1
; TCCR1A - Timer/Counter1 Control Register A
.equ WGM10 = 0 ; Waveform Generation Mode
.equ WGM11 = 1 ; Waveform Generation Mode
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
; TCCR1B - Timer/Counter1 Control Register B
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1
.equ WGM12 = 3 ; Waveform Generation Mode
.equ WGM13 = 4 ; Waveform Generation Mode
.equ ICES1 = 6 ; Input Capture 1 Edge Select
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
; TCCR1C - Timer/Counter1 Control Register C
.equ FOC1B = 6 ;
.equ FOC1A = 7 ;
; GTCCR - General Timer/Counter Control Register
.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0
;.equ TSM = 7 ; Timer/Counter Synchronization Mode
; ***** AD_CONVERTER *****************
; ADMUX - The ADC multiplexer Selection Register
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits
.equ ADLAR = 5 ; Left Adjust Result
.equ REFS0 = 6 ; Reference Selection Bit 0
.equ REFS1 = 7 ; Reference Selection Bit 1
; ADCSRA - The ADC Control and Status register
.equ ADPS0 = 0 ; ADC Prescaler Select Bits
.equ ADPS1 = 1 ; ADC Prescaler Select Bits
.equ ADPS2 = 2 ; ADC Prescaler Select Bits
.equ ADIE = 3 ; ADC Interrupt Enable
.equ ADIF = 4 ; ADC Interrupt Flag
.equ ADATE = 5 ; ADC Auto Trigger Enable
.equ ADSC = 6 ; ADC Start Conversion
.equ ADEN = 7 ; ADC Enable
; ADCH - ADC Data Register High Byte
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7
; ADCL - ADC Data Register Low Byte
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7
; ADCSRB - ADC Control and Status Register B
.equ ADTS0 = 0 ; ADC Auto Trigger Source 0
.equ ADTS1 = 1 ; ADC Auto Trigger Source 1
.equ ADTS2 = 2 ; ADC Auto Trigger Source 2
.equ ADTS3 = 3 ; ADC Auto Trigger Source 3
.equ ADASCR = 4 ; ADC on Amplified Channel Start Conversion Request Bit
.equ ADHSM = 7 ; ADC High Speed Mode
; DIDR0 - Digital Input Disable Register 0
.equ ADC0D = 0 ; ADC0 Digital input Disable
.equ ADC1D = 1 ; ADC1 Digital input Disable
.equ ADC2D = 2 ; ADC2 Digital input Disable
.equ ADC3D = 3 ; ADC3 Digital input Disable
.equ ADC4D = 4 ; ADC4 Digital input Disable
.equ ADC5D = 5 ; ADC5 Digital input Disable
.equ ADC6D = 6 ; ADC6 Digital input Disable
.equ ADC7D = 7 ; ADC7 Digital input Disable
; DIDR1 - Digital Input Disable Register 0
.equ ADC8D = 0 ;
.equ ADC9D = 1 ;
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