📄 pwm324def.inc
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; EEDR - EEPROM Data Register
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
; EECR - EEPROM Control Register
.equ EERE = 0 ; EEPROM Read Enable
.equ EEWE = 1 ; EEPROM Write Enable
.equ EEMWE = 2 ; EEPROM Master Write Enable
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable
; ***** PSC **************************
; PIFR - PSC Interrupt Flag Register
.equ PEOP = 0 ; PSC End of Cycle Interrupt
.equ PEV0 = 1 ; PSC External Event 0 Interrupt
.equ PEV1 = 2 ; PSC External Event 1 Interrupt
.equ PEV2 = 3 ; PSC External Event 2 Interrupt
; PIM - PSC Interrupt Mask Register
.equ PEOPE = 0 ; PSC End of Cycle Interrupt Enable
.equ PEVE0 = 1 ; External Event 0 Interrupt Enable
.equ PEVE1 = 2 ; External Event 1 Interrupt Enable
.equ PEVE2 = 3 ; External Event 2 Interrupt Enable
; PMIC2 - PSC Module 2 Input Control Register
.equ PRFM20 = 0 ; PSC Module 2 Input Mode bit 0
.equ PRFM21 = 1 ; PSC Module 2 Input Mode bit 1
.equ PRFM22 = 2 ; PSC Module 2 Input Mode bit 2
.equ PAOC2 = 3 ; PSC Module 2 Asynchronous Output Control
.equ PFLTE2 = 4 ; PSC Module 2 Input Filter Enable
.equ PELEV2 = 5 ; PSC Module 2 Input Level Selector
.equ PISEL2 = 6 ; PSC Module 2 Input Select
.equ POVEN2 = 7 ; PSC Module 2 Overlap Enable
; PMIC1 - PSC Module 1 Input Control Register
.equ PRFM10 = 0 ; PSC Module 1 Input Mode bit 0
.equ PRFM11 = 1 ; PSC Module 1 Input Mode bit 1
.equ PRFM12 = 2 ; PSC Module 1 Input Mode bit 2
.equ PAOC1 = 3 ; PSC Module 1 Asynchronous Output Control
.equ PFLTE1 = 4 ; PSC Module 1 Input Filter Enable
.equ PELEV1 = 5 ; PSC Module 1 Input Level Selector
.equ PISEL1 = 6 ; PSC Module 1 Input Select
.equ POVEN1 = 7 ; PSC Module 1 Overlap Enable
; PMIC0 - PSC Module 0 Input Control Register
.equ PRFM00 = 0 ; PSC Module 0 Input Mode bit 0
.equ PRFM01 = 1 ; PSC Module 0 Input Mode bit 1
.equ PRFM02 = 2 ; PSC Module 0 Input Mode bit 2
.equ PAOC0 = 3 ; PSC Module 0 Asynchronous Output Control
.equ PFLTE0 = 4 ; PSC Module 0 Input Filter Enable
.equ PELEV0 = 5 ; PSC Module 0 Input Level Selector
.equ PISEL0 = 6 ; PSC Module 0 Input Select
.equ POVEN0 = 7 ; PSC Module 0 Overlap Enable
; PCTL - PSC Control Register
.equ PRUN = 0 ; PSC Run
.equ PCCYC = 1 ; PSC Complete Cycle
.equ PCLKSEL = 5 ; PSC Input Clock Select
.equ PPRE0 = 6 ; PSC Prescaler Select bit 0
.equ PPRE1 = 7 ; PSC Prescaler Select bit 1
; POC - PSC Output Configuration
.equ POEN0A = 0 ; PSC Output 0A Enable
.equ POEN0B = 1 ; PSC Output 0B Enable
.equ POEN1A = 2 ; PSC Output 1A Enable
.equ POEN1B = 3 ; PSC Output 1B Enable
.equ POEN2A = 4 ; PSC Output 2A Enable
.equ POEN2B = 5 ; PSC Output 2B Enable
; PCNF - PSC Configuration Register
.equ POPA = 2 ; PSC Output A Polarity
.equ POPB = 3 ; PSC Output B Polarity
.equ PMODE = 4 ; PSC Mode
.equ PULOCK = 5 ; PSC Update Lock
; PSYNC - PSC Synchro Configuration
.equ PSYNC00 = 0 ; Selection of Synchronization Out for ADC
.equ PSYNC01 = 1 ; Selection of Synchronization Out for ADC
.equ PSYNC10 = 2 ; Selection of Synchronization Out for ADC
.equ PSYNC11 = 3 ; Selection of Synchronization Out for ADC
.equ PSYNC20 = 4 ; Selection of Synchronization Out for ADC
.equ PSYNC21 = 5 ; Selection of Synchronization Out for ADC
; POCRxRBH - PSC Output Compare RB Register High
.equ POCR_RB_8 = 0 ;
.equ POCR_RB_9 = 1 ;
.equ POCR_RB_00 = 2 ;
.equ POCR_RB_01 = 3 ;
; POCRxRBL - PSC Output Compare RB Register Low
.equ POCR_RB_0 = 0 ;
.equ POCR_RB_1 = 1 ;
.equ POCR_RB_2 = 2 ;
.equ POCR_RB_3 = 3 ;
.equ POCR_RB_4 = 4 ;
.equ POCR_RB_5 = 5 ;
.equ POCR_RB_6 = 6 ;
.equ POCR_RB_7 = 7 ;
; POCR2SBH - PSC Module 2 Output Compare SB Register High
.equ POCR2SB_8 = 0 ;
.equ POCR2SB_9 = 1 ;
.equ POCR2SB_00 = 2 ;
.equ POCR2SB_01 = 3 ;
; POCR2SBL - PSC Module 2 Output Compare SB Register Low
.equ POCR2SB_0 = 0 ;
.equ POCR2SB_1 = 1 ;
.equ POCR2SB_2 = 2 ;
.equ POCR2SB_3 = 3 ;
.equ POCR2SB_4 = 4 ;
.equ POCR2SB_5 = 5 ;
.equ POCR2SB_6 = 6 ;
.equ POCR2SB_7 = 7 ;
; POCR2RAH - PSC Module 2 Output Compare RA Register High
.equ POCR2RA_8 = 0 ;
.equ POCR2RA_9 = 1 ;
.equ POCR2RA_00 = 2 ;
.equ POCR2RA_01 = 3 ;
; POCR2RAL - PSC Module 2 Output Compare RA Register Low
.equ POCR2RA_0 = 0 ;
.equ POCR2RA_1 = 1 ;
.equ POCR2RA_2 = 2 ;
.equ POCR2RA_3 = 3 ;
.equ POCR2RA_4 = 4 ;
.equ POCR2RA_5 = 5 ;
.equ POCR2RA_6 = 6 ;
.equ POCR2RA_7 = 7 ;
; POCR2SAH - PSC Module 2 Output Compare SA Register High
.equ POCR2SA_8 = 0 ;
.equ POCR2SA_9 = 1 ;
.equ POCR2SA_00 = 2 ;
.equ POCR2SA_01 = 3 ;
; POCR2SAL - PSC Module 2 Output Compare SA Register Low
.equ POCR2SA_0 = 0 ;
.equ POCR2SA_1 = 1 ;
.equ POCR2SA_2 = 2 ;
.equ POCR2SA_3 = 3 ;
.equ POCR2SA_4 = 4 ;
.equ POCR2SA_5 = 5 ;
.equ POCR2SA_6 = 6 ;
.equ POCR2SA_7 = 7 ;
; POCR1SBH - PSC Module 1 Output Compare SB Register High
.equ POCR1SB_8 = 0 ;
.equ POCR1SB_9 = 1 ;
.equ POCR1SB_00 = 2 ;
.equ POCR1SB_01 = 3 ;
; POCR1SBL - PSC Module 1 Output Compare SB Register Low
.equ POCR1SB_0 = 0 ;
.equ POCR1SB_1 = 1 ;
.equ POCR1SB_2 = 2 ;
.equ POCR1SB_3 = 3 ;
.equ POCR1SB_4 = 4 ;
.equ POCR1SB_5 = 5 ;
.equ POCR1SB_6 = 6 ;
.equ POCR1SB_7 = 7 ;
; POCR1RAH - PSC Module 1 Output Compare RA Register High
.equ POCR1RA_8 = 0 ;
.equ POCR1RA_9 = 1 ;
.equ POCR1RA_00 = 2 ;
.equ POCR1RA_01 = 3 ;
; POCR1RAL - PSC Module 1 Output Compare RA Register Low
.equ POCR1RA_0 = 0 ;
.equ POCR1RA_1 = 1 ;
.equ POCR1RA_2 = 2 ;
.equ POCR1RA_3 = 3 ;
.equ POCR1RA_4 = 4 ;
.equ POCR1RA_5 = 5 ;
.equ POCR1RA_6 = 6 ;
.equ POCR1RA_7 = 7 ;
; POCR1SAH - PSC Output Compare SA Register High
.equ POCR1SA_8 = 0 ;
.equ POCR1SA_9 = 1 ;
.equ POCR1SA_00 = 2 ;
.equ POCR1SA_01 = 3 ;
; POCR1SAL - PSC Module 1 Output Compare SA Register Low
.equ POCR1SA_0 = 0 ;
.equ POCR1SA_1 = 1 ;
.equ POCR1SA_2 = 2 ;
.equ POCR1SA_3 = 3 ;
.equ POCR1SA_4 = 4 ;
.equ POCR1SA_5 = 5 ;
.equ POCR1SA_6 = 6 ;
.equ POCR1SA_7 = 7 ;
; POCR0SBH - PSC Output Compare SB Register High
.equ POCR0SB_8 = 0 ;
.equ POCR0SB_9 = 1 ;
.equ POCR0SB_00 = 2 ;
.equ POCR0SB_01 = 3 ;
; POCR0SBL - PSC Module 0 Output Compare SB Register Low
.equ POCR0SB_0 = 0 ;
.equ POCR0SB_1 = 1 ;
.equ POCR0SB_2 = 2 ;
.equ POCR0SB_3 = 3 ;
.equ POCR0SB_4 = 4 ;
.equ POCR0SB_5 = 5 ;
.equ POCR0SB_6 = 6 ;
.equ POCR0SB_7 = 7 ;
; POCR0RAH - PSC Module 0 Output Compare RA Register High
.equ POCR0RA_8 = 0 ;
.equ POCR0RA_9 = 1 ;
.equ POCR0RA_00 = 2 ;
.equ POCR0RA_01 = 3 ;
; POCR0RAL - PSC Module 0 Output Compare RA Register Low
.equ POCR0RA_0 = 0 ;
.equ POCR0RA_1 = 1 ;
.equ POCR0RA_2 = 2 ;
.equ POCR0RA_3 = 3 ;
.equ POCR0RA_4 = 4 ;
.equ POCR0RA_5 = 5 ;
.equ POCR0RA_6 = 6 ;
.equ POCR0RA_7 = 7 ;
; POCR0SAH - PSC Module 0 Output Compare SA Register High
.equ POCR0SA_8 = 0 ;
.equ POCR0SA_9 = 1 ;
.equ POCR0SA_00 = 2 ;
.equ POCR0SA_01 = 3 ;
; POCR0SAL - PSC Module 0 Output Compare SA Register Low
.equ POCR0SA_0 = 0 ;
.equ POCR0SA_1 = 1 ;
.equ POCR0SA_2 = 2 ;
.equ POCR0SA_3 = 3 ;
.equ POCR0SA_4 = 4 ;
.equ POCR0SA_5 = 5 ;
.equ POCR0SA_6 = 6 ;
.equ POCR0SA_7 = 7 ;
; ***** LOCKSBITS ********************************************************
.equ LB1 = 0 ; Lock bit
.equ LB2 = 1 ; Lock bit
.equ BLB01 = 2 ; Boot Lock bit
.equ BLB02 = 3 ; Boot Lock bit
.equ BLB11 = 4 ; Boot lock bit
.equ BLB12 = 5 ; Boot lock bit
; ***** FUSES ************************************************************
; LOW fuse bits
.equ CKSEL0 = 0 ; Select Clock Source
.equ CKSEL1 = 1 ; Select Clock Source
.equ CKSEL2 = 2 ; Select Clock Source
.equ CKSEL3 = 3 ; Select Clock Source
.equ SUT0 = 4 ; Select start-up time
.equ SUT1 = 5 ; Select start-up time
.equ CKOUT = 6 ; Oscillator output option
.equ CKDIV8 = 7 ; Divide clock by 8
; HIGH fuse bits
.equ BOOTRST = 0 ; Select Reset Vector
.equ BOOTSZ0 = 1 ; Select Boot Size
.equ BOOTSZ1 = 2 ; Select Boot Size
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase
.equ WDTON = 4 ; Watchdog timer always on
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading
.equ DWEN = 6 ; dwbugWIRE Enable
.equ RSTDISBL = 7 ; External Reset Disable
; EXTENDED fuse bits
.equ BODLEVEL0 = 0 ; Brown-out Detector Trigger Level
.equ BODLEVEL1 = 1 ; Brown-out Detector Trigger Level
.equ BODLEVEL2 = 2 ; Brown-out Detector Trigger Level
.equ PSCBRV = 3 ; PSC Outputs xB Reset Value
.equ PSCARV = 4 ; PSC Outputs xA Reset Value
.equ PSCRB = 5 ; PSC Reset Behavior
; ***** CPU REGISTER DEFINITIONS *****************************************
.def XH = r27
.def XL = r26
.def YH = r29
.def YL = r28
.def ZH = r31
.def ZL = r30
; ***** DATA MEMORY DECLARATIONS *****************************************
.equ FLASHEND = 0x3fff ; Note: Word address
.equ IOEND = 0x00ff
.equ SRAM_START = 0x0100
.equ SRAM_SIZE = 2048
.equ RAMEND = 0x08ff
.equ XRAMEND = 0x0000
.equ E2END = 0x03ff
.equ EEPROMEND = 0x03ff
.equ EEADRBITS = 10
#pragma AVRPART MEMORY PROG_FLASH 32768
#pragma AVRPART MEMORY EEPROM 1024
#pragma AVRPART MEMORY INT_SRAM SIZE 2048
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100
; ***** BOOTLOADER DECLARATIONS ******************************************
.equ NRWW_START_ADDR = 0x3800
.equ NRWW_STOP_ADDR = 0x3fff
.equ RWW_START_ADDR = 0x0
.equ RWW_STOP_ADDR = 0x37ff
.equ PAGESIZE = 64
.equ FIRSTBOOTSTART = 0x3f00
.equ SECONDBOOTSTART = 0x3e00
.equ THIRDBOOTSTART = 0x3c00
.equ FOURTHBOOTSTART = 0x3800
.equ SMALLBOOTSTART = FIRSTBOOTSTART
.equ LARGEBOOTSTART = FOURTHBOOTSTART
; ***** INTERRUPT VECTORS ************************************************
.equ ACI0addr = 0x0002 ; Analog Comparator 0
.equ ACI1addr = 0x0004 ; Analog Comparator 1
.equ ACI2addr = 0x0006 ; Analog Comparator 2
.equ ACI3addr = 0x0008 ; Analog Comparator 3
.equ PSC_FAULTaddr = 0x000a ; PSC Fault
.equ PSC_ECaddr = 0x000c ; PSC End of Cycle
.equ INT0addr = 0x000e ; External Interrupt Request 0
.equ INT1addr = 0x0010 ; External Interrupt Request 1
.equ INT2addr = 0x0012 ; External Interrupt Request 2
.equ INT3addr = 0x0014 ; External Interrupt Request 3
.equ ICP1addr = 0x0016 ; Timer/Counter1 Capture Event
.equ OC1Aaddr = 0x0018 ; Timer/Counter1 Compare Match A
.equ OC1Baddr = 0x001a ; Timer/Counter1 Compare Match B
.equ OVF1addr = 0x001c ; Timer1/Counter1 Overflow
.equ OC0Aaddr = 0x001e ; Timer/Counter0 Compare Match A
.equ OC0Baddr = 0x0020 ; Timer/Counter0 Compare Match B
.equ OVF0addr = 0x0022 ; Timer/Counter0 Overflow
.equ CAN_INTaddr = 0x0024 ; CAN MOB, Burst, General Errors
.equ CAN_TOVFaddr = 0x0026 ; CAN Timer Overflow
.equ LIN_TCaddr = 0x0028 ; LIN Transfer Complete
.equ LIN_ERRaddr = 0x002a ; LIN Error
.equ PCI0addr = 0x002c ; Pin Change Interrupt Request 0
.equ PCI1addr = 0x002e ; Pin Change Interrupt Request 1
.equ PCI2addr = 0x0030 ; Pin Change Interrupt Request 2
.equ PCI3addr = 0x0032 ; Pin Change Interrupt Request 3
.equ SPIaddr = 0x0034 ; SPI Serial Transfer Complete
.equ ADCCaddr = 0x0036 ; ADC Conversion Complete
.equ WDTaddr = 0x0038 ; Watchdog Time-Out Interrupt
.equ ERDYaddr = 0x003a ; EEPROM Ready
.equ SPMRaddr = 0x003c ; Store Program Memory Read
.equ INT_VECTORS_SIZE = 62 ; size in words
#endif /* _PWM324DEF_INC_ */
; ***** END OF FILE ******************************************************
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