📄 pwm324def.inc
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.equ PRPSC1 = 6 ; Power Reduction PSC1
.equ PRPSC2 = 7 ; Power Reduction PSC2
; ***** PORTE ************************
; PORTE - Port E Data Register
.equ PORTE0 = 0 ;
.equ PE0 = 0 ; For compatibility
.equ PORTE1 = 1 ;
.equ PE1 = 1 ; For compatibility
.equ PORTE2 = 2 ;
.equ PE2 = 2 ; For compatibility
; DDRE - Port E Data Direction Register
.equ DDE0 = 0 ;
.equ DDE1 = 1 ;
.equ DDE2 = 2 ;
; PINE - Port E Input Pins
.equ PINE0 = 0 ;
.equ PINE1 = 1 ;
.equ PINE2 = 2 ;
; ***** TIMER_COUNTER_0 **************
; TIMSK0 - Timer/Counter0 Interrupt Mask Register
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable
.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable
; TIFR0 - Timer/Counter0 Interrupt Flag register
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0A
.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B
; TCCR0A - Timer/Counter Control Register A
.equ WGM00 = 0 ; Waveform Generation Mode
.equ WGM01 = 1 ; Waveform Generation Mode
.equ COM0B0 = 4 ; Compare Output Mode, Fast PWm
.equ COM0B1 = 5 ; Compare Output Mode, Fast PWm
.equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode
.equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode
; TCCR0B - Timer/Counter Control Register B
.equ CS00 = 0 ; Clock Select
.equ CS01 = 1 ; Clock Select
.equ CS02 = 2 ; Clock Select
.equ WGM02 = 3 ;
.equ FOC0B = 6 ; Force Output Compare B
.equ FOC0A = 7 ; Force Output Compare A
; TCNT0 - Timer/Counter0
.equ TCNT0_0 = 0 ;
.equ TCNT0_1 = 1 ;
.equ TCNT0_2 = 2 ;
.equ TCNT0_3 = 3 ;
.equ TCNT0_4 = 4 ;
.equ TCNT0_5 = 5 ;
.equ TCNT0_6 = 6 ;
.equ TCNT0_7 = 7 ;
; OCR0A - Timer/Counter0 Output Compare Register
.equ OCR0_0 = 0 ;
.equ OCR0_1 = 1 ;
.equ OCR0_2 = 2 ;
.equ OCR0_3 = 3 ;
.equ OCR0_4 = 4 ;
.equ OCR0_5 = 5 ;
.equ OCR0_6 = 6 ;
.equ OCR0_7 = 7 ;
; OCR0B - Timer/Counter0 Output Compare Register
;.equ OCR0_0 = 0 ;
;.equ OCR0_1 = 1 ;
;.equ OCR0_2 = 2 ;
;.equ OCR0_3 = 3 ;
;.equ OCR0_4 = 4 ;
;.equ OCR0_5 = 5 ;
;.equ OCR0_6 = 6 ;
;.equ OCR0_7 = 7 ;
; GTCCR - General Timer/Counter Control Register
.equ PSR10 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0
.equ ICPSEL1 = 6 ; Timer1 Input Capture Selection Bit
.equ TSM = 7 ; Timer/Counter Synchronization Mode
; ***** TIMER_COUNTER_1 **************
; TIMSK1 - Timer/Counter Interrupt Mask Register
.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable
.equ OCIE1A = 1 ; Timer/Counter1 Output CompareA Match Interrupt Enable
.equ OCIE1B = 2 ; Timer/Counter1 Output CompareB Match Interrupt Enable
.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable
; TIFR1 - Timer/Counter Interrupt Flag register
.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag
.equ OCF1A = 1 ; Output Compare Flag 1A
.equ OCF1B = 2 ; Output Compare Flag 1B
.equ ICF1 = 5 ; Input Capture Flag 1
; TCCR1A - Timer/Counter1 Control Register A
.equ WGM10 = 0 ; Waveform Generation Mode
.equ WGM11 = 1 ; Waveform Generation Mode
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
; TCCR1B - Timer/Counter1 Control Register B
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1
.equ WGM12 = 3 ; Waveform Generation Mode
.equ WGM13 = 4 ; Waveform Generation Mode
.equ ICES1 = 6 ; Input Capture 1 Edge Select
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
; TCCR1C - Timer/Counter1 Control Register C
.equ FOC1B = 6 ;
.equ FOC1A = 7 ;
; GTCCR - General Timer/Counter Control Register
.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0
;.equ TSM = 7 ; Timer/Counter Synchronization Mode
; ***** AD_CONVERTER *****************
; ADMUX - The ADC multiplexer Selection Register
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits
.equ ADLAR = 5 ; Left Adjust Result
.equ REFS0 = 6 ; Reference Selection Bit 0
.equ REFS1 = 7 ; Reference Selection Bit 1
; ADCSRA - The ADC Control and Status register
.equ ADPS0 = 0 ; ADC Prescaler Select Bits
.equ ADPS1 = 1 ; ADC Prescaler Select Bits
.equ ADPS2 = 2 ; ADC Prescaler Select Bits
.equ ADIE = 3 ; ADC Interrupt Enable
.equ ADIF = 4 ; ADC Interrupt Flag
.equ ADATE = 5 ; ADC Auto Trigger Enable
.equ ADSC = 6 ; ADC Start Conversion
.equ ADEN = 7 ; ADC Enable
; ADCH - ADC Data Register High Byte
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7
; ADCL - ADC Data Register Low Byte
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7
; ADCSRB - ADC Control and Status Register B
.equ ADTS0 = 0 ; ADC Auto Trigger Source 0
.equ ADTS1 = 1 ; ADC Auto Trigger Source 1
.equ ADTS2 = 2 ; ADC Auto Trigger Source 2
.equ ADTS3 = 3 ; ADC Auto Trigger Source 3
.equ ADASCR = 4 ; ADC on Amplified Channel Start Conversion Request Bit
.equ ADHSM = 7 ; ADC High Speed Mode
; DIDR0 - Digital Input Disable Register 0
.equ ADC0D = 0 ; ADC0 Digital input Disable
.equ ADC1D = 1 ; ADC1 Digital input Disable
.equ ADC2D = 2 ; ADC2 Digital input Disable
.equ ADC3D = 3 ; ADC3 Digital input Disable
.equ ADC4D = 4 ; ADC4 Digital input Disable
.equ ADC5D = 5 ; ADC5 Digital input Disable
.equ ADC6D = 6 ; ADC6 Digital input Disable
.equ ADC7D = 7 ; ADC7 Digital input Disable
; DIDR1 - Digital Input Disable Register 0
.equ ADC8D = 0 ;
.equ ADC9D = 1 ;
.equ ADC10D = 2 ;
.equ AMP0ND = 3 ;
.equ AMP0PD = 4 ;
.equ ACMP0D = 5 ;
; AMP0CSR -
.equ AMP0TS0 = 0 ;
.equ AMP0TS1 = 1 ;
.equ AMP0G0 = 4 ;
.equ AMP0G1 = 5 ;
.equ AMP0IS = 6 ;
.equ AMP0EN = 7 ;
; AMP1CSR -
.equ AMP1TS0 = 0 ;
.equ AMP1TS1 = 1 ;
.equ AMP1G0 = 4 ;
.equ AMP1G1 = 5 ;
.equ AMP1IS = 6 ;
.equ AMP1EN = 7 ;
; ***** LINUART **********************
; LINCR - LIN Control Register
.equ LCMD0 = 0 ; LIN Command and Mode bit 0
.equ LCMD1 = 1 ; LIN Command and Mode bit 1
.equ LCMD2 = 2 ; LIN Command and Mode bit 2
.equ LENA = 3 ; LIN or UART Enable
.equ LCONF0 = 4 ; LIN Configuration bit 0
.equ LCONF1 = 5 ; LIN Configuration bit 1
.equ LIN13 = 6 ; LIN Standard
.equ LSWRES = 7 ; Software Reset
; LINSIR - LIN Status and Interrupt Register
.equ LRXOK = 0 ; Receive Performed Interrupt
.equ LTXOK = 1 ; Transmit Performed Interrupt
.equ LIDOK = 2 ; Identifier Interrupt
.equ LERR = 3 ; Error Interrupt
.equ LBUSY = 4 ; Busy Signal
.equ LIDST0 = 5 ; Identifier Status bit 0
.equ LIDST1 = 6 ; Identifier Status bit 1
.equ LIDST2 = 7 ; Identifier Status bit 2
; LINENIR - LIN Enable Interrupt Register
.equ LENRXOK = 0 ; Enable Receive Performed Interrupt
.equ LENTXOK = 1 ; Enable Transmit Performed Interrupt
.equ LENIDOK = 2 ; Enable Identifier Interrupt
.equ LENERR = 3 ; Enable Error Interrupt
; LINERR - LIN Error Register
.equ LBERR = 0 ; Bit Error Flag
.equ LCERR = 1 ; Checksum Error Flag
.equ LPERR = 2 ; Parity Error Flag
.equ LSERR = 3 ; Synchronization Error Flag
.equ LFERR = 4 ; Framing Error Flag
.equ LOVERR = 5 ; Overrun Error Flag
.equ LTOERR = 6 ; Frame Time Out Error Flag
.equ LABORT = 7 ; Abort Flag
; LINBTR - LIN Bit Timing Register
.equ LBT0 = 0 ; LIN Bit Timing bit 0
.equ LBT1 = 1 ; LIN Bit Timing bit 1
.equ LBT2 = 2 ; LIN Bit Timing bit 2
.equ LBT3 = 3 ; LIN Bit Timing bit 3
.equ LBT4 = 4 ; LIN Bit Timing bit 4
.equ LBT5 = 5 ; LIN Bit Timing bit 5
.equ LDISR = 7 ; Disable Bit Timing Resynchronization
; LINBRRL - LIN Baud Rate Low Register
.equ LDIV0 = 0 ;
.equ LDIV1 = 1 ;
.equ LDIV2 = 2 ;
.equ LDIV3 = 3 ;
.equ LDIV4 = 4 ;
.equ LDIV5 = 5 ;
.equ LDIV6 = 6 ;
.equ LDIV7 = 7 ;
; LINBRRH - LIN Baud Rate High Register
.equ LDIV8 = 0 ;
.equ LDIV9 = 1 ;
.equ LDIV10 = 2 ;
.equ LDIV11 = 3 ;
; LINDLR - LIN Data Length Register
.equ LRXDL0 = 0 ; LIN Receive Data Length bit 0
.equ LRXDL1 = 1 ; LIN Receive Data Length bit 1
.equ LRXDL2 = 2 ; LIN Receive Data Length bit 2
.equ LRXDL3 = 3 ; LIN Receive Data Length bit 3
.equ LTXDL0 = 4 ; LIN Transmit Data Length bit 0
.equ LTXDL1 = 5 ; LIN Transmit Data Length bit 1
.equ LTXDL2 = 6 ; LIN Transmit Data Length bit 2
.equ LTXDL3 = 7 ; LIN Transmit Data Length bit 3
; LINIDR - LIN Identifier Register
.equ LID0 = 0 ; Identifier bit 0
.equ LID1 = 1 ; Identifier bit 1
.equ LID2 = 2 ; Identifier bit 2
.equ LID3 = 3 ; Identifier bit 3
.equ LID4 = 4 ; Identifier bit 4 or Data Length bit 0
.equ LID5 = 5 ; Identifier bit 5 or Data Length bit 1
.equ LP0 = 6 ; Parity bit 0
.equ LP1 = 7 ; Parity bit 1
; LINSEL - LIN Data Buffer Selection Register
.equ LINDX0 = 0 ; FIFO LIN Data Buffer Index bit 0
.equ LINDX1 = 1 ; FIFO LIN Data Buffer Index bit 1
.equ LINDX2 = 2 ; FIFO LIN Data Buffer Index bit 2
.equ LAINC = 3 ; Auto Increment of Data Buffer Index (Active Low)
; LINDAT - LIN Data Register
.equ LDATA0 = 0 ;
.equ LDATA1 = 1 ;
.equ LDATA2 = 2 ;
.equ LDATA3 = 3 ;
.equ LDATA4 = 4 ;
.equ LDATA5 = 5 ;
.equ LDATA6 = 6 ;
.equ LDATA7 = 7 ;
; ***** SPI **************************
; SPDR - SPI Data Register
.equ SPDR0 = 0 ; SPI Data Register bit 0
.equ SPDR1 = 1 ; SPI Data Register bit 1
.equ SPDR2 = 2 ; SPI Data Register bit 2
.equ SPDR3 = 3 ; SPI Data Register bit 3
.equ SPDR4 = 4 ; SPI Data Register bit 4
.equ SPDR5 = 5 ; SPI Data Register bit 5
.equ SPDR6 = 6 ; SPI Data Register bit 6
.equ SPDR7 = 7 ; SPI Data Register bit 7
; SPSR - SPI Status Register
.equ SPI2X = 0 ; Double SPI Speed Bit
.equ WCOL = 6 ; Write Collision Flag
.equ SPIF = 7 ; SPI Interrupt Flag
; SPCR - SPI Control Register
.equ SPR0 = 0 ; SPI Clock Rate Select 0
.equ SPR1 = 1 ; SPI Clock Rate Select 1
.equ CPHA = 2 ; Clock Phase
.equ CPOL = 3 ; Clock polarity
.equ MSTR = 4 ; Master/Slave Select
.equ DORD = 5 ; Data Order
.equ SPE = 6 ; SPI Enable
.equ SPIE = 7 ; SPI Interrupt Enable
; ***** WATCHDOG *********************
; WDTCSR - Watchdog Timer Control Register
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
.equ WDE = 3 ; Watch Dog Enable
.equ WDCE = 4 ; Watchdog Change Enable
.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3
.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable
.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag
; ***** EXTERNAL_INTERRUPT ***********
; EICRA - External Interrupt Control Register A
.equ ISC00 = 0 ; External Interrupt Sense Control Bit
.equ ISC01 = 1 ; External Interrupt Sense Control Bit
.equ ISC10 = 2 ; External Interrupt Sense Control Bit
.equ ISC11 = 3 ; External Interrupt Sense Control Bit
.equ ISC20 = 4 ; External Interrupt Sense Control Bit
.equ ISC21 = 5 ; External Interrupt Sense Control Bit
.equ ISC30 = 6 ; External Interrupt Sense Control Bit
.equ ISC31 = 7 ; External Interrupt Sense Control Bit
; EIMSK - External Interrupt Mask Register
.equ INT0 = 0 ; External Interrupt Request 0 Enable
.equ INT1 = 1 ; External Interrupt Request 1 Enable
.equ INT2 = 2 ; External Interrupt Request 2 Enable
.equ INT3 = 3 ; External Interrupt Request 3 Enable
; EIFR - External Interrupt Flag Register
.equ INTF0 = 0 ; External Interrupt Flag 0
.equ INTF1 = 1 ; External Interrupt Flag 1
.equ INTF2 = 2 ; External Interrupt Flag 2
.equ INTF3 = 3 ; External Interrupt Flag 3
; ***** EEPROM ***********************
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