📄 pwm2def.inc
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; ***** PSC2 *************************
; PICR2H - PSC 2 Input Capture Register High
.equ PICR2_8 = 0 ;
.equ PICR2_9 = 1 ;
.equ PICR2_10 = 2 ;
.equ PICR2_11 = 3 ;
; PICR2L - PSC 2 Input Capture Register Low
.equ PICR2_0 = 0 ;
.equ PICR2_1 = 1 ;
.equ PICR2_2 = 2 ;
.equ PICR2_3 = 3 ;
.equ PICR2_4 = 4 ;
.equ PICR2_5 = 5 ;
.equ PICR2_6 = 6 ;
.equ PICR2_7 = 7 ;
; PFRC2B - PSC 2 Input B Control
.equ PRFM2B0 = 0 ; PSC 2 Retrigger and Fault Mode for Part B
.equ PRFM2B1 = 1 ; PSC 2 Retrigger and Fault Mode for Part B
.equ PRFM2B2 = 2 ; PSC 2 Retrigger and Fault Mode for Part B
.equ PRFM2B3 = 3 ; PSC 2 Retrigger and Fault Mode for Part B
.equ PFLTE2B = 4 ; PSC 2 Filter Enable on Input Part B
.equ PELEV2B = 5 ; PSC 2 Edge Level Selector on Input Part B
.equ PISEL2B = 6 ; PSC 2 Input Select for Part B
.equ PCAE2B = 7 ; PSC 2 Capture Enable Input Part B
; PFRC2A - PSC 2 Input B Control
.equ PRFM2A0 = 0 ; PSC 2 Retrigger and Fault Mode for Part A
.equ PRFM2A1 = 1 ; PSC 2 Retrigger and Fault Mode for Part A
.equ PRFM2A2 = 2 ; PSC 2 Retrigger and Fault Mode for Part A
.equ PRFM2A3 = 3 ; PSC 2 Retrigger and Fault Mode for Part A
.equ PFLTE2A = 4 ; PSC 2 Filter Enable on Input Part A
.equ PELEV2A = 5 ; PSC 2 Edge Level Selector on Input Part A
.equ PISEL2A = 6 ; PSC 2 Input Select for Part A
.equ PCAE2A = 7 ; PSC 2 Capture Enable Input Part A
; PCTL2 - PSC 2 Control Register
.equ PRUN2 = 0 ; PSC 2 Run
.equ PCCYC2 = 1 ; PSC2 Complete Cycle
.equ PARUN2 = 2 ; PSC2 Auto Run
.equ PAOC2A = 3 ; PSC 2 Asynchronous Output Control A
.equ PAOC2B = 4 ; PSC 2 Asynchronous Output Control B
.equ PBFM2 = 5 ; Balance Flank Width Modulation
.equ PPRE20 = 6 ; PSC 2 Prescaler Select 0
.equ PPRE21 = 7 ; PSC 2 Prescaler Select 1
; PCNF2 - PSC 2 Configuration Register
.equ POME2 = 0 ; PSC 2 Output Matrix Enable
.equ PCLKSEL2 = 1 ; PSC 2 Input Clock Select
.equ POP2 = 2 ; PSC 2 Output Polarity
.equ PMODE20 = 3 ; PSC 2 Mode
.equ PMODE21 = 4 ; PSC 2 Mode
.equ PLOCK2 = 5 ; PSC 2 Lock
.equ PALOCK2 = 6 ; PSC 2 Autolock
.equ PFIFTY2 = 7 ; PSC 2 Fifty
; OCR2RBH - Output Compare RB Register High
.equ OCR2RB_8 = 0 ;
.equ OCR2RB_9 = 1 ;
.equ OCR2RB_10 = 2 ;
.equ OCR2RB_11 = 3 ;
.equ OCR2RB_12 = 4 ;
.equ OCR2RB_13 = 5 ;
.equ OCR2RB_14 = 6 ;
.equ OCR2RB_15 = 7 ;
; OCR2RBL - Output Compare RB Register Low
.equ OCR2RB_0 = 0 ;
.equ OCR2RB_1 = 1 ;
.equ OCR2RB_2 = 2 ;
.equ OCR2RB_3 = 3 ;
.equ OCR2RB_4 = 4 ;
.equ OCR2RB_5 = 5 ;
.equ OCR2RB_6 = 6 ;
.equ OCR2RB_7 = 7 ;
; OCR2SBH - Output Compare SB Register High
.equ OCR2SB_8 = 0 ;
.equ OCR2SB_9 = 1 ;
.equ OCR2SB_10 = 2 ;
.equ OCR2SB_11 = 3 ;
; OCR2SBL - Output Compare SB Register Low
.equ OCR2SB_0 = 0 ;
.equ OCR2SB_1 = 1 ;
.equ OCR2SB_2 = 2 ;
.equ OCR2SB_3 = 3 ;
.equ OCR2SB_4 = 4 ;
.equ OCR2SB_5 = 5 ;
.equ OCR2SB_6 = 6 ;
.equ OCR2SB_7 = 7 ;
; OCR2RAH - Output Compare RA Register High
.equ OCR2RA_8 = 0 ;
.equ OCR2RA_9 = 1 ;
.equ OCR2RA_10 = 2 ;
.equ OCR2RA_11 = 3 ;
; OCR2RAL - Output Compare RA Register Low
.equ OCR2RA_0 = 0 ;
.equ OCR2RA_1 = 1 ;
.equ OCR2RA_2 = 2 ;
.equ OCR2RA_3 = 3 ;
.equ OCR2RA_4 = 4 ;
.equ OCR2RA_5 = 5 ;
.equ OCR2RA_6 = 6 ;
.equ OCR2RA_7 = 7 ;
; OCR2SAH - Output Compare SA Register High
.equ OCR2SA_8 = 0 ;
.equ OCR2SA_9 = 1 ;
.equ OCR2SA_10 = 2 ;
.equ OCR2SA_11 = 3 ;
; OCR2SAL - Output Compare SA Register Low
.equ OCR2SA_0 = 0 ;
.equ OCR2SA_1 = 1 ;
.equ OCR2SA_2 = 2 ;
.equ OCR2SA_3 = 3 ;
.equ OCR2SA_4 = 4 ;
.equ OCR2SA_5 = 5 ;
.equ OCR2SA_6 = 6 ;
.equ OCR2SA_7 = 7 ;
; POM2 - PSC 2 Output Matrix
.equ POMV2A0 = 0 ; Output Matrix Output A Ramp 0
.equ POMV2A1 = 1 ; Output Matrix Output A Ramp 1
.equ POMV2A2 = 2 ; Output Matrix Output A Ramp 2
.equ POMV2A3 = 3 ; Output Matrix Output A Ramp 3
.equ POMV2B0 = 4 ; Output Matrix Output B Ramp 0
.equ POMV2B1 = 5 ; Output Matrix Output B Ramp 2
.equ POMV2B2 = 6 ; Output Matrix Output B Ramp 2
.equ POMV2B3 = 7 ; Output Matrix Output B Ramp 3
; PSOC2 - PSC2 Synchro and Output Configuration
.equ POEN2A = 0 ; PSCOUT20 Output Enable
.equ POEN2C = 1 ; PSCOUT22 Output Enable
.equ POEN2B = 2 ; PSCOUT21 Output Enable
.equ POEN2D = 3 ; PSCOUT23 Output Enable
.equ PSYNC2_0 = 4 ; Synchronization Out for ADC Selection
.equ PSYNC2_1 = 5 ; Synchronization Out for ADC Selection
.equ POS22 = 6 ; PSC 2 Output 22 Select
.equ POS23 = 7 ; PSC 2 Output 23 Select
; PIM2 - PSC2 Interrupt Mask Register
.equ PEOPE2 = 0 ; End of Cycle Interrupt Enable
.equ PEVE2A = 3 ; External Event A Interrupt Enable
.equ PEVE2B = 4 ; External Event B Interrupt Enable
.equ PSEIE2 = 5 ; PSC 2 Synchro Error Interrupt Enable
; PIFR2 - PSC2 Interrupt Flag Register
.equ PEOP2 = 0 ; End of PSC2 Interrupt
.equ PRN20 = 1 ; Ramp Number
.equ PRN21 = 2 ; Ramp Number
.equ PEV2A = 3 ; External Event A Interrupt
.equ PEV2B = 4 ; External Event B Interrupt
.equ PSEI2 = 5 ; PSC 2 Synchro Error Interrupt
; ***** EUSART ***********************
; EUDR - EUSART I/O Data Register
.equ EUDR0 = 0 ; EUSART I/O Data Register bit 0
.equ EUDR1 = 1 ; EUSART I/O Data Register bit 1
.equ EUDR2 = 2 ; EUSART I/O Data Register bit 2
.equ EUDR3 = 3 ; EUSART I/O Data Register bit 3
.equ EUDR4 = 4 ; EUSART I/O Data Register bit 4
.equ EUDR5 = 5 ; EUSART I/O Data Register bit 5
.equ EUDR6 = 6 ; EUSART I/O Data Register bit 6
.equ EUDR7 = 7 ; EUSART I/O Data Register bit 7
; EUCSRA - EUSART Control and Status Register A
.equ URxS0 = 0 ; EUSART Control and Status Register A Bit 0
.equ URxS1 = 1 ; EUSART Control and Status Register A Bit 1
.equ URxS2 = 2 ; EUSART Control and Status Register A Bit 2
.equ URxS3 = 3 ; EUSART Control and Status Register A Bit 3
.equ UTxS0 = 4 ; EUSART Control and Status Register A Bit 4
.equ UTxS1 = 5 ; EUSART Control and Status Register A Bit 5
.equ UTxS2 = 6 ; EUSART Control and Status Register A Bit 6
.equ UTxS3 = 7 ; EUSART Control and Status Register A Bit 7
; EUCSRB - EUSART Control Register B
.equ BODR = 0 ; Order Bit
.equ EMCH = 1 ; Manchester Mode Bit
.equ EUSBS = 3 ; EUSBS Enable Bit
.equ EUSART = 4 ; EUSART Enable Bit
; EUCSRC - EUSART Status Register C
.equ STP0 = 0 ; Stop Bit 0
.equ STP1 = 1 ; Stop Bit 1
.equ F1617 = 2 ; F1617 Bit
.equ FEM = 3 ; Frame Error Manchester Bit
; MUBRRH - Manchester Receiver Baud Rate Register High Byte
.equ MUBRR8 = 0 ; Manchester Receiver Baud Rate Register Bit 8
.equ MUBRR9 = 1 ; Manchester Receiver Baud Rate Register Bit 9
.equ MUBRR10 = 2 ; Manchester Receiver Baud Rate Register Bit 10
.equ MUBRR11 = 3 ; Manchester Receiver Baud Rate Register Bit 11
.equ MUBRR12 = 4 ; Manchester Receiver Baud Rate Register Bit 12
.equ MUBRR13 = 5 ; Manchester Receiver Baud Rate Register Bit 13
.equ MUBRR14 = 6 ; Manchester Receiver Baud Rate Register Bit 14
.equ MUBRR15 = 7 ; Manchester Receiver Baud Rate Register Bit 15
; MUBRRL - Manchester Receiver Baud Rate Register Low Byte
.equ MUBRR0 = 0 ; Manchester Receiver Baud Rate Register Bit 0
.equ MUBRR1 = 1 ; Manchester Receiver Baud Rate Register Bit 1
.equ MUBRR2 = 2 ; Manchester Receiver Baud Rate Register Bit 2
.equ MUBRR3 = 3 ; Manchester Receiver Baud Rate Register Bit 3
.equ MUBRR4 = 4 ; Manchester Receiver Baud Rate Register Bit 4
.equ MUBRR5 = 5 ; Manchester Receiver Baud Rate Register Bit 5
.equ MUBRR6 = 6 ; Manchester Receiver Baud Rate Register Bit 6
.equ MUBRR7 = 7 ; Manchester Receiver Baud Rate Register Bit 7
; ***** ANALOG_COMPARATOR ************
; AC0CON - Analog Comparator 0 Control Register
.equ AC0M0 = 0 ; Analog Comparator 0 Multiplexer Register
.equ AC0M1 = 1 ; Analog Comparator 0 Multiplexer Regsiter
.equ AC0M2 = 2 ; Analog Comparator 0 Multiplexer Register
.equ AC0IS0 = 4 ; Analog Comparator 0 Interrupt Select Bit
.equ AC0IS1 = 5 ; Analog Comparator 0 Interrupt Select Bit
.equ AC0IE = 6 ; Analog Comparator 0 Interrupt Enable Bit
.equ AC0EN = 7 ; Analog Comparator 0 Enable Bit
; AC1CON - Analog Comparator 1 Control Register
.equ AC1M0 = 0 ; Analog Comparator 1 Multiplexer Register
.equ AC1M1 = 1 ; Analog Comparator 1 Multiplexer Regsiter
.equ AC1M2 = 2 ; Analog Comparator 1 Multiplexer Register
.equ AC1ICE = 3 ; Analog Comparator 1 Interrupt Capture Enable Bit
.equ AC1IS0 = 4 ; Analog Comparator 1 Interrupt Select Bit
.equ AC1IS1 = 5 ; Analog Comparator 1 Interrupt Select Bit
.equ AC1IE = 6 ; Analog Comparator 1 Interrupt Enable Bit
.equ AC1EN = 7 ; Analog Comparator 1 Enable Bit
; AC2CON - Analog Comparator 2 Control Register
.equ AC2M0 = 0 ; Analog Comparator 2 Multiplexer Register
.equ AC2M1 = 1 ; Analog Comparator 2 Multiplexer Regsiter
.equ AC2M2 = 2 ; Analog Comparator 2 Multiplexer Register
.equ AC2IS0 = 4 ; Analog Comparator 2 Interrupt Select Bit
.equ AC2IS1 = 5 ; Analog Comparator 2 Interrupt Select Bit
.equ AC2IE = 6 ; Analog Comparator 2 Interrupt Enable Bit
.equ AC2EN = 7 ; Analog Comparator 2 Enable Bit
; ACSR - Analog Comparator Status Register
.equ AC0O = 0 ; Analog Comparator 0 Output Bit
.equ AC1O = 1 ; Analog Comparator 1 Output Bit
.equ AC2O = 2 ; Analog Comparator 2 Output Bit
.equ AC0IF = 4 ; Analog Comparator 0 Interrupt Flag Bit
.equ AC1IF = 5 ; Analog Comparator 1 Interrupt Flag Bit
.equ AC2IF = 6 ; Analog Comparator 2 Interrupt Flag Bit
.equ ACCKDIV = 7 ; Analog Comparator Clock Divider
; ***** DA_CONVERTER *****************
; DACH - DAC Data Register High Byte
.equ DACH0 = 0 ; DAC Data Register High Byte Bit 0
.equ DACH1 = 1 ; DAC Data Register High Byte Bit 1
.equ DACH2 = 2 ; DAC Data Register High Byte Bit 2
.equ DACH3 = 3 ; DAC Data Register High Byte Bit 3
.equ DACH4 = 4 ; DAC Data Register High Byte Bit 4
.equ DACH5 = 5 ; DAC Data Register High Byte Bit 5
.equ DACH6 = 6 ; DAC Data Register High Byte Bit 6
.equ DACH7 = 7 ; DAC Data Register High Byte Bit 7
; DACL - DAC Data Register Low Byte
.equ DACL0 = 0 ; DAC Data Register Low Byte Bit 0
.equ DACL1 = 1 ; DAC Data Register Low Byte Bit 1
.equ DACL2 = 2 ; DAC Data Register Low Byte Bit 2
.equ DACL3 = 3 ; DAC Data Register Low Byte Bit 3
.equ DACL4 = 4 ; DAC Data Register Low Byte Bit 4
.equ DACL5 = 5 ; DAC Data Register Low Byte Bit 5
.equ DACL6 = 6 ; DAC Data Register Low Byte Bit 6
.equ DACL7 = 7 ; DAC Data Register Low Byte Bit 7
; DACON - DAC Control Register
.equ DAEN = 0 ; DAC Enable Bit
.equ DAOE = 1 ; DAC Output Enable Bit
.equ DALA = 2 ; DAC Left Adjust
.equ DATS0 = 4 ; DAC Trigger Selection Bit 0
.equ DATS1 = 5 ; DAC Trigger Selection Bit 1
.equ DATS2 = 6 ; DAC Trigger Selection Bit 2
.equ DAATE = 7 ; DAC Auto Trigger Enable Bit
; ***** CPU **************************
; SREG - Status Register
.equ SREG_C = 0 ; Carry Flag
.equ SREG_Z = 1 ; Zero Flag
.equ SREG_N = 2 ; Negative Flag
.equ SREG_V = 3 ; Two's Complement Overflow Flag
.equ SREG_S = 4 ; Sign Bit
.equ SREG_H = 5 ; Half Carry Flag
.equ SREG_T = 6 ; Bit Copy Storage
.equ SREG_I = 7 ; Global Interrupt Enable
; MCUCR - MCU Control Register
.equ IVCE = 0 ; Interrupt Vector Change Enable
.equ IVSEL = 1 ; Interrupt Vector Select
.equ PUD = 4 ; Pull-up disable
.equ SPIPS = 7 ; SPI Pin Select
; MCUSR - MCU Status Register
.equ PORF = 0 ; Power-on reset flag
.equ EXTRF = 1 ; External Reset Flag
.equ BORF = 2 ; Brown-out Reset Flag
.equ WDRF = 3 ; Watchdog Reset Flag
; OSCCAL - Oscillator Calibration Value
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6
; CLKPR -
.equ CLKPS0 = 0 ;
.equ CLKPS1 = 1 ;
.equ CLKPS2 = 2 ;
.equ CLKPS3 = 3 ;
.equ CLKPCE = 7 ;
; SMCR - Sleep Mode Control Register
.equ SE = 0 ; Sleep Enable
.equ SM0 = 1 ; Sleep Mode Select bit 0
.equ SM1 = 2 ; Sleep Mode Select bit 1
.equ SM2 = 3 ; Sleep Mode Select bit 2
; GPIOR3 - General Purpose IO Register 3
.equ GPIOR30 = 0 ; General Purpose IO Register 3 bit 0
.equ GPIOR31 = 1 ; General Purpose IO Register 3 bit 1
.equ GPIOR32 = 2 ; General Purpose IO Register 3 bit 2
.equ GPIOR33 = 3 ; General Purpose IO Register 3 bit 3
.equ GPIOR34 = 4 ; General Purpose IO Register 3 bit 4
.equ GPIOR35 = 5 ; General Purpose IO Register 3 bit 5
.equ GPIOR36 = 6 ; General Purpose IO Register 3 bit 6
.equ GPIOR37 = 7 ; General Purpose IO Register 3 bit 7
; GPIOR2 - General Purpose IO Register 2
.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0
.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1
.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2
.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3
.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4
.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5
.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6
.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7
; GPIOR1 - General Purpose IO Register 1
.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0
.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1
.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2
.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3
.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4
.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5
.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6
.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7
; GPIOR0 - General Purpose IO Register 0
.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0
.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1
.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2
.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3
.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4
.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5
.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6
.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7
; PLLCSR - PLL Control And Status Register
.equ PLOCK = 0 ; PLL Lock Detector
.equ PLLE = 1 ; PLL Enable
.equ PLLF = 2 ; PLL Factor
; PRR - Power Reduction Register
.equ PRADC = 0 ; Power Reduction ADC
.equ PRUSART0 = 1 ; Power Reduction USART
.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface
.equ PRTIM0 = 3 ; Power Reduction Timer/Counter0
.equ PRTIM1 = 4 ; Power Reduction Timer/Counter1
.equ PRPSC0 = 5 ; Power Reduction PSC0
.equ PRPSC1 = 6 ; Power Reduction PSC1
.equ PRPSC2 = 7 ; Power Reduction PSC2
; ***** PORTE ************************
; PORTE - Port E Data Register
.equ PORTE0 = 0 ;
.equ PE0 = 0 ; For compatibility
.equ PORTE1 = 1 ;
.equ PE1 = 1 ; For compatibility
.equ PORTE2 = 2 ;
.equ PE2 = 2 ; For compatibility
; DDRE - Port E Data Direction Register
.equ DDE0 = 0 ;
.equ DDE1 = 1 ;
.equ DDE2 = 2 ;
; PINE - Port E Input Pins
.equ PINE0 = 0 ;
.equ PINE1 = 1 ;
.equ PINE2 = 2 ;
; ***** TIMER_COUNTER_0 **************
; TIMSK0 - Timer/Counter0 Interrupt Mask Register
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable
.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable
; TIFR0 - Timer/Counter0 Interrupt Flag register
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0A
.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B
; TCCR0A - Timer/Counter Control Register A
.equ WGM00 = 0 ; Waveform Generation Mode
.equ WGM01 = 1 ; Waveform Generation Mode
.equ COM0B0 = 4 ; Compare Output Mode, Fast PWm
.equ COM0B1 = 5 ; Compare Output Mode, Fast PWm
.equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode
.equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode
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