📄 pwm2def.inc
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;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
;***** Created: 2007-12-13 07:27 ******* Source: AT90PWM2.xml ************
;*************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number : AVR000
;* File Name : "pwm2def.inc"
;* Title : Register/Bit Definitions for the AT90PWM2
;* Date : 2007-12-13
;* Version : 2.24
;* Support E-mail : avr@atmel.com
;* Target MCU : AT90PWM2
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;* The Register names are represented by their hexadecimal address.
;*
;* The Register Bit names are represented by their bit number (0-7).
;*
;* Please observe the difference in using the bit names with instructions
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
;* (skip if bit in register set/cleared). The following example illustrates
;* this:
;*
;* in r16,PORTB ;read PORTB latch
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
;* out PORTB,r16 ;output to PORTB
;*
;* in r16,TIFR ;read the Timer Interrupt Flag Register
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
;* rjmp TOV0_is_set ;jump if set
;* ... ;otherwise do something else
;*************************************************************************
#ifndef _PWM2DEF_INC_
#define _PWM2DEF_INC_
#pragma partinc 0
; ***** SPECIFY DEVICE ***************************************************
.device AT90PWM2
#pragma AVRPART ADMIN PART_NAME AT90PWM2
.equ SIGNATURE_000 = 0x1e
.equ SIGNATURE_001 = 0x93
.equ SIGNATURE_002 = 0x81
#pragma AVRPART CORE CORE_VERSION V2E
; ***** I/O REGISTER DEFINITIONS *****************************************
; NOTE:
; Definitions marked "MEMORY MAPPED"are extended I/O ports
; and cannot be used with IN/OUT instructions
.equ PICR2H = 0xff ; MEMORY MAPPED
.equ PICR2L = 0xfe ; MEMORY MAPPED
.equ PFRC2B = 0xfd ; MEMORY MAPPED
.equ PFRC2A = 0xfc ; MEMORY MAPPED
.equ PCTL2 = 0xfb ; MEMORY MAPPED
.equ PCNF2 = 0xfa ; MEMORY MAPPED
.equ OCR2RBH = 0xf9 ; MEMORY MAPPED
.equ OCR2RBL = 0xf8 ; MEMORY MAPPED
.equ OCR2SBH = 0xf7 ; MEMORY MAPPED
.equ OCR2SBL = 0xf6 ; MEMORY MAPPED
.equ OCR2RAH = 0xf5 ; MEMORY MAPPED
.equ OCR2RAL = 0xf4 ; MEMORY MAPPED
.equ OCR2SAH = 0xf3 ; MEMORY MAPPED
.equ OCR2SAL = 0xf2 ; MEMORY MAPPED
.equ POM2 = 0xf1 ; MEMORY MAPPED
.equ PSOC2 = 0xf0 ; MEMORY MAPPED
.equ PICR0H = 0xdf ; MEMORY MAPPED
.equ PICR0L = 0xde ; MEMORY MAPPED
.equ PFRC0B = 0xdd ; MEMORY MAPPED
.equ PFRC0A = 0xdc ; MEMORY MAPPED
.equ PCTL0 = 0xdb ; MEMORY MAPPED
.equ PCNF0 = 0xda ; MEMORY MAPPED
.equ OCR0RBH = 0xd9 ; MEMORY MAPPED
.equ OCR0RBL = 0xd8 ; MEMORY MAPPED
.equ OCR0SBH = 0xd7 ; MEMORY MAPPED
.equ OCR0SBL = 0xd6 ; MEMORY MAPPED
.equ OCR0RAH = 0xd5 ; MEMORY MAPPED
.equ OCR0RAL = 0xd4 ; MEMORY MAPPED
.equ OCR0SAH = 0xd3 ; MEMORY MAPPED
.equ OCR0SAL = 0xd2 ; MEMORY MAPPED
.equ PSOC0 = 0xd0 ; MEMORY MAPPED
.equ EUDR = 0xce ; MEMORY MAPPED
.equ MUBRRL = 0xcc ; MEMORY MAPPED
.equ MUBRRH = 0xcd ; MEMORY MAPPED
.equ EUCSRC = 0xca ; MEMORY MAPPED
.equ EUCSRB = 0xc9 ; MEMORY MAPPED
.equ EUCSRA = 0xc8 ; MEMORY MAPPED
.equ UDR = 0xc6 ; MEMORY MAPPED
.equ UBRRH = 0xc5 ; MEMORY MAPPED
.equ UBRRL = 0xc4 ; MEMORY MAPPED
.equ UCSRC = 0xc2 ; MEMORY MAPPED
.equ UCSRB = 0xc1 ; MEMORY MAPPED
.equ UCSRA = 0xc0 ; MEMORY MAPPED
.equ AC2CON = 0xaf ; MEMORY MAPPED
.equ AC1CON = 0xae ; MEMORY MAPPED
.equ AC0CON = 0xad ; MEMORY MAPPED
.equ DACH = 0xac ; MEMORY MAPPED
.equ DACL = 0xab ; MEMORY MAPPED
.equ DACON = 0xaa ; MEMORY MAPPED
.equ PIM2 = 0xa5 ; MEMORY MAPPED
.equ PIFR2 = 0xa4 ; MEMORY MAPPED
.equ PIM1 = 0xa3 ; MEMORY MAPPED
.equ PIFR1 = 0xa2 ; MEMORY MAPPED
.equ PIM0 = 0xa1 ; MEMORY MAPPED
.equ PIFR0 = 0xa0 ; MEMORY MAPPED
.equ OCR1BL = 0x8a ; MEMORY MAPPED
.equ OCR1BH = 0x8b ; MEMORY MAPPED
.equ OCR1AL = 0x88 ; MEMORY MAPPED
.equ OCR1AH = 0x89 ; MEMORY MAPPED
.equ ICR1L = 0x86 ; MEMORY MAPPED
.equ ICR1H = 0x87 ; MEMORY MAPPED
.equ TCNT1L = 0x84 ; MEMORY MAPPED
.equ TCNT1H = 0x85 ; MEMORY MAPPED
.equ TCCR1C = 0x82 ; MEMORY MAPPED
.equ TCCR1B = 0x81 ; MEMORY MAPPED
.equ TCCR1A = 0x80 ; MEMORY MAPPED
.equ DIDR1 = 0x7f ; MEMORY MAPPED
.equ DIDR0 = 0x7e ; MEMORY MAPPED
.equ ADMUX = 0x7c ; MEMORY MAPPED
.equ ADCSRB = 0x7b ; MEMORY MAPPED
.equ ADCSRA = 0x7a ; MEMORY MAPPED
.equ ADCH = 0x79 ; MEMORY MAPPED
.equ ADCL = 0x78 ; MEMORY MAPPED
.equ AMP1CSR = 0x77 ; MEMORY MAPPED
.equ AMP0CSR = 0x76 ; MEMORY MAPPED
.equ TIMSK1 = 0x6f ; MEMORY MAPPED
.equ TIMSK0 = 0x6e ; MEMORY MAPPED
.equ EICRA = 0x69 ; MEMORY MAPPED
.equ OSCCAL = 0x66 ; MEMORY MAPPED
.equ PRR = 0x64 ; MEMORY MAPPED
.equ CLKPR = 0x61 ; MEMORY MAPPED
.equ WDTCSR = 0x60 ; MEMORY MAPPED
.equ SREG = 0x3f
.equ SPL = 0x3d
.equ SPH = 0x3e
.equ SPMCSR = 0x37
.equ MCUCR = 0x35
.equ MCUSR = 0x34
.equ SMCR = 0x33
.equ ACSR = 0x30
.equ SPDR = 0x2e
.equ SPSR = 0x2d
.equ SPCR = 0x2c
.equ PLLCSR = 0x29
.equ OCR0B = 0x28
.equ OCR0A = 0x27
.equ TCNT0 = 0x26
.equ TCCR0B = 0x25
.equ TCCR0A = 0x24
.equ GTCCR = 0x23
.equ EEARL = 0x21
.equ EEARH = 0x22
.equ EEDR = 0x20
.equ EECR = 0x1f
.equ GPIOR0 = 0x1e
.equ EIMSK = 0x1d
.equ EIFR = 0x1c
.equ GPIOR3 = 0x1b
.equ GPIOR2 = 0x1a
.equ GPIOR1 = 0x19
.equ TIFR1 = 0x16
.equ TIFR0 = 0x15
.equ PORTE = 0x0e
.equ DDRE = 0x0d
.equ PINE = 0x0c
.equ PORTD = 0x0b
.equ DDRD = 0x0a
.equ PIND = 0x09
.equ PORTC = 0x08
.equ DDRC = 0x07
.equ PINC = 0x06
.equ PORTB = 0x05
.equ DDRB = 0x04
.equ PINB = 0x03
; ***** BIT DEFINITIONS **************************************************
; ***** PORTB ************************
; PORTB - Port B Data Register
.equ PORTB0 = 0 ; Port B Data Register bit 0
.equ PB0 = 0 ; For compatibility
.equ PORTB1 = 1 ; Port B Data Register bit 1
.equ PB1 = 1 ; For compatibility
.equ PORTB2 = 2 ; Port B Data Register bit 2
.equ PB2 = 2 ; For compatibility
.equ PORTB3 = 3 ; Port B Data Register bit 3
.equ PB3 = 3 ; For compatibility
.equ PORTB4 = 4 ; Port B Data Register bit 4
.equ PB4 = 4 ; For compatibility
.equ PORTB5 = 5 ; Port B Data Register bit 5
.equ PB5 = 5 ; For compatibility
.equ PORTB6 = 6 ; Port B Data Register bit 6
.equ PB6 = 6 ; For compatibility
.equ PORTB7 = 7 ; Port B Data Register bit 7
.equ PB7 = 7 ; For compatibility
; DDRB - Port B Data Direction Register
.equ DDB0 = 0 ; Port B Data Direction Register bit 0
.equ DDB1 = 1 ; Port B Data Direction Register bit 1
.equ DDB2 = 2 ; Port B Data Direction Register bit 2
.equ DDB3 = 3 ; Port B Data Direction Register bit 3
.equ DDB4 = 4 ; Port B Data Direction Register bit 4
.equ DDB5 = 5 ; Port B Data Direction Register bit 5
.equ DDB6 = 6 ; Port B Data Direction Register bit 6
.equ DDB7 = 7 ; Port B Data Direction Register bit 7
; PINB - Port B Input Pins
.equ PINB0 = 0 ; Port B Input Pins bit 0
.equ PINB1 = 1 ; Port B Input Pins bit 1
.equ PINB2 = 2 ; Port B Input Pins bit 2
.equ PINB3 = 3 ; Port B Input Pins bit 3
.equ PINB4 = 4 ; Port B Input Pins bit 4
.equ PINB5 = 5 ; Port B Input Pins bit 5
.equ PINB6 = 6 ; Port B Input Pins bit 6
.equ PINB7 = 7 ; Port B Input Pins bit 7
; ***** PORTD ************************
; PORTD - Port D Data Register
.equ PORTD0 = 0 ; Port D Data Register bit 0
.equ PD0 = 0 ; For compatibility
.equ PORTD1 = 1 ; Port D Data Register bit 1
.equ PD1 = 1 ; For compatibility
.equ PORTD2 = 2 ; Port D Data Register bit 2
.equ PD2 = 2 ; For compatibility
.equ PORTD3 = 3 ; Port D Data Register bit 3
.equ PD3 = 3 ; For compatibility
.equ PORTD4 = 4 ; Port D Data Register bit 4
.equ PD4 = 4 ; For compatibility
.equ PORTD5 = 5 ; Port D Data Register bit 5
.equ PD5 = 5 ; For compatibility
.equ PORTD6 = 6 ; Port D Data Register bit 6
.equ PD6 = 6 ; For compatibility
.equ PORTD7 = 7 ; Port D Data Register bit 7
.equ PD7 = 7 ; For compatibility
; DDRD - Port D Data Direction Register
.equ DDD0 = 0 ; Port D Data Direction Register bit 0
.equ DDD1 = 1 ; Port D Data Direction Register bit 1
.equ DDD2 = 2 ; Port D Data Direction Register bit 2
.equ DDD3 = 3 ; Port D Data Direction Register bit 3
.equ DDD4 = 4 ; Port D Data Direction Register bit 4
.equ DDD5 = 5 ; Port D Data Direction Register bit 5
.equ DDD6 = 6 ; Port D Data Direction Register bit 6
.equ DDD7 = 7 ; Port D Data Direction Register bit 7
; PIND - Port D Input Pins
.equ PIND0 = 0 ; Port D Input Pins bit 0
.equ PIND1 = 1 ; Port D Input Pins bit 1
.equ PIND2 = 2 ; Port D Input Pins bit 2
.equ PIND3 = 3 ; Port D Input Pins bit 3
.equ PIND4 = 4 ; Port D Input Pins bit 4
.equ PIND5 = 5 ; Port D Input Pins bit 5
.equ PIND6 = 6 ; Port D Input Pins bit 6
.equ PIND7 = 7 ; Port D Input Pins bit 7
; ***** BOOT_LOAD ********************
; SPMCSR - Store Program Memory Control Register
.equ SPMCR = SPMCSR ; For compatibility
.equ SPMEN = 0 ; Store Program Memory Enable
.equ PGERS = 1 ; Page Erase
.equ PGWRT = 2 ; Page Write
.equ BLBSET = 3 ; Boot Lock Bit Set
.equ RWWSRE = 4 ; Read While Write section read enable
.equ ASRE = RWWSRE ; For compatibility
.equ RWWSB = 6 ; Read While Write Section Busy
.equ ASB = RWWSB ; For compatibility
.equ SPMIE = 7 ; SPM Interrupt Enable
; ***** PSC0 *************************
; PICR0H - PSC 0 Input Capture Register High
.equ PICR0_8 = 0 ;
.equ PICR0_9 = 1 ;
.equ PICR0_10 = 2 ;
.equ PICR0_11 = 3 ;
; PICR0L - PSC 0 Input Capture Register Low
.equ PICR0_0 = 0 ;
.equ PICR0_1 = 1 ;
.equ PICR0_2 = 2 ;
.equ PICR0_3 = 3 ;
.equ PICR0_4 = 4 ;
.equ PICR0_5 = 5 ;
.equ PICR0_6 = 6 ;
.equ PICR0_7 = 7 ;
; PFRC0B - PSC 0 Input B Control
.equ PRFM0B0 = 0 ; PSC 0 Retrigger and Fault Mode for Part B
.equ PRFM0B1 = 1 ; PSC 0 Retrigger and Fault Mode for Part B
.equ PRFM0B2 = 2 ; PSC 0 Retrigger and Fault Mode for Part B
.equ PRFM0B3 = 3 ; PSC 0 Retrigger and Fault Mode for Part B
.equ PFLTE0B = 4 ; PSC 0 Filter Enable on Input Part B
.equ PELEV0B = 5 ; PSC 0 Edge Level Selector on Input Part B
.equ PISEL0B = 6 ; PSC 0 Input Select for Part B
.equ PCAE0B = 7 ; PSC 0 Capture Enable Input Part B
; PFRC0A - PSC 0 Input A Control
.equ PRFM0A0 = 0 ; PSC 0 Retrigger and Fault Mode for Part A
.equ PRFM0A1 = 1 ; PSC 0 Retrigger and Fault Mode for Part A
.equ PRFM0A2 = 2 ; PSC 0 Retrigger and Fault Mode for Part A
.equ PRFM0A3 = 3 ; PSC 0 Retrigger and Fault Mode for Part A
.equ PFLTE0A = 4 ; PSC 0 Filter Enable on Input Part A
.equ PELEV0A = 5 ; PSC 0 Edge Level Selector on Input Part A
.equ PISEL0A = 6 ; PSC 0 Input Select for Part A
.equ PCAE0A = 7 ; PSC 0 Capture Enable Input Part A
; PCTL0 - PSC 0 Control Register
.equ PRUN0 = 0 ; PSC 0 Run
.equ PCCYC0 = 1 ; PSC0 Complete Cycle
.equ PARUN0 = 2 ; PSC0 Auto Run
.equ PAOC0A = 3 ; PSC 0 Asynchronous Output Control A
.equ PAOC0B = 4 ; PSC 0 Asynchronous Output Control B
.equ PBFM0 = 5 ; PSC 0 Balance Flank Width Modulation
.equ PPRE00 = 6 ; PSC 0 Prescaler Select 0
.equ PPRE01 = 7 ; PSC 0 Prescaler Select 1
; PCNF0 - PSC 0 Configuration Register
.equ PCLKSEL0 = 1 ; PSC 0 Input Clock Select
.equ POP0 = 2 ; PSC 0 Output Polarity
.equ PMODE00 = 3 ; PSC 0 Mode
.equ PMODE01 = 4 ; PSC 0 Mode
.equ PLOCK0 = 5 ; PSC 0 Lock
.equ PALOCK0 = 6 ; PSC 0 Autolock
.equ PFIFTY0 = 7 ; PSC 0 Fifty
; OCR0RBH - Output Compare RB Register High
.equ OCR0RB_8 = 0 ;
.equ OCR0RB_9 = 1 ;
.equ OCR0RB_00 = 2 ;
.equ OCR0RB_01 = 3 ;
.equ OCR0RB_02 = 4 ;
.equ OCR0RB_03 = 5 ;
.equ OCR0RB_04 = 6 ;
.equ OCR0RB_05 = 7 ;
; OCR0RBL - Output Compare RB Register Low
.equ OCR0RB_0 = 0 ;
.equ OCR0RB_1 = 1 ;
.equ OCR0RB_2 = 2 ;
.equ OCR0RB_3 = 3 ;
.equ OCR0RB_4 = 4 ;
.equ OCR0RB_5 = 5 ;
.equ OCR0RB_6 = 6 ;
.equ OCR0RB_7 = 7 ;
; OCR0SBH - Output Compare SB Register High
.equ OCR0SB_8 = 0 ;
.equ OCR0SB_9 = 1 ;
.equ OCR0SB_00 = 2 ;
.equ OCR0SB_01 = 3 ;
; OCR0SBL - Output Compare SB Register Low
.equ OCR0SB_0 = 0 ;
.equ OCR0SB_1 = 1 ;
.equ OCR0SB_2 = 2 ;
.equ OCR0SB_3 = 3 ;
.equ OCR0SB_4 = 4 ;
.equ OCR0SB_5 = 5 ;
.equ OCR0SB_6 = 6 ;
.equ OCR0SB_7 = 7 ;
; OCR0RAH - Output Compare RA Register High
.equ OCR0RA_8 = 0 ;
.equ OCR0RA_9 = 1 ;
.equ OCR0RA_00 = 2 ;
.equ OCR0RA_01 = 3 ;
; OCR0RAL - Output Compare RA Register Low
.equ OCR0RA_0 = 0 ;
.equ OCR0RA_1 = 1 ;
.equ OCR0RA_2 = 2 ;
.equ OCR0RA_3 = 3 ;
.equ OCR0RA_4 = 4 ;
.equ OCR0RA_5 = 5 ;
.equ OCR0RA_6 = 6 ;
.equ OCR0RA_7 = 7 ;
; OCR0SAH - Output Compare SA Register High
.equ OCR0SA_8 = 0 ;
.equ OCR0SA_9 = 1 ;
.equ OCR0SA_00 = 2 ;
.equ OCR0SA_01 = 3 ;
; OCR0SAL - Output Compare SA Register Low
.equ OCR0SA_0 = 0 ;
.equ OCR0SA_1 = 1 ;
.equ OCR0SA_2 = 2 ;
.equ OCR0SA_3 = 3 ;
.equ OCR0SA_4 = 4 ;
.equ OCR0SA_5 = 5 ;
.equ OCR0SA_6 = 6 ;
.equ OCR0SA_7 = 7 ;
; PSOC0 - PSC0 Synchro and Output Configuration
.equ POEN0A = 0 ; PSCOUT00 Output Enable
.equ POEN0B = 2 ; PSCOUT01 Output Enable
.equ PSYNC00 = 4 ; Synchronization Out for ADC Selection
.equ PSYNC01 = 5 ; Synchronization Out for ADC Selection
; PIM0 - PSC0 Interrupt Mask Register
.equ PEOPE0 = 0 ; End of Cycle Interrupt Enable
.equ PEVE0A = 3 ; External Event A Interrupt Enable
.equ PEVE0B = 4 ; External Event B Interrupt Enable
.equ PSEIE0 = 5 ; PSC 0 Synchro Error Interrupt Enable
; PIFR0 - PSC0 Interrupt Flag Register
.equ PEOP0 = 0 ; End of PSC0 Interrupt
.equ PRN00 = 1 ; Ramp Number
.equ PRN01 = 2 ; Ramp Number
.equ PEV0A = 3 ; External Event A Interrupt
.equ PEV0B = 4 ; External Event B Interrupt
.equ PSEI0 = 5 ; PSC 0 Synchro Error Interrupt
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