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.equ PORTE4 = 4 ;
.equ PE4 = 4 ; For compatibility
.equ PORTE5 = 5 ;
.equ PE5 = 5 ; For compatibility
.equ PORTE6 = 6 ;
.equ PE6 = 6 ; For compatibility
.equ PORTE7 = 7 ;
.equ PE7 = 7 ; For compatibility
; DDRE - Data Direction Register, Port E
.equ DDE0 = 0 ;
.equ DDE1 = 1 ;
.equ DDE2 = 2 ;
.equ DDE3 = 3 ;
.equ DDE4 = 4 ;
.equ DDE5 = 5 ;
.equ DDE6 = 6 ;
.equ DDE7 = 7 ;
; PINE - Input Pins, Port E
.equ PINE0 = 0 ;
.equ PINE1 = 1 ;
.equ PINE2 = 2 ;
.equ PINE3 = 3 ;
.equ PINE4 = 4 ;
.equ PINE5 = 5 ;
.equ PINE6 = 6 ;
.equ PINE7 = 7 ;
; ***** PORTF ************************
; PORTF - Data Register, Port F
.equ PORTF0 = 0 ;
.equ PF0 = 0 ; For compatibility
.equ PORTF1 = 1 ;
.equ PF1 = 1 ; For compatibility
.equ PORTF2 = 2 ;
.equ PF2 = 2 ; For compatibility
.equ PORTF3 = 3 ;
.equ PF3 = 3 ; For compatibility
.equ PORTF4 = 4 ;
.equ PF4 = 4 ; For compatibility
.equ PORTF5 = 5 ;
.equ PF5 = 5 ; For compatibility
.equ PORTF6 = 6 ;
.equ PF6 = 6 ; For compatibility
.equ PORTF7 = 7 ;
.equ PF7 = 7 ; For compatibility
; DDRF - Data Direction Register, Port F
.equ DDF0 = 0 ;
.equ DDF1 = 1 ;
.equ DDF2 = 2 ;
.equ DDF3 = 3 ;
.equ DDF4 = 4 ;
.equ DDF5 = 5 ;
.equ DDF6 = 6 ;
.equ DDF7 = 7 ;
; PINF - Input Pins, Port F
.equ PINF0 = 0 ;
.equ PINF1 = 1 ;
.equ PINF2 = 2 ;
.equ PINF3 = 3 ;
.equ PINF4 = 4 ;
.equ PINF5 = 5 ;
.equ PINF6 = 6 ;
.equ PINF7 = 7 ;
; ***** PORTG ************************
; PORTG - Data Register, Port G
.equ PORTG0 = 0 ;
.equ PG0 = 0 ; For compatibility
.equ PORTG1 = 1 ;
.equ PG1 = 1 ; For compatibility
.equ PORTG2 = 2 ;
.equ PG2 = 2 ; For compatibility
.equ PORTG3 = 3 ;
.equ PG3 = 3 ; For compatibility
.equ PORTG4 = 4 ;
.equ PG4 = 4 ; For compatibility
; DDRG - Data Direction Register, Port G
.equ DDG0 = 0 ;
.equ DDG1 = 1 ;
.equ DDG2 = 2 ;
.equ DDG3 = 3 ;
.equ DDG4 = 4 ;
; PING - Input Pins, Port G
.equ PING0 = 0 ;
.equ PING1 = 1 ;
.equ PING2 = 2 ;
.equ PING3 = 3 ;
.equ PING4 = 4 ;
; ***** JTAG *************************
; OCDR - On-Chip Debug Related Register in I/O Memory
.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0
.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1
.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2
.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3
.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4
.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5
.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6
.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7
.equ IDRD = OCDR7 ; For compatibility
; MCUCR - MCU Control Register
.equ JTD = 7 ; JTAG Interface Disable
; MCUSR - MCU Status Register
.equ JTRF = 4 ; JTAG Reset Flag
; ***** SPI **************************
; SPDR - SPI Data Register
.equ SPDR0 = 0 ; SPI Data Register bit 0
.equ SPDR1 = 1 ; SPI Data Register bit 1
.equ SPDR2 = 2 ; SPI Data Register bit 2
.equ SPDR3 = 3 ; SPI Data Register bit 3
.equ SPDR4 = 4 ; SPI Data Register bit 4
.equ SPDR5 = 5 ; SPI Data Register bit 5
.equ SPDR6 = 6 ; SPI Data Register bit 6
.equ SPDR7 = 7 ; SPI Data Register bit 7
; SPSR - SPI Status Register
.equ SPI2X = 0 ; Double SPI Speed Bit
.equ WCOL = 6 ; Write Collision Flag
.equ SPIF = 7 ; SPI Interrupt Flag
; SPCR - SPI Control Register
.equ SPR0 = 0 ; SPI Clock Rate Select 0
.equ SPR1 = 1 ; SPI Clock Rate Select 1
.equ CPHA = 2 ; Clock Phase
.equ CPOL = 3 ; Clock polarity
.equ MSTR = 4 ; Master/Slave Select
.equ DORD = 5 ; Data Order
.equ SPE = 6 ; SPI Enable
.equ SPIE = 7 ; SPI Interrupt Enable
; ***** TWI **************************
; TWBR - TWI Bit Rate register
.equ I2BR = TWBR ; For compatibility
.equ TWBR0 = 0 ;
.equ TWBR1 = 1 ;
.equ TWBR2 = 2 ;
.equ TWBR3 = 3 ;
.equ TWBR4 = 4 ;
.equ TWBR5 = 5 ;
.equ TWBR6 = 6 ;
.equ TWBR7 = 7 ;
; TWCR - TWI Control Register
.equ I2CR = TWCR ; For compatibility
.equ TWIE = 0 ; TWI Interrupt Enable
.equ I2IE = TWIE ; For compatibility
.equ TWEN = 2 ; TWI Enable Bit
.equ I2EN = TWEN ; For compatibility
.equ ENI2C = TWEN ; For compatibility
.equ TWWC = 3 ; TWI Write Collition Flag
.equ I2WC = TWWC ; For compatibility
.equ TWSTO = 4 ; TWI Stop Condition Bit
.equ I2STO = TWSTO ; For compatibility
.equ TWSTA = 5 ; TWI Start Condition Bit
.equ I2STA = TWSTA ; For compatibility
.equ TWEA = 6 ; TWI Enable Acknowledge Bit
.equ I2EA = TWEA ; For compatibility
.equ TWINT = 7 ; TWI Interrupt Flag
.equ I2INT = TWINT ; For compatibility
; TWSR - TWI Status Register
.equ I2SR = TWSR ; For compatibility
.equ TWPS0 = 0 ; TWI Prescaler
.equ TWS0 = TWPS0 ; For compatibility
.equ I2GCE = TWPS0 ; For compatibility
.equ TWPS1 = 1 ; TWI Prescaler
.equ TWS1 = TWPS1 ; For compatibility
.equ TWS3 = 3 ; TWI Status
.equ I2S3 = TWS3 ; For compatibility
.equ TWS4 = 4 ; TWI Status
.equ I2S4 = TWS4 ; For compatibility
.equ TWS5 = 5 ; TWI Status
.equ I2S5 = TWS5 ; For compatibility
.equ TWS6 = 6 ; TWI Status
.equ I2S6 = TWS6 ; For compatibility
.equ TWS7 = 7 ; TWI Status
.equ I2S7 = TWS7 ; For compatibility
; TWDR - TWI Data register
.equ I2DR = TWDR ; For compatibility
.equ TWD0 = 0 ; TWI Data Register Bit 0
.equ TWD1 = 1 ; TWI Data Register Bit 1
.equ TWD2 = 2 ; TWI Data Register Bit 2
.equ TWD3 = 3 ; TWI Data Register Bit 3
.equ TWD4 = 4 ; TWI Data Register Bit 4
.equ TWD5 = 5 ; TWI Data Register Bit 5
.equ TWD6 = 6 ; TWI Data Register Bit 6
.equ TWD7 = 7 ; TWI Data Register Bit 7
; TWAR - TWI (Slave) Address register
.equ I2AR = TWAR ; For compatibility
.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit
.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0
.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1
.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2
.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3
.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4
.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5
.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6
; ***** USART0 ***********************
; UDR0 - USART I/O Data Register
.equ UDR00 = 0 ; USART I/O Data Register bit 0
.equ UDR01 = 1 ; USART I/O Data Register bit 1
.equ UDR02 = 2 ; USART I/O Data Register bit 2
.equ UDR03 = 3 ; USART I/O Data Register bit 3
.equ UDR04 = 4 ; USART I/O Data Register bit 4
.equ UDR05 = 5 ; USART I/O Data Register bit 5
.equ UDR06 = 6 ; USART I/O Data Register bit 6
.equ UDR07 = 7 ; USART I/O Data Register bit 7
; UCSR0A - USART Control and Status Register A
.equ MPCM0 = 0 ; Multi-processor Communication Mode
.equ U2X0 = 1 ; Double the USART transmission speed
.equ UPE0 = 2 ; Parity Error
.equ DOR0 = 3 ; Data overRun
.equ FE0 = 4 ; Framing Error
.equ UDRE0 = 5 ; USART Data Register Empty
.equ TXC0 = 6 ; USART Transmitt Complete
.equ RXC0 = 7 ; USART Receive Complete
; UCSR0B - USART Control and Status Register B
.equ TXB80 = 0 ; Transmit Data Bit 8
.equ RXB80 = 1 ; Receive Data Bit 8
.equ UCSZ02 = 2 ; Character Size
.equ UCSZ2 = UCSZ02 ; For compatibility
.equ TXEN0 = 3 ; Transmitter Enable
.equ RXEN0 = 4 ; Receiver Enable
.equ UDRIE0 = 5 ; USART Data register Empty Interrupt Enable
.equ TXCIE0 = 6 ; TX Complete Interrupt Enable
.equ RXCIE0 = 7 ; RX Complete Interrupt Enable
; UCSR0C - USART Control and Status Register C
.equ UCPOL0 = 0 ; Clock Polarity
.equ UCSZ00 = 1 ; Character Size
.equ UCSZ01 = 2 ; Character Size
.equ USBS0 = 3 ; Stop Bit Select
.equ UPM00 = 4 ; Parity Mode Bit 0
.equ UPM01 = 5 ; Parity Mode Bit 1
.equ UMSEL0 = 6 ; USART Mode Select
; UBRR0H - USART Baud Rate Register Hight Byte
.equ UBRR8 = 0 ; USART Baud Rate Register bit 8
.equ UBRR9 = 1 ; USART Baud Rate Register bit 9
.equ UBRR10 = 2 ; USART Baud Rate Register bit 10
.equ UBRR11 = 3 ; USART Baud Rate Register bit 11
; UBRR0L - USART Baud Rate Register Low Byte
.equ UBRR0 = 0 ; USART Baud Rate Register bit 0
.equ UBRR1 = 1 ; USART Baud Rate Register bit 1
.equ UBRR2 = 2 ; USART Baud Rate Register bit 2
.equ UBRR3 = 3 ; USART Baud Rate Register bit 3
.equ UBRR4 = 4 ; USART Baud Rate Register bit 4
.equ UBRR5 = 5 ; USART Baud Rate Register bit 5
.equ UBRR6 = 6 ; USART Baud Rate Register bit 6
.equ UBRR7 = 7 ; USART Baud Rate Register bit 7
; ***** USART1 ***********************
; UDR1 - USART I/O Data Register
.equ UDR10 = 0 ; USART I/O Data Register bit 0
.equ UDR11 = 1 ; USART I/O Data Register bit 1
.equ UDR12 = 2 ; USART I/O Data Register bit 2
.equ UDR13 = 3 ; USART I/O Data Register bit 3
.equ UDR14 = 4 ; USART I/O Data Register bit 4
.equ UDR15 = 5 ; USART I/O Data Register bit 5
.equ UDR16 = 6 ; USART I/O Data Register bit 6
.equ UDR17 = 7 ; USART I/O Data Register bit 7
; UCSR1A - USART Control and Status Register A
.equ MPCM1 = 0 ; Multi-processor Communication Mode
.equ U2X1 = 1 ; Double the USART transmission speed
.equ UPE1 = 2 ; Parity Error
.equ DOR1 = 3 ; Data overRun
.equ FE1 = 4 ; Framing Error
.equ UDRE1 = 5 ; USART Data Register Empty
.equ TXC1 = 6 ; USART Transmitt Complete
.equ RXC1 = 7 ; USART Receive Complete
; UCSR1B - USART Control and Status Register B
.equ TXB81 = 0 ; Transmit Data Bit 8
.equ RXB81 = 1 ; Receive Data Bit 8
.equ UCSZ12 = 2 ; Character Size
.equ TXEN1 = 3 ; Transmitter Enable
.equ RXEN1 = 4 ; Receiver Enable
.equ UDRIE1 = 5 ; USART Data register Empty Interrupt Enable
.equ TXCIE1 = 6 ; TX Complete Interrupt Enable
.equ RXCIE1 = 7 ; RX Complete Interrupt Enable
; UCSR1C - USART Control and Status Register C
.equ UCPOL1 = 0 ; Clock Polarity
.equ UCSZ10 = 1 ; Character Size
.equ UCSZ11 = 2 ; Character Size
.equ USBS1 = 3 ; Stop Bit Select
.equ UPM10 = 4 ; Parity Mode Bit 0
.equ UPM11 = 5 ; Parity Mode Bit 1
.equ UMSEL1 = 6 ; USART Mode Select
; UBRR1H - USART Baud Rate Register Hight Byte
;.equ UBRR8 = 0 ; USART Baud Rate Register bit 8
;.equ UBRR9 = 1 ; USART Baud Rate Register bit 9
;.equ UBRR10 = 2 ; USART Baud Rate Register bit 10
;.equ UBRR11 = 3 ; USART Baud Rate Register bit 11
; UBRR1L - USART Baud Rate Register Low Byte
;.equ UBRR0 = 0 ; USART Baud Rate Register bit 0
;.equ UBRR1 = 1 ; USART Baud Rate Register bit 1
;.equ UBRR2 = 2 ; USART Baud Rate Register bit 2
;.equ UBRR3 = 3 ; USART Baud Rate Register bit 3
;.equ UBRR4 = 4 ; USART Baud Rate Register bit 4
;.equ UBRR5 = 5 ; USART Baud Rate Register bit 5
;.equ UBRR6 = 6 ; USART Baud Rate Register bit 6
;.equ UBRR7 = 7 ; USART Baud Rate Register bit 7
; ***** CPU **************************
; SREG - Status Register
.equ SREG_C = 0 ; Carry Flag
.equ SREG_Z = 1 ; Zero Flag
.equ SREG_N = 2 ; Negative Flag
.equ SREG_V = 3 ; Two's Complement Overflow Flag
.equ SREG_S = 4 ; Sign Bit
.equ SREG_H = 5 ; Half Carry Flag
.equ SREG_T = 6 ; Bit Copy Storage
.equ SREG_I = 7 ; Global Interrupt Enable
; MCUCR - MCU Control Register
.equ IVCE = 0 ; Interrupt Vector Change Enable
.equ IVSEL = 1 ; Interrupt Vector Select
.equ PUD = 4 ; Pull-up disable
; MCUSR - MCU Status Register
.equ PORF = 0 ; Power-on reset flag
.equ EXTRF = 1 ; External Reset Flag
.equ BORF = 2 ; Brown-out Reset Flag
.equ WDRF = 3 ; Watchdog Reset Flag
;.equ JTRF = 4 ; JTAG Reset Flag
; XMCRA - External Memory Control Register A
.equ SRW00 = 0 ; Wait state select bit lower page
.equ SRW01 = 1 ; Wait state select bit lower page
.equ SRW10 = 2 ; Wait state select bit upper page
.equ SRW11 = 3 ; Wait state select bit upper page
.equ SRL0 = 4 ; Wait state page limit
.equ SRL1 = 5 ; Wait state page limit
.equ SRL2 = 6 ; Wait state page limit
.equ SRE = 7 ; External SRAM Enable
; XMCRB - External Memory Control Register B
.equ XMM0 = 0 ; External Memory High Mask
.equ XMM1 = 1 ; External Memory High Mask
.equ XMM2 = 2 ; External Memory High Mask
.equ XMBK = 7 ; External Memory Bus Keeper Enable
; OSCCAL - Oscillator Calibration Value
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6
; CLKPR - Clock Prescale Register
.equ CLKPS0 = 0 ;
.equ CLKPS1 = 1 ;
.equ CLKPS2 = 2 ;
.equ CLKPS3 = 3 ;
.equ CLKPCE = 7 ;
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