📄 m128def.inc
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; MCUCR - MCU Control Register
.equ IVCE = 0 ; Interrupt Vector Change Enable
.equ IVSEL = 1 ; Interrupt Vector Select
.equ SM2 = 2 ; Sleep Mode Select
.equ SM0 = 3 ; Sleep Mode Select
.equ SM1 = 4 ; Sleep Mode Select
.equ SE = 5 ; Sleep Enable
.equ SRW10 = 6 ; External SRAM Wait State Select
.equ SRE = 7 ; External SRAM Enable
; XMCRA - External Memory Control Register A
.equ SRW11 = 1 ; Wait state select bit upper page
.equ SRW00 = 2 ; Wait state select bit lower page
.equ SRW01 = 3 ; Wait state select bit lower page
.equ SRL0 = 4 ; Wait state page limit
.equ SRL1 = 5 ; Wait state page limit
.equ SRL2 = 6 ; Wait state page limit
; XMCRB - External Memory Control Register B
.equ XMM0 = 0 ; External Memory High Mask
.equ XMM1 = 1 ; External Memory High Mask
.equ XMM2 = 2 ; External Memory High Mask
.equ XMBK = 7 ; External Memory Bus Keeper Enable
; OSCCAL - Oscillator Calibration Value
.equ CAL0 = 0 ; Oscillator Calibration Value
.equ CAL1 = 1 ; Oscillator Calibration Value
.equ CAL2 = 2 ; Oscillator Calibration Value
.equ CAL3 = 3 ; Oscillator Calibration Value
.equ CAL4 = 4 ; Oscillator Calibration Value
.equ CAL5 = 5 ; Oscillator Calibration Value
.equ CAL6 = 6 ; Oscillator Calibration Value
.equ CAL7 = 7 ; Oscillator Calibration Value
; XDIV - XTAL Divide Control Register
.equ XDIV0 = 0 ; XTAl Divide Select Bit 0
.equ XDIV1 = 1 ; XTAl Divide Select Bit 1
.equ XDIV2 = 2 ; XTAl Divide Select Bit 2
.equ XDIV3 = 3 ; XTAl Divide Select Bit 3
.equ XDIV4 = 4 ; XTAl Divide Select Bit 4
.equ XDIV5 = 5 ; XTAl Divide Select Bit 5
.equ XDIV6 = 6 ; XTAl Divide Select Bit 6
.equ XDIVEN = 7 ; XTAL Divide Enable
; MCUCSR - MCU Control And Status Register
.equ PORF = 0 ; Power-on reset flag
.equ EXTRF = 1 ; External Reset Flag
.equ BORF = 2 ; Brown-out Reset Flag
.equ WDRF = 3 ; Watchdog Reset Flag
.equ JTRF = 4 ; JTAG Reset Flag
.equ JTD = 7 ; JTAG Interface Disable
; RAMPZ - RAM Page Z Select Register
.equ RAMPZ0 = 0 ; RAM Page Z Select Register Bit 0
; ***** BOOT_LOAD ********************
; SPMCSR - Store Program Memory Control Register
.equ SPMCR = SPMCSR ; For compatibility
.equ SPMEN = 0 ; Store Program Memory Enable
.equ PGERS = 1 ; Page Erase
.equ PGWRT = 2 ; Page Write
.equ BLBSET = 3 ; Boot Lock Bit Set
.equ RWWSRE = 4 ; Read While Write section read enable
.equ ASRE = RWWSRE ; For compatibility
.equ RWWSB = 6 ; Read While Write Section Busy
.equ ASB = RWWSB ; For compatibility
.equ SPMIE = 7 ; SPM Interrupt Enable
; ***** JTAG *************************
; OCDR - On-Chip Debug Related Register in I/O Memory
.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0
.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1
.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2
.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3
.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4
.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5
.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6
.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7
.equ IDRD = OCDR7 ; For compatibility
; MCUCSR - MCU Control And Status Register
;.equ JTRF = 4 ; JTAG Reset Flag
;.equ JTD = 7 ; JTAG Interface Disable
; ***** MISC *************************
; SFIOR - Special Function IO Register
.equ PSR321 = 0 ; Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1
.equ PSR1 = PSR321 ; For compatibility
.equ PSR2 = PSR321 ; For compatibility
.equ PSR3 = PSR321 ; For compatibility
.equ PSR0 = 1 ; Prescaler Reset Timer/Counter0
.equ PUD = 2 ; Pull Up Disable
;.equ ACME = 3 ; Analog Comparator Multiplexer Enable
.equ TSM = 7 ; Timer/Counter Synchronization Mode
; ***** EXTERNAL_INTERRUPT ***********
; EICRA - External Interrupt Control Register A
.equ ISC00 = 0 ; External Interrupt Sense Control Bit
.equ ISC01 = 1 ; External Interrupt Sense Control Bit
.equ ISC10 = 2 ; External Interrupt Sense Control Bit
.equ ISC11 = 3 ; External Interrupt Sense Control Bit
.equ ISC20 = 4 ; External Interrupt Sense Control Bit
.equ ISC21 = 5 ; External Interrupt Sense Control Bit
.equ ISC30 = 6 ; External Interrupt Sense Control Bit
.equ ISC31 = 7 ; External Interrupt Sense Control Bit
; EICRB - External Interrupt Control Register B
.equ ISC40 = 0 ; External Interrupt 7-4 Sense Control Bit
.equ ISC41 = 1 ; External Interrupt 7-4 Sense Control Bit
.equ ISC50 = 2 ; External Interrupt 7-4 Sense Control Bit
.equ ISC51 = 3 ; External Interrupt 7-4 Sense Control Bit
.equ ISC60 = 4 ; External Interrupt 7-4 Sense Control Bit
.equ ISC61 = 5 ; External Interrupt 7-4 Sense Control Bit
.equ ISC70 = 6 ; External Interrupt 7-4 Sense Control Bit
.equ ISC71 = 7 ; External Interrupt 7-4 Sense Control Bit
; EIMSK - External Interrupt Mask Register
.equ GICR = EIMSK ; For compatibility
.equ GIMSK = EIMSK ; For compatibility
.equ INT0 = 0 ; External Interrupt Request 0 Enable
.equ INT1 = 1 ; External Interrupt Request 1 Enable
.equ INT2 = 2 ; External Interrupt Request 2 Enable
.equ INT3 = 3 ; External Interrupt Request 3 Enable
.equ INT4 = 4 ; External Interrupt Request 4 Enable
.equ INT5 = 5 ; External Interrupt Request 5 Enable
.equ INT6 = 6 ; External Interrupt Request 6 Enable
.equ INT7 = 7 ; External Interrupt Request 7 Enable
; EIFR - External Interrupt Flag Register
.equ GIFR = EIFR ; For compatibility
.equ INTF0 = 0 ; External Interrupt Flag 0
.equ INTF1 = 1 ; External Interrupt Flag 1
.equ INTF2 = 2 ; External Interrupt Flag 2
.equ INTF3 = 3 ; External Interrupt Flag 3
.equ INTF4 = 4 ; External Interrupt Flag 4
.equ INTF5 = 5 ; External Interrupt Flag 5
.equ INTF6 = 6 ; External Interrupt Flag 6
.equ INTF7 = 7 ; External Interrupt Flag 7
; ***** EEPROM ***********************
; EEDR - EEPROM Data Register
.equ EEDR0 = 0 ; EEPROM Data Register bit 0
.equ EEDR1 = 1 ; EEPROM Data Register bit 1
.equ EEDR2 = 2 ; EEPROM Data Register bit 2
.equ EEDR3 = 3 ; EEPROM Data Register bit 3
.equ EEDR4 = 4 ; EEPROM Data Register bit 4
.equ EEDR5 = 5 ; EEPROM Data Register bit 5
.equ EEDR6 = 6 ; EEPROM Data Register bit 6
.equ EEDR7 = 7 ; EEPROM Data Register bit 7
; EECR - EEPROM Control Register
.equ EERE = 0 ; EEPROM Read Enable
.equ EEWE = 1 ; EEPROM Write Enable
.equ EEMWE = 2 ; EEPROM Master Write Enable
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable
; ***** PORTA ************************
; PORTA - Port A Data Register
.equ PORTA0 = 0 ; Port A Data Register bit 0
.equ PA0 = 0 ; For compatibility
.equ PORTA1 = 1 ; Port A Data Register bit 1
.equ PA1 = 1 ; For compatibility
.equ PORTA2 = 2 ; Port A Data Register bit 2
.equ PA2 = 2 ; For compatibility
.equ PORTA3 = 3 ; Port A Data Register bit 3
.equ PA3 = 3 ; For compatibility
.equ PORTA4 = 4 ; Port A Data Register bit 4
.equ PA4 = 4 ; For compatibility
.equ PORTA5 = 5 ; Port A Data Register bit 5
.equ PA5 = 5 ; For compatibility
.equ PORTA6 = 6 ; Port A Data Register bit 6
.equ PA6 = 6 ; For compatibility
.equ PORTA7 = 7 ; Port A Data Register bit 7
.equ PA7 = 7 ; For compatibility
; DDRA - Port A Data Direction Register
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7
; PINA - Port A Input Pins
.equ PINA0 = 0 ; Input Pins, Port A bit 0
.equ PINA1 = 1 ; Input Pins, Port A bit 1
.equ PINA2 = 2 ; Input Pins, Port A bit 2
.equ PINA3 = 3 ; Input Pins, Port A bit 3
.equ PINA4 = 4 ; Input Pins, Port A bit 4
.equ PINA5 = 5 ; Input Pins, Port A bit 5
.equ PINA6 = 6 ; Input Pins, Port A bit 6
.equ PINA7 = 7 ; Input Pins, Port A bit 7
; ***** PORTB ************************
; PORTB - Port B Data Register
.equ PORTB0 = 0 ; Port B Data Register bit 0
.equ PB0 = 0 ; For compatibility
.equ PORTB1 = 1 ; Port B Data Register bit 1
.equ PB1 = 1 ; For compatibility
.equ PORTB2 = 2 ; Port B Data Register bit 2
.equ PB2 = 2 ; For compatibility
.equ PORTB3 = 3 ; Port B Data Register bit 3
.equ PB3 = 3 ; For compatibility
.equ PORTB4 = 4 ; Port B Data Register bit 4
.equ PB4 = 4 ; For compatibility
.equ PORTB5 = 5 ; Port B Data Register bit 5
.equ PB5 = 5 ; For compatibility
.equ PORTB6 = 6 ; Port B Data Register bit 6
.equ PB6 = 6 ; For compatibility
.equ PORTB7 = 7 ; Port B Data Register bit 7
.equ PB7 = 7 ; For compatibility
; DDRB - Port B Data Direction Register
.equ DDB0 = 0 ; Port B Data Direction Register bit 0
.equ DDB1 = 1 ; Port B Data Direction Register bit 1
.equ DDB2 = 2 ; Port B Data Direction Register bit 2
.equ DDB3 = 3 ; Port B Data Direction Register bit 3
.equ DDB4 = 4 ; Port B Data Direction Register bit 4
.equ DDB5 = 5 ; Port B Data Direction Register bit 5
.equ DDB6 = 6 ; Port B Data Direction Register bit 6
.equ DDB7 = 7 ; Port B Data Direction Register bit 7
; PINB - Port B Input Pins
.equ PINB0 = 0 ; Port B Input Pins bit 0
.equ PINB1 = 1 ; Port B Input Pins bit 1
.equ PINB2 = 2 ; Port B Input Pins bit 2
.equ PINB3 = 3 ; Port B Input Pins bit 3
.equ PINB4 = 4 ; Port B Input Pins bit 4
.equ PINB5 = 5 ; Port B Input Pins bit 5
.equ PINB6 = 6 ; Port B Input Pins bit 6
.equ PINB7 = 7 ; Port B Input Pins bit 7
; ***** PORTC ************************
; PORTC - Port C Data Register
.equ PORTC0 = 0 ; Port C Data Register bit 0
.equ PC0 = 0 ; For compatibility
.equ PORTC1 = 1 ; Port C Data Register bit 1
.equ PC1 = 1 ; For compatibility
.equ PORTC2 = 2 ; Port C Data Register bit 2
.equ PC2 = 2 ; For compatibility
.equ PORTC3 = 3 ; Port C Data Register bit 3
.equ PC3 = 3 ; For compatibility
.equ PORTC4 = 4 ; Port C Data Register bit 4
.equ PC4 = 4 ; For compatibility
.equ PORTC5 = 5 ; Port C Data Register bit 5
.equ PC5 = 5 ; For compatibility
.equ PORTC6 = 6 ; Port C Data Register bit 6
.equ PC6 = 6 ; For compatibility
.equ PORTC7 = 7 ; Port C Data Register bit 7
.equ PC7 = 7 ; For compatibility
; DDRC - Port C Data Direction Register
.equ DDC0 = 0 ; Port C Data Direction Register bit 0
.equ DDC1 = 1 ; Port C Data Direction Register bit 1
.equ DDC2 = 2 ; Port C Data Direction Register bit 2
.equ DDC3 = 3 ; Port C Data Direction Register bit 3
.equ DDC4 = 4 ; Port C Data Direction Register bit 4
.equ DDC5 = 5 ; Port C Data Direction Register bit 5
.equ DDC6 = 6 ; Port C Data Direction Register bit 6
.equ DDC7 = 7 ; Port C Data Direction Register bit 7
; PINC - Port C Input Pins
.equ PINC0 = 0 ; Port C Input Pins bit 0
.equ PINC1 = 1 ; Port C Input Pins bit 1
.equ PINC2 = 2 ; Port C Input Pins bit 2
.equ PINC3 = 3 ; Port C Input Pins bit 3
.equ PINC4 = 4 ; Port C Input Pins bit 4
.equ PINC5 = 5 ; Port C Input Pins bit 5
.equ PINC6 = 6 ; Port C Input Pins bit 6
.equ PINC7 = 7 ; Port C Input Pins bit 7
; ***** PORTD ************************
; PORTD - Port D Data Register
.equ PORTD0 = 0 ; Port D Data Register bit 0
.equ PD0 = 0 ; For compatibility
.equ PORTD1 = 1 ; Port D Data Register bit 1
.equ PD1 = 1 ; For compatibility
.equ PORTD2 = 2 ; Port D Data Register bit 2
.equ PD2 = 2 ; For compatibility
.equ PORTD3 = 3 ; Port D Data Register bit 3
.equ PD3 = 3 ; For compatibility
.equ PORTD4 = 4 ; Port D Data Register bit 4
.equ PD4 = 4 ; For compatibility
.equ PORTD5 = 5 ; Port D Data Register bit 5
.equ PD5 = 5 ; For compatibility
.equ PORTD6 = 6 ; Port D Data Register bit 6
.equ PD6 = 6 ; For compatibility
.equ PORTD7 = 7 ; Port D Data Register bit 7
.equ PD7 = 7 ; For compatibility
; DDRD - Port D Data Direction Register
.equ DDD0 = 0 ; Port D Data Direction Register bit 0
.equ DDD1 = 1 ; Port D Data Direction Register bit 1
.equ DDD2 = 2 ; Port D Data Direction Register bit 2
.equ DDD3 = 3 ; Port D Data Direction Register bit 3
.equ DDD4 = 4 ; Port D Data Direction Register bit 4
.equ DDD5 = 5 ; Port D Data Direction Register bit 5
.equ DDD6 = 6 ; Port D Data Direction Register bit 6
.equ DDD7 = 7 ; Port D Data Direction Register bit 7
; PIND - Port D Input Pins
.equ PIND0 = 0 ; Port D Input Pins bit 0
.equ PIND1 = 1 ; Port D Input Pins bit 1
.equ PIND2 = 2 ; Port D Input Pins bit 2
.equ PIND3 = 3 ; Port D Input Pins bit 3
.equ PIND4 = 4 ; Port D Input Pins bit 4
.equ PIND5 = 5 ; Port D Input Pins bit 5
.equ PIND6 = 6 ; Port D Input Pins bit 6
.equ PIND7 = 7 ; Port D Input Pins bit 7
; ***** PORTE ************************
; PORTE - Data Register, Port E
.equ PORTE0 = 0 ;
.equ PE0 = 0 ; For compatibility
.equ PORTE1 = 1 ;
.equ PE1 = 1 ; For compatibility
.equ PORTE2 = 2 ;
.equ PE2 = 2 ; For compatibility
.equ PORTE3 = 3 ;
.equ PE3 = 3 ; For compatibility
.equ PORTE4 = 4 ;
.equ PE4 = 4 ; For compatibility
.equ PORTE5 = 5 ;
.equ PE5 = 5 ; For compatibility
.equ PORTE6 = 6 ;
.equ PE6 = 6 ; For compatibility
.equ PORTE7 = 7 ;
.equ PE7 = 7 ; For compatibility
; DDRE - Data Direction Register, Port E
.equ DDE0 = 0 ;
.equ DDE1 = 1 ;
.equ DDE2 = 2 ;
.equ DDE3 = 3 ;
.equ DDE4 = 4 ;
.equ DDE5 = 5 ;
.equ DDE6 = 6 ;
.equ DDE7 = 7 ;
; PINE - Input Pins, Port E
.equ PINE0 = 0 ;
.equ PINE1 = 1 ;
.equ PINE2 = 2 ;
.equ PINE3 = 3 ;
.equ PINE4 = 4 ;
.equ PINE5 = 5 ;
.equ PINE6 = 6 ;
.equ PINE7 = 7 ;
; ***** PORTF ************************
; PORTF - Data Register, Port F
.equ PORTF0 = 0 ;
.equ PF0 = 0 ; For compatibility
.equ PORTF1 = 1 ;
.equ PF1 = 1 ; For compatibility
.equ PORTF2 = 2 ;
.equ PF2 = 2 ; For compatibility
.equ PORTF3 = 3 ;
.equ PF3 = 3 ; For compatibility
.equ PORTF4 = 4 ;
.equ PF4 = 4 ; For compatibility
.equ PORTF5 = 5 ;
.equ PF5 = 5 ; For compatibility
.equ PORTF6 = 6 ;
.equ PF6 = 6 ; For compatibility
.equ PORTF7 = 7 ;
.equ PF7 = 7 ; For compatibility
; DDRF - Data Direction Register, Port F
.equ DDF0 = 0 ;
.equ DDF1 = 1 ;
.equ DDF2 = 2 ;
.equ DDF3 = 3 ;
.equ DDF4 = 4 ;
.equ DDF5 = 5 ;
.equ DDF6 = 6 ;
.equ DDF7 = 7 ;
; PINF - Input Pins, Port F
.equ PINF0 = 0 ;
.equ PINF1 = 1 ;
.equ PINF2 = 2 ;
.equ PINF3 = 3 ;
.equ PINF4 = 4 ;
.equ PINF5 = 5 ;
.equ PINF6 = 6 ;
.equ PINF7 = 7 ;
; ***** PORTG ************************
; PORTG - Data Register, Port G
.equ PORTG0 = 0 ;
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