📄 gxt4500.c
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/* set PLL registers */ tmp = readreg(par, PLL_C) & ~0x7f; if (par->pll_n < 38) tmp |= 0x29; if (par->pll_n < 69) tmp |= 0x35; else if (par->pll_n < 100) tmp |= 0x76; else tmp |= 0x7e; writereg(par, PLL_C, tmp); writereg(par, PLL_M, mdivtab[par->pll_m - 1]); writereg(par, PLL_N, ndivtab[par->pll_n - 2]); tmp = ((8 - par->pll_pd2) << 3) | (8 - par->pll_pd1); if (par->pll_pd1 == 8 || par->pll_pd2 == 8) { /* work around erratum */ writereg(par, PLL_POSTDIV, tmp | 0x9); udelay(1); } writereg(par, PLL_POSTDIV, tmp); msleep(20); /* turn off hardware cursor */ writereg(par, CURSOR_MODE, CURSOR_MODE_OFF); /* reset raster engine */ writereg(par, CTRL_REG0, CR0_RASTER_RESET | (CR0_RASTER_RESET << 16)); udelay(10); writereg(par, CTRL_REG0, CR0_RASTER_RESET << 16); /* set display timing generator registers */ htot = var->xres + var->left_margin + var->right_margin + var->hsync_len; writereg(par, DTG_HORIZ_EXTENT, htot - 1); writereg(par, DTG_HORIZ_DISPLAY, var->xres - 1); writereg(par, DTG_HSYNC_START, var->xres + var->right_margin - 1); writereg(par, DTG_HSYNC_END, var->xres + var->right_margin + var->hsync_len - 1); writereg(par, DTG_HSYNC_END_COMP, var->xres + var->right_margin + var->hsync_len - 1); writereg(par, DTG_VERT_EXTENT, var->yres + var->upper_margin + var->lower_margin + var->vsync_len - 1); writereg(par, DTG_VERT_DISPLAY, var->yres - 1); writereg(par, DTG_VSYNC_START, var->yres + var->lower_margin - 1); writereg(par, DTG_VSYNC_END, var->yres + var->lower_margin + var->vsync_len - 1); prefetch_pix = 3300000 / var->pixclock; if (prefetch_pix >= htot) prefetch_pix = htot - 1; writereg(par, DTG_VERT_SHORT, htot - prefetch_pix - 1); ctrlreg |= DTG_CTL_ENABLE | DTG_CTL_SCREEN_REFRESH; writereg(par, DTG_CONTROL, ctrlreg); /* calculate stride in DFA aperture */ if (var->xres_virtual > 2048) { stride = 4096; dfa_ctl = DFA_FB_STRIDE_4k; } else if (var->xres_virtual > 1024) { stride = 2048; dfa_ctl = DFA_FB_STRIDE_2k; } else { stride = 1024; dfa_ctl = DFA_FB_STRIDE_1k; } /* Set up framebuffer definition */ wid_tiles = (var->xres_virtual + 63) >> 6; /* XXX add proper FB allocation here someday */ writereg(par, FB_AB_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0); writereg(par, REFRESH_AB_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0); writereg(par, FB_CD_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0); writereg(par, REFRESH_CD_CTRL, FB_CTRL_TYPE | (wid_tiles << 16) | 0); writereg(par, REFRESH_START, (var->xoffset << 16) | var->yoffset); writereg(par, REFRESH_SIZE, (var->xres << 16) | var->yres); /* Set up framebuffer access by CPU */ pixfmt = par->pixfmt; dfa_ctl |= DFA_FB_ENABLE | pixfmt; writereg(par, DFA_FB_A, dfa_ctl); /* * Set up window attribute table. * We set all WAT entries the same so it doesn't matter what the * window ID (WID) plane contains. */ for (i = 0; i < 32; ++i) { writereg(par, WAT_FMT + (i << 4), watfmt[pixfmt]); writereg(par, WAT_CMAP_OFFSET + (i << 4), 0); writereg(par, WAT_CTRL + (i << 4), 0); writereg(par, WAT_GAMMA_CTRL + (i << 4), WAT_GAMMA_DISABLE); } /* Set sync polarity etc. */ ctrlreg = readreg(par, SYNC_CTL) & ~(SYNC_CTL_SYNC_ON_RGB | SYNC_CTL_HSYNC_INV | SYNC_CTL_VSYNC_INV); if (var->sync & FB_SYNC_ON_GREEN) ctrlreg |= SYNC_CTL_SYNC_ON_RGB; if (!(var->sync & FB_SYNC_HOR_HIGH_ACT)) ctrlreg |= SYNC_CTL_HSYNC_INV; if (!(var->sync & FB_SYNC_VERT_HIGH_ACT)) ctrlreg |= SYNC_CTL_VSYNC_INV; writereg(par, SYNC_CTL, ctrlreg); info->fix.line_length = stride * pixsize[pixfmt]; info->fix.visual = (pixfmt == DFA_PIX_8BIT)? FB_VISUAL_PSEUDOCOLOR: FB_VISUAL_DIRECTCOLOR; return 0;}static int gxt4500_setcolreg(unsigned int reg, unsigned int red, unsigned int green, unsigned int blue, unsigned int transp, struct fb_info *info){ u32 cmap_entry; struct gxt4500_par *par = info->par; if (reg > 1023) return 1; cmap_entry = ((transp & 0xff00) << 16) | ((red & 0xff00) << 8) | (green & 0xff00) | (blue >> 8); writereg(par, CMAP + reg * 4, cmap_entry); if (reg < 16 && par->pixfmt != DFA_PIX_8BIT) { u32 *pal = info->pseudo_palette; u32 val = reg; switch (par->pixfmt) { case DFA_PIX_16BIT_565: val |= (reg << 11) | (reg << 6); break; case DFA_PIX_16BIT_1555: val |= (reg << 10) | (reg << 5); break; case DFA_PIX_32BIT: val |= (reg << 24); /* fall through */ case DFA_PIX_24BIT: val |= (reg << 16) | (reg << 8); break; } pal[reg] = val; } return 0;}static int gxt4500_pan_display(struct fb_var_screeninfo *var, struct fb_info *info){ struct gxt4500_par *par = info->par; if (var->xoffset & 7) return -EINVAL; if (var->xoffset + var->xres > var->xres_virtual || var->yoffset + var->yres > var->yres_virtual) return -EINVAL; writereg(par, REFRESH_START, (var->xoffset << 16) | var->yoffset); return 0;}static int gxt4500_blank(int blank, struct fb_info *info){ struct gxt4500_par *par = info->par; int ctrl, dctl; ctrl = readreg(par, SYNC_CTL); ctrl &= ~(SYNC_CTL_SYNC_OFF | SYNC_CTL_HSYNC_OFF | SYNC_CTL_VSYNC_OFF); dctl = readreg(par, DISP_CTL); dctl |= DISP_CTL_OFF; switch (blank) { case FB_BLANK_UNBLANK: dctl &= ~DISP_CTL_OFF; break; case FB_BLANK_POWERDOWN: ctrl |= SYNC_CTL_SYNC_OFF; break; case FB_BLANK_HSYNC_SUSPEND: ctrl |= SYNC_CTL_HSYNC_OFF; break; case FB_BLANK_VSYNC_SUSPEND: ctrl |= SYNC_CTL_VSYNC_OFF; break; default: ; } writereg(par, SYNC_CTL, ctrl); writereg(par, DISP_CTL, dctl); return 0;}static const struct fb_fix_screeninfo gxt4500_fix __devinitdata = { .id = "IBM GXT4500P", .type = FB_TYPE_PACKED_PIXELS, .visual = FB_VISUAL_PSEUDOCOLOR, .xpanstep = 8, .ypanstep = 1, .mmio_len = 0x20000,};static struct fb_ops gxt4500_ops = { .owner = THIS_MODULE, .fb_check_var = gxt4500_check_var, .fb_set_par = gxt4500_set_par, .fb_setcolreg = gxt4500_setcolreg, .fb_pan_display = gxt4500_pan_display, .fb_blank = gxt4500_blank, .fb_fillrect = cfb_fillrect, .fb_copyarea = cfb_copyarea, .fb_imageblit = cfb_imageblit,};/* PCI functions */static int __devinit gxt4500_probe(struct pci_dev *pdev, const struct pci_device_id *ent){ int err; unsigned long reg_phys, fb_phys; struct gxt4500_par *par; struct fb_info *info; struct fb_var_screeninfo var; enum gxt_cards cardtype; err = pci_enable_device(pdev); if (err) { dev_err(&pdev->dev, "gxt4500: cannot enable PCI device: %d\n", err); return err; } reg_phys = pci_resource_start(pdev, 0); if (!request_mem_region(reg_phys, pci_resource_len(pdev, 0), "gxt4500 regs")) { dev_err(&pdev->dev, "gxt4500: cannot get registers\n"); goto err_nodev; } fb_phys = pci_resource_start(pdev, 1); if (!request_mem_region(fb_phys, pci_resource_len(pdev, 1), "gxt4500 FB")) { dev_err(&pdev->dev, "gxt4500: cannot get framebuffer\n"); goto err_free_regs; } info = framebuffer_alloc(sizeof(struct gxt4500_par), &pdev->dev); if (!info) { dev_err(&pdev->dev, "gxt4500: cannot alloc FB info record\n"); goto err_free_fb; } par = info->par; cardtype = ent->driver_data; par->refclk_ps = cardinfo[cardtype].refclk_ps; info->fix = gxt4500_fix; strlcpy(info->fix.id, cardinfo[cardtype].cardname, sizeof(info->fix.id)); info->pseudo_palette = par->pseudo_palette; info->fix.mmio_start = reg_phys; par->regs = pci_ioremap_bar(pdev, 0); if (!par->regs) { dev_err(&pdev->dev, "gxt4500: cannot map registers\n"); goto err_free_all; } info->fix.smem_start = fb_phys; info->fix.smem_len = pci_resource_len(pdev, 1); info->screen_base = pci_ioremap_bar(pdev, 1); if (!info->screen_base) { dev_err(&pdev->dev, "gxt4500: cannot map framebuffer\n"); goto err_unmap_regs; } pci_set_drvdata(pdev, info); /* Set byte-swapping for DFA aperture for all pixel sizes */ pci_write_config_dword(pdev, CFG_ENDIAN0, 0x333300); info->fbops = &gxt4500_ops; info->flags = FBINFO_FLAG_DEFAULT; err = fb_alloc_cmap(&info->cmap, 256, 0); if (err) { dev_err(&pdev->dev, "gxt4500: cannot allocate cmap\n"); goto err_unmap_all; } gxt4500_blank(FB_BLANK_UNBLANK, info); if (!fb_find_mode(&var, info, mode_option, NULL, 0, &defaultmode, 8)) { dev_err(&pdev->dev, "gxt4500: cannot find valid video mode\n"); goto err_free_cmap; } info->var = var; if (gxt4500_set_par(info)) { printk(KERN_ERR "gxt4500: cannot set video mode\n"); goto err_free_cmap; } if (register_framebuffer(info) < 0) { dev_err(&pdev->dev, "gxt4500: cannot register framebuffer\n"); goto err_free_cmap; } printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, info->fix.id); return 0; err_free_cmap: fb_dealloc_cmap(&info->cmap); err_unmap_all: iounmap(info->screen_base); err_unmap_regs: iounmap(par->regs); err_free_all: framebuffer_release(info); err_free_fb: release_mem_region(fb_phys, pci_resource_len(pdev, 1)); err_free_regs: release_mem_region(reg_phys, pci_resource_len(pdev, 0)); err_nodev: return -ENODEV;}static void __devexit gxt4500_remove(struct pci_dev *pdev){ struct fb_info *info = pci_get_drvdata(pdev); struct gxt4500_par *par; if (!info) return; par = info->par; unregister_framebuffer(info); fb_dealloc_cmap(&info->cmap); iounmap(par->regs); iounmap(info->screen_base); release_mem_region(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0)); release_mem_region(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1)); framebuffer_release(info);}/* supported chipsets */static const struct pci_device_id gxt4500_pci_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_GXT4500P), .driver_data = GXT4500P }, { PCI_DEVICE(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_GXT6000P), .driver_data = GXT6000P }, { 0 }};MODULE_DEVICE_TABLE(pci, gxt4500_pci_tbl);static struct pci_driver gxt4500_driver = { .name = "gxt4500", .id_table = gxt4500_pci_tbl, .probe = gxt4500_probe, .remove = __devexit_p(gxt4500_remove),};static int __devinit gxt4500_init(void){#ifndef MODULE if (fb_get_options("gxt4500", &mode_option)) return -ENODEV;#endif return pci_register_driver(&gxt4500_driver);}module_init(gxt4500_init);static void __exit gxt4500_exit(void){ pci_unregister_driver(&gxt4500_driver);}module_exit(gxt4500_exit);MODULE_AUTHOR("Paul Mackerras <paulus@samba.org>");MODULE_DESCRIPTION("FBDev driver for IBM GXT4500P/6000P");MODULE_LICENSE("GPL");module_param(mode_option, charp, 0);MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\"");
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