📄 savagefb_driver.c
字号:
else if ((var->bits_per_pixel > 8) && (var->bits_per_pixel < 24)) par->dacSpeedBpp = par->clock[1]; else if (var->bits_per_pixel <= 8) par->dacSpeedBpp = par->clock[0]; } /* Set ramdac limits */ par->maxClock = par->dacSpeedBpp; par->minClock = 10000; savagefb_set_par_int(par, &par->state); fb_set_cmap(&info->cmap, info); savagefb_set_fix(info); savagefb_set_clip(info); SavagePrintRegs(par); return 0;}/* * Pan or Wrap the Display */static int savagefb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info){ struct savagefb_par *par = info->par; savagefb_update_start(par, var); return 0;}static int savagefb_blank(int blank, struct fb_info *info){ struct savagefb_par *par = info->par; u8 sr8 = 0, srd = 0; if (par->display_type == DISP_CRT) { vga_out8(0x3c4, 0x08, par); sr8 = vga_in8(0x3c5, par); sr8 |= 0x06; vga_out8(0x3c5, sr8, par); vga_out8(0x3c4, 0x0d, par); srd = vga_in8(0x3c5, par); srd &= 0x03; switch (blank) { case FB_BLANK_UNBLANK: case FB_BLANK_NORMAL: break; case FB_BLANK_VSYNC_SUSPEND: srd |= 0x10; break; case FB_BLANK_HSYNC_SUSPEND: srd |= 0x40; break; case FB_BLANK_POWERDOWN: srd |= 0x50; break; } vga_out8(0x3c4, 0x0d, par); vga_out8(0x3c5, srd, par); } if (par->display_type == DISP_LCD || par->display_type == DISP_DFP) { switch(blank) { case FB_BLANK_UNBLANK: case FB_BLANK_NORMAL: vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */ vga_out8(0x3c5, vga_in8(0x3c5, par) | 0x10, par); break; case FB_BLANK_VSYNC_SUSPEND: case FB_BLANK_HSYNC_SUSPEND: case FB_BLANK_POWERDOWN: vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */ vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x10, par); break; } } return (blank == FB_BLANK_NORMAL) ? 1 : 0;}static void savagefb_save_state(struct fb_info *info){ struct savagefb_par *par = info->par; savage_get_default_par(par, &par->save);}static void savagefb_restore_state(struct fb_info *info){ struct savagefb_par *par = info->par; savagefb_blank(FB_BLANK_POWERDOWN, info); savage_set_default_par(par, &par->save); savagefb_blank(FB_BLANK_UNBLANK, info);}static int savagefb_open(struct fb_info *info, int user){ struct savagefb_par *par = info->par; mutex_lock(&par->open_lock); if (!par->open_count) { memset(&par->vgastate, 0, sizeof(par->vgastate)); par->vgastate.flags = VGA_SAVE_CMAP | VGA_SAVE_FONTS | VGA_SAVE_MODE; par->vgastate.vgabase = par->mmio.vbase + 0x8000; save_vga(&par->vgastate); savage_get_default_par(par, &par->initial); } par->open_count++; mutex_unlock(&par->open_lock); return 0;}static int savagefb_release(struct fb_info *info, int user){ struct savagefb_par *par = info->par; mutex_lock(&par->open_lock); if (par->open_count == 1) { savage_set_default_par(par, &par->initial); restore_vga(&par->vgastate); } par->open_count--; mutex_unlock(&par->open_lock); return 0;}static struct fb_ops savagefb_ops = { .owner = THIS_MODULE, .fb_open = savagefb_open, .fb_release = savagefb_release, .fb_check_var = savagefb_check_var, .fb_set_par = savagefb_set_par, .fb_setcolreg = savagefb_setcolreg, .fb_pan_display = savagefb_pan_display, .fb_blank = savagefb_blank, .fb_save_state = savagefb_save_state, .fb_restore_state = savagefb_restore_state,#if defined(CONFIG_FB_SAVAGE_ACCEL) .fb_fillrect = savagefb_fillrect, .fb_copyarea = savagefb_copyarea, .fb_imageblit = savagefb_imageblit, .fb_sync = savagefb_sync,#else .fb_fillrect = cfb_fillrect, .fb_copyarea = cfb_copyarea, .fb_imageblit = cfb_imageblit,#endif};/* --------------------------------------------------------------------- */static struct fb_var_screeninfo __devinitdata savagefb_var800x600x8 = { .accel_flags = FB_ACCELF_TEXT, .xres = 800, .yres = 600, .xres_virtual = 800, .yres_virtual = 600, .bits_per_pixel = 8, .pixclock = 25000, .left_margin = 88, .right_margin = 40, .upper_margin = 23, .lower_margin = 1, .hsync_len = 128, .vsync_len = 4, .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, .vmode = FB_VMODE_NONINTERLACED};static void savage_enable_mmio(struct savagefb_par *par){ unsigned char val; DBG("savage_enable_mmio\n"); val = vga_in8(0x3c3, par); vga_out8(0x3c3, val | 0x01, par); val = vga_in8(0x3cc, par); vga_out8(0x3c2, val | 0x01, par); if (par->chip >= S3_SAVAGE4) { vga_out8(0x3d4, 0x40, par); val = vga_in8(0x3d5, par); vga_out8(0x3d5, val | 1, par); }}static void savage_disable_mmio(struct savagefb_par *par){ unsigned char val; DBG("savage_disable_mmio\n"); if (par->chip >= S3_SAVAGE4) { vga_out8(0x3d4, 0x40, par); val = vga_in8(0x3d5, par); vga_out8(0x3d5, val | 1, par); }}static int __devinit savage_map_mmio(struct fb_info *info){ struct savagefb_par *par = info->par; DBG("savage_map_mmio"); if (S3_SAVAGE3D_SERIES(par->chip)) par->mmio.pbase = pci_resource_start(par->pcidev, 0) + SAVAGE_NEWMMIO_REGBASE_S3; else par->mmio.pbase = pci_resource_start(par->pcidev, 0) + SAVAGE_NEWMMIO_REGBASE_S4; par->mmio.len = SAVAGE_NEWMMIO_REGSIZE; par->mmio.vbase = ioremap(par->mmio.pbase, par->mmio.len); if (!par->mmio.vbase) { printk("savagefb: unable to map memory mapped IO\n"); return -ENOMEM; } else printk(KERN_INFO "savagefb: mapped io at %p\n", par->mmio.vbase); info->fix.mmio_start = par->mmio.pbase; info->fix.mmio_len = par->mmio.len; par->bci_base = (u32 __iomem *)(par->mmio.vbase + BCI_BUFFER_OFFSET); par->bci_ptr = 0; savage_enable_mmio(par); return 0;}static void savage_unmap_mmio(struct fb_info *info){ struct savagefb_par *par = info->par; DBG("savage_unmap_mmio"); savage_disable_mmio(par); if (par->mmio.vbase) { iounmap(par->mmio.vbase); par->mmio.vbase = NULL; }}static int __devinit savage_map_video(struct fb_info *info, int video_len){ struct savagefb_par *par = info->par; int resource; DBG("savage_map_video"); if (S3_SAVAGE3D_SERIES(par->chip)) resource = 0; else resource = 1; par->video.pbase = pci_resource_start(par->pcidev, resource); par->video.len = video_len; par->video.vbase = ioremap(par->video.pbase, par->video.len); if (!par->video.vbase) { printk("savagefb: unable to map screen memory\n"); return -ENOMEM; } else printk(KERN_INFO "savagefb: mapped framebuffer at %p, " "pbase == %x\n", par->video.vbase, par->video.pbase); info->fix.smem_start = par->video.pbase; info->fix.smem_len = par->video.len - par->cob_size; info->screen_base = par->video.vbase;#ifdef CONFIG_MTRR par->video.mtrr = mtrr_add(par->video.pbase, video_len, MTRR_TYPE_WRCOMB, 1);#endif /* Clear framebuffer, it's all white in memory after boot */ memset_io(par->video.vbase, 0, par->video.len); return 0;}static void savage_unmap_video(struct fb_info *info){ struct savagefb_par *par = info->par; DBG("savage_unmap_video"); if (par->video.vbase) {#ifdef CONFIG_MTRR mtrr_del(par->video.mtrr, par->video.pbase, par->video.len);#endif iounmap(par->video.vbase); par->video.vbase = NULL; info->screen_base = NULL; }}static int savage_init_hw(struct savagefb_par *par){ unsigned char config1, m, n, n1, n2, sr8, cr3f, cr66 = 0, tmp; static unsigned char RamSavage3D[] = { 8, 4, 4, 2 }; static unsigned char RamSavage4[] = { 2, 4, 8, 12, 16, 32, 64, 32 }; static unsigned char RamSavageMX[] = { 2, 8, 4, 16, 8, 16, 4, 16 }; static unsigned char RamSavageNB[] = { 0, 2, 4, 8, 16, 32, 2, 2 }; int videoRam, videoRambytes, dvi; DBG("savage_init_hw"); /* unprotect CRTC[0-7] */ vga_out8(0x3d4, 0x11, par); tmp = vga_in8(0x3d5, par); vga_out8(0x3d5, tmp & 0x7f, par); /* unlock extended regs */ vga_out16(0x3d4, 0x4838, par); vga_out16(0x3d4, 0xa039, par); vga_out16(0x3c4, 0x0608, par); vga_out8(0x3d4, 0x40, par); tmp = vga_in8(0x3d5, par); vga_out8(0x3d5, tmp & ~0x01, par); /* unlock sys regs */ vga_out8(0x3d4, 0x38, par); vga_out8(0x3d5, 0x48, par); /* Unlock system registers. */ vga_out16(0x3d4, 0x4838, par); /* Next go on to detect amount of installed ram */ vga_out8(0x3d4, 0x36, par); /* for register CR36 (CONFG_REG1), */ config1 = vga_in8(0x3d5, par); /* get amount of vram installed */ /* Compute the amount of video memory and offscreen memory. */ switch (par->chip) { case S3_SAVAGE3D: videoRam = RamSavage3D[(config1 & 0xC0) >> 6 ] * 1024; break; case S3_SAVAGE4: /* * The Savage4 has one ugly special case to consider. On * systems with 4 banks of 2Mx32 SDRAM, the BIOS says 4MB * when it really means 8MB. Why do it the same when you * can do it different... */ vga_out8(0x3d4, 0x68, par); /* memory control 1 */ if ((vga_in8(0x3d5, par) & 0xC0) == (0x01 << 6)) RamSavage4[1] = 8; /*FALLTHROUGH*/ case S3_SAVAGE2000: videoRam = RamSavage4[(config1 & 0xE0) >> 5] * 1024; break; case S3_SAVAGE_MX: case S3_SUPERSAVAGE: videoRam = RamSavageMX[(config1 & 0x0E) >> 1] * 1024; break; case S3_PROSAVAGE: videoRam = RamSavageNB[(config1 & 0xE0) >> 5] * 1024; break; default: /* How did we get here? */ videoRam = 0; break; } videoRambytes = videoRam * 1024; printk(KERN_INFO "savagefb: probed videoram: %dk\n", videoRam); /* reset graphics engine to avoid memory corruption */ vga_out8(0x3d4, 0x66, par); cr66 = vga_in8(0x3d5, par); vga_out8(0x3d5, cr66 | 0x02, par); udelay(10000); vga_out8(0x3d4, 0x66, par); vga_out8(0x3d5, cr66 & ~0x02, par); /* clear reset flag */ udelay(10000); /* * reset memory interface, 3D engine, AGP master, PCI master, * master engine unit, motion compensation/LPB */ vga_out8(0x3d4, 0x3f, par); cr3f = vga_in8(0x3d5, par); vga_out8(0x3d5, cr3f | 0x08, par); udelay(10000); vga_out8(0x3d4, 0x3f, par); vga_out8(0x3d5, cr3f & ~0x08, par); /* clear reset flags */ udelay(10000); /* Savage ramdac speeds */ par->numClocks = 4; par->clock[0] = 250000; par->clock[1] = 250000; par->clock[2] = 220000; par->clock[3] = 220000; /* detect current mclk */ vga_out8(0x3c4, 0x08, par); sr8 = vga_in8(0x3c5, par); vga_out8(0x3c5, 0x06, par); vga_out8(0x3c4, 0x10, par); n = vga_in8(0x3c5, par); vga_out8(0x3c4, 0x11, par); m = vga_in8(0x3c5, par); vga_out8(0x3c4, 0x08, par); vga_out8(0x3c5, sr8, par); m &= 0x7f; n1 = n & 0x1f; n2 = (n >> 5) & 0x03; par->MCLK = ((1431818 * (m+2)) / (n1+2) / (1 << n2) + 50) / 100; printk(KERN_INFO "savagefb: Detected current MCLK value of %d kHz\n", par->MCLK); /* check for DVI/flat panel */ dvi = 0; if (par->chip == S3_SAVAGE4) { unsigned char sr30 = 0x00; vga_out8(0x3c4, 0x30, par); /* clear bit 1 */ vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x02, par); sr30 = vga_in8(0x3c5, par); if (sr30 & 0x02 /*0x04 */) { dvi = 1; printk("savagefb: Digital Flat Panel Detected\n"); } } if (S3_SAVAGE_MOBILE_SERIES(par->chip) && !par->crtonly) par->display_type = DISP_LCD; else if (dvi || (par->chip == S3_SAVAGE4 && par->dvi)) par->display_type = DISP_DFP; else par->display_type = DISP_CRT; /* Check LCD panel parrmation */ if (par->display_type == DISP_LCD) { unsigned char cr6b = VGArCR(0x6b, par); int panelX = (VGArSEQ(0x61, par) + ((VGArSEQ(0x66, par) & 0x02) << 7) + 1) * 8; int panelY = (VGArSEQ(0x69, par) + ((VGArSEQ(0x6e, par) & 0x70) << 4) + 1); char * sTechnology = "Unknown"; /* OK, I admit it. I don't know how to limit the max dot clock * for LCD panels of various sizes. I thought I copied the * formula from the BIOS, but many users have parrmed me of * my folly. * * Instead, I'll abandon any attempt to automatically limit the * clock, and add an LCDClock option to XF86Config. Some day, * I should come back to this. */ enum ACTIVE_DISPLAYS { /* These are the bits in CR6B */ ActiveCRT = 0x01, ActiveLCD = 0x02, ActiveTV = 0x04, ActiveCRT2 = 0x20, ActiveDUO = 0x80 }; if ((VGArSEQ(0x39, par) & 0x03) == 0) { sTechnology = "TFT"; } else if ((VGArSEQ(0x30, par) & 0x01) == 0) { sTechnology = "DSTN"; } else { sTechnology = "STN"; } printk(KERN_INFO "savagefb: %dx%d %s LCD panel detected %s\n", panelX, panelY, sTechnology, cr6b & ActiveLCD ? "and active" : "but not active");
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -