📄 cg6.c
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} if (width) { u32 val; sbus_writel(y, &fbc->y0); sbus_writel(x, &fbc->x0); sbus_writel(x + width - 1, &fbc->x1); if (width <= 8) { val = (u32) data[0] << 24; data += 1; } else if (width <= 16) { val = ((u32) data[0] << 24) | ((u32) data[1] << 16); data += 2; } else { val = ((u32) data[0] << 24) | ((u32) data[1] << 16) | ((u32) data[2] << 8); data += 3; } sbus_writel(val, &fbc->font); } y += 1; x = image->dx; } spin_unlock_irqrestore(&par->lock, flags);}/** * cg6_setcolreg - Sets a color register. * * @regno: boolean, 0 copy local, 1 get_user() function * @red: frame buffer colormap structure * @green: The green value which can be up to 16 bits wide * @blue: The blue value which can be up to 16 bits wide. * @transp: If supported the alpha value which can be up to 16 bits wide. * @info: frame buffer info structure */static int cg6_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue, unsigned transp, struct fb_info *info){ struct cg6_par *par = (struct cg6_par *)info->par; struct bt_regs __iomem *bt = par->bt; unsigned long flags; if (regno >= 256) return 1; red >>= 8; green >>= 8; blue >>= 8; spin_lock_irqsave(&par->lock, flags); sbus_writel((u32)regno << 24, &bt->addr); sbus_writel((u32)red << 24, &bt->color_map); sbus_writel((u32)green << 24, &bt->color_map); sbus_writel((u32)blue << 24, &bt->color_map); spin_unlock_irqrestore(&par->lock, flags); return 0;}/** * cg6_blank - Blanks the display. * * @blank_mode: the blank mode we want. * @info: frame buffer structure that represents a single frame buffer */static int cg6_blank(int blank, struct fb_info *info){ struct cg6_par *par = (struct cg6_par *)info->par; struct cg6_thc __iomem *thc = par->thc; unsigned long flags; u32 val; spin_lock_irqsave(&par->lock, flags); val = sbus_readl(&thc->thc_misc); switch (blank) { case FB_BLANK_UNBLANK: /* Unblanking */ val |= CG6_THC_MISC_VIDEO; par->flags &= ~CG6_FLAG_BLANKED; break; case FB_BLANK_NORMAL: /* Normal blanking */ case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */ case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */ case FB_BLANK_POWERDOWN: /* Poweroff */ val &= ~CG6_THC_MISC_VIDEO; par->flags |= CG6_FLAG_BLANKED; break; } sbus_writel(val, &thc->thc_misc); spin_unlock_irqrestore(&par->lock, flags); return 0;}static struct sbus_mmap_map cg6_mmap_map[] = { { .voff = CG6_FBC, .poff = CG6_FBC_OFFSET, .size = PAGE_SIZE }, { .voff = CG6_TEC, .poff = CG6_TEC_OFFSET, .size = PAGE_SIZE }, { .voff = CG6_BTREGS, .poff = CG6_BROOKTREE_OFFSET, .size = PAGE_SIZE }, { .voff = CG6_FHC, .poff = CG6_FHC_OFFSET, .size = PAGE_SIZE }, { .voff = CG6_THC, .poff = CG6_THC_OFFSET, .size = PAGE_SIZE }, { .voff = CG6_ROM, .poff = CG6_ROM_OFFSET, .size = 0x10000 }, { .voff = CG6_RAM, .poff = CG6_RAM_OFFSET, .size = SBUS_MMAP_FBSIZE(1) }, { .voff = CG6_DHC, .poff = CG6_DHC_OFFSET, .size = 0x40000 }, { .size = 0 }};static int cg6_mmap(struct fb_info *info, struct vm_area_struct *vma){ struct cg6_par *par = (struct cg6_par *)info->par; return sbusfb_mmap_helper(cg6_mmap_map, par->physbase, par->fbsize, par->which_io, vma);}static int cg6_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg){ struct cg6_par *par = (struct cg6_par *)info->par; return sbusfb_ioctl_helper(cmd, arg, info, FBTYPE_SUNFAST_COLOR, 8, par->fbsize);}/* * Initialisation */static void __devinit cg6_init_fix(struct fb_info *info, int linebytes){ struct cg6_par *par = (struct cg6_par *)info->par; const char *cg6_cpu_name, *cg6_card_name; u32 conf; conf = sbus_readl(par->fhc); switch (conf & CG6_FHC_CPU_MASK) { case CG6_FHC_CPU_SPARC: cg6_cpu_name = "sparc"; break; case CG6_FHC_CPU_68020: cg6_cpu_name = "68020"; break; default: cg6_cpu_name = "i386"; break; }; if (((conf >> CG6_FHC_REV_SHIFT) & CG6_FHC_REV_MASK) >= 11) { if (par->fbsize <= 0x100000) cg6_card_name = "TGX"; else cg6_card_name = "TGX+"; } else { if (par->fbsize <= 0x100000) cg6_card_name = "GX"; else cg6_card_name = "GX+"; } sprintf(info->fix.id, "%s %s", cg6_card_name, cg6_cpu_name); info->fix.id[sizeof(info->fix.id) - 1] = 0; info->fix.type = FB_TYPE_PACKED_PIXELS; info->fix.visual = FB_VISUAL_PSEUDOCOLOR; info->fix.line_length = linebytes; info->fix.accel = FB_ACCEL_SUN_CGSIX;}/* Initialize Brooktree DAC */static void __devinit cg6_bt_init(struct cg6_par *par){ struct bt_regs __iomem *bt = par->bt; sbus_writel(0x04 << 24, &bt->addr); /* color planes */ sbus_writel(0xff << 24, &bt->control); sbus_writel(0x05 << 24, &bt->addr); sbus_writel(0x00 << 24, &bt->control); sbus_writel(0x06 << 24, &bt->addr); /* overlay plane */ sbus_writel(0x73 << 24, &bt->control); sbus_writel(0x07 << 24, &bt->addr); sbus_writel(0x00 << 24, &bt->control);}static void __devinit cg6_chip_init(struct fb_info *info){ struct cg6_par *par = (struct cg6_par *)info->par; struct cg6_tec __iomem *tec = par->tec; struct cg6_fbc __iomem *fbc = par->fbc; struct cg6_thc __iomem *thc = par->thc; u32 rev, conf, mode; int i; /* Hide the cursor. */ sbus_writel(CG6_THC_CURSOFF, &thc->thc_cursxy); /* Turn off stuff in the Transform Engine. */ sbus_writel(0, &tec->tec_matrix); sbus_writel(0, &tec->tec_clip); sbus_writel(0, &tec->tec_vdc); /* Take care of bugs in old revisions. */ rev = (sbus_readl(par->fhc) >> CG6_FHC_REV_SHIFT) & CG6_FHC_REV_MASK; if (rev < 5) { conf = (sbus_readl(par->fhc) & CG6_FHC_RES_MASK) | CG6_FHC_CPU_68020 | CG6_FHC_TEST | (11 << CG6_FHC_TEST_X_SHIFT) | (11 << CG6_FHC_TEST_Y_SHIFT); if (rev < 2) conf |= CG6_FHC_DST_DISABLE; sbus_writel(conf, par->fhc); } /* Set things in the FBC. Bad things appear to happen if we do * back to back store/loads on the mode register, so copy it * out instead. */ mode = sbus_readl(&fbc->mode); do { i = sbus_readl(&fbc->s); } while (i & 0x10000000); mode &= ~(CG6_FBC_BLIT_MASK | CG6_FBC_MODE_MASK | CG6_FBC_DRAW_MASK | CG6_FBC_BWRITE0_MASK | CG6_FBC_BWRITE1_MASK | CG6_FBC_BREAD_MASK | CG6_FBC_BDISP_MASK); mode |= (CG6_FBC_BLIT_SRC | CG6_FBC_MODE_COLOR8 | CG6_FBC_DRAW_RENDER | CG6_FBC_BWRITE0_ENABLE | CG6_FBC_BWRITE1_DISABLE | CG6_FBC_BREAD_0 | CG6_FBC_BDISP_0); sbus_writel(mode, &fbc->mode); sbus_writel(0, &fbc->clip); sbus_writel(0, &fbc->offx); sbus_writel(0, &fbc->offy); sbus_writel(0, &fbc->clipminx); sbus_writel(0, &fbc->clipminy); sbus_writel(info->var.xres - 1, &fbc->clipmaxx); sbus_writel(info->var.yres - 1, &fbc->clipmaxy);}static void cg6_unmap_regs(struct of_device *op, struct fb_info *info, struct cg6_par *par){ if (par->fbc) of_iounmap(&op->resource[0], par->fbc, 4096); if (par->tec) of_iounmap(&op->resource[0], par->tec, sizeof(struct cg6_tec)); if (par->thc) of_iounmap(&op->resource[0], par->thc, sizeof(struct cg6_thc)); if (par->bt) of_iounmap(&op->resource[0], par->bt, sizeof(struct bt_regs)); if (par->fhc) of_iounmap(&op->resource[0], par->fhc, sizeof(u32)); if (info->screen_base) of_iounmap(&op->resource[0], info->screen_base, par->fbsize);}static int __devinit cg6_probe(struct of_device *op, const struct of_device_id *match){ struct device_node *dp = op->node; struct fb_info *info; struct cg6_par *par; int linebytes, err; int dblbuf; info = framebuffer_alloc(sizeof(struct cg6_par), &op->dev); err = -ENOMEM; if (!info) goto out_err; par = info->par; spin_lock_init(&par->lock); par->physbase = op->resource[0].start; par->which_io = op->resource[0].flags & IORESOURCE_BITS; sbusfb_fill_var(&info->var, dp, 8); info->var.red.length = 8; info->var.green.length = 8; info->var.blue.length = 8; linebytes = of_getintprop_default(dp, "linebytes", info->var.xres); par->fbsize = PAGE_ALIGN(linebytes * info->var.yres); dblbuf = of_getintprop_default(dp, "dblbuf", 0); if (dblbuf) par->fbsize *= 4; par->fbc = of_ioremap(&op->resource[0], CG6_FBC_OFFSET, 4096, "cgsix fbc"); par->tec = of_ioremap(&op->resource[0], CG6_TEC_OFFSET, sizeof(struct cg6_tec), "cgsix tec"); par->thc = of_ioremap(&op->resource[0], CG6_THC_OFFSET, sizeof(struct cg6_thc), "cgsix thc"); par->bt = of_ioremap(&op->resource[0], CG6_BROOKTREE_OFFSET, sizeof(struct bt_regs), "cgsix dac"); par->fhc = of_ioremap(&op->resource[0], CG6_FHC_OFFSET, sizeof(u32), "cgsix fhc"); info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT | FBINFO_READS_FAST; info->fbops = &cg6_ops; info->screen_base = of_ioremap(&op->resource[0], CG6_RAM_OFFSET, par->fbsize, "cgsix ram"); if (!par->fbc || !par->tec || !par->thc || !par->bt || !par->fhc || !info->screen_base) goto out_unmap_regs; info->var.accel_flags = FB_ACCELF_TEXT; cg6_bt_init(par); cg6_chip_init(info); cg6_blank(FB_BLANK_UNBLANK, info); if (fb_alloc_cmap(&info->cmap, 256, 0)) goto out_unmap_regs; fb_set_cmap(&info->cmap, info); cg6_init_fix(info, linebytes); err = register_framebuffer(info); if (err < 0) goto out_dealloc_cmap; dev_set_drvdata(&op->dev, info); printk(KERN_INFO "%s: CGsix [%s] at %lx:%lx\n", dp->full_name, info->fix.id, par->which_io, par->physbase); return 0;out_dealloc_cmap: fb_dealloc_cmap(&info->cmap);out_unmap_regs: cg6_unmap_regs(op, info, par);out_err: return err;}static int __devexit cg6_remove(struct of_device *op){ struct fb_info *info = dev_get_drvdata(&op->dev); struct cg6_par *par = info->par; unregister_framebuffer(info); fb_dealloc_cmap(&info->cmap); cg6_unmap_regs(op, info, par); framebuffer_release(info); dev_set_drvdata(&op->dev, NULL); return 0;}static const struct of_device_id cg6_match[] = { { .name = "cgsix", }, { .name = "cgthree+", }, {},};MODULE_DEVICE_TABLE(of, cg6_match);static struct of_platform_driver cg6_driver = { .name = "cg6", .match_table = cg6_match, .probe = cg6_probe, .remove = __devexit_p(cg6_remove),};static int __init cg6_init(void){ if (fb_get_options("cg6fb", NULL)) return -ENODEV; return of_register_driver(&cg6_driver, &of_bus_type);}static void __exit cg6_exit(void){ of_unregister_driver(&cg6_driver);}module_init(cg6_init);module_exit(cg6_exit);MODULE_DESCRIPTION("framebuffer driver for CGsix chipsets");MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");MODULE_VERSION("2.0");MODULE_LICENSE("GPL");
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