lcd.c

Linux环境下视频显示卡设备的驱动程序源代码

			viafb_vt1636_patch_skew_on_vt3364(plvds_setting_info,
						    plvds_chip_info);
			break;
		case UNICHROME_P4M890:
			viafb_vt1636_patch_skew_on_vt3327(plvds_setting_info,
						    plvds_chip_info);
			break;
		}
	}
}
static void lcd_patch_skew_dvp1(struct lvds_setting_information
			 *plvds_setting_info,
			 struct lvds_chip_information *plvds_chip_info)
{
	if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
		switch (viaparinfo->chip_info->gfx_chip_name) {
		case UNICHROME_CX700:
			viafb_vt1636_patch_skew_on_vt3324(plvds_setting_info,
						    plvds_chip_info);
			break;
		}
	}
}
static void lcd_patch_skew(struct lvds_setting_information
	*plvds_setting_info, struct lvds_chip_information *plvds_chip_info)
{
	DEBUG_MSG(KERN_INFO "lcd_patch_skew\n");
	switch (plvds_chip_info->output_interface) {
	case INTERFACE_DVP0:
		lcd_patch_skew_dvp0(plvds_setting_info, plvds_chip_info);
		break;
	case INTERFACE_DVP1:
		lcd_patch_skew_dvp1(plvds_setting_info, plvds_chip_info);
		break;
	case INTERFACE_DFP_LOW:
		if (UNICHROME_P4M900 == viaparinfo->chip_info->gfx_chip_name) {
			viafb_write_reg_mask(CR99, VIACR, 0x08,
				       BIT0 + BIT1 + BIT2 + BIT3);
		}
		break;
	}
}

/* LCD Set Mode */
void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
		  struct lvds_setting_information *plvds_setting_info,
		  struct lvds_chip_information *plvds_chip_info)
{
	int video_index = plvds_setting_info->lcd_panel_size;
	int set_iga = plvds_setting_info->iga_path;
	int mode_bpp = plvds_setting_info->bpp;
	int viafb_load_reg_num = 0;
	int reg_value = 0;
	int set_hres, set_vres;
	int panel_hres, panel_vres;
	u32 pll_D_N;
	int offset;
	struct io_register *reg = NULL;
	struct display_timing mode_crt_reg, panel_crt_reg;
	struct crt_mode_table *panel_crt_table = NULL;
	struct VideoModeTable *vmode_tbl = NULL;

	DEBUG_MSG(KERN_INFO "viafb_lcd_set_mode!!\n");
	/* Get mode table */
	mode_crt_reg = mode_crt_table->crtc;
	/* Get panel table Pointer */
	vmode_tbl = viafb_get_modetbl_pointer(video_index);
	panel_crt_table = vmode_tbl->crtc;
	panel_crt_reg = panel_crt_table->crtc;
	DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n");
	set_hres = plvds_setting_info->h_active;
	set_vres = plvds_setting_info->v_active;
	panel_hres = plvds_setting_info->lcd_panel_hres;
	panel_vres = plvds_setting_info->lcd_panel_vres;
	if (VT1636_LVDS == plvds_chip_info->lvds_chip_name)
		viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info);
	plvds_setting_info->vclk = panel_crt_table->clk;
	if (set_iga == IGA1) {
		/* IGA1 doesn't have LCD scaling, so set it as centering. */
		viafb_load_crtc_timing(lcd_centering_timging
				 (mode_crt_reg, panel_crt_reg), IGA1);
	} else {
		/* Expansion */
		if ((plvds_setting_info->display_method ==
		     LCD_EXPANDSION) & ((set_hres != panel_hres)
					|| (set_vres != panel_vres))) {
			/* expansion timing IGA2 loaded panel set timing*/
			viafb_load_crtc_timing(panel_crt_reg, IGA2);
			DEBUG_MSG(KERN_INFO "viafb_load_crtc_timing!!\n");
			load_lcd_scaling(set_hres, set_vres, panel_hres,
					 panel_vres);
			DEBUG_MSG(KERN_INFO "load_lcd_scaling!!\n");
		} else {	/* Centering */
			/* centering timing IGA2 always loaded panel
			   and mode releative timing */
			viafb_load_crtc_timing(lcd_centering_timging
					 (mode_crt_reg, panel_crt_reg), IGA2);
			viafb_write_reg_mask(CR79, VIACR, 0x00,
				BIT0 + BIT1 + BIT2);
			/* LCD scaling disabled */
		}
	}

	if (set_iga == IGA1_IGA2) {
		load_crtc_shadow_timing(mode_crt_reg, panel_crt_reg);
		/* Fill shadow registers */

		switch (plvds_setting_info->lcd_panel_id) {
		case LCD_PANEL_ID0_640X480:
			offset = 80;
			break;
		case LCD_PANEL_ID1_800X600:
		case LCD_PANEL_IDA_800X480:
			offset = 110;
			break;
		case LCD_PANEL_ID2_1024X768:
			offset = 150;
			break;
		case LCD_PANEL_ID3_1280X768:
		case LCD_PANEL_ID4_1280X1024:
		case LCD_PANEL_ID5_1400X1050:
		case LCD_PANEL_ID9_1280X800:
			offset = 190;
			break;
		case LCD_PANEL_ID6_1600X1200:
			offset = 250;
			break;
		case LCD_PANEL_ID7_1366X768:
		case LCD_PANEL_IDB_1360X768:
			offset = 212;
			break;
		default:
			offset = 140;
			break;
		}

		/* Offset for simultaneous */
		reg_value = offset;
		viafb_load_reg_num = offset_reg.iga2_offset_reg.reg_num;
		reg = offset_reg.iga2_offset_reg.reg;
		viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
		DEBUG_MSG(KERN_INFO "viafb_load_reg!!\n");
		viafb_load_fetch_count_reg(set_hres, 4, IGA2);
		/* Fetch count for simultaneous */
	} else {		/* SAMM */
		/* Offset for IGA2 only */
		viafb_load_offset_reg(set_hres, mode_bpp / 8, set_iga);
		/* Fetch count for IGA2 only */
		viafb_load_fetch_count_reg(set_hres, mode_bpp / 8, set_iga);

		if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
		    && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
			viafb_load_FIFO_reg(set_iga, set_hres, set_vres);

		viafb_set_color_depth(mode_bpp / 8, set_iga);
	}

	fill_lcd_format();

	pll_D_N = viafb_get_clk_value(panel_crt_table[0].clk);
	DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N);
	viafb_set_vclock(pll_D_N, set_iga);

	viafb_set_output_path(DEVICE_LCD, set_iga,
		plvds_chip_info->output_interface);
	lcd_patch_skew(plvds_setting_info, plvds_chip_info);

	/* If K8M800, enable LCD Prefetch Mode. */
	if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
	    || (UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name))
		viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0);

	load_lcd_patch_regs(set_hres, set_vres,
			    plvds_setting_info->lcd_panel_id, set_iga);

	DEBUG_MSG(KERN_INFO "load_lcd_patch_regs!!\n");

	/* Patch for non 32bit alignment mode */
	via_pitch_alignment_patch_lcd(plvds_setting_info, plvds_chip_info);
}

static void integrated_lvds_disable(struct lvds_setting_information
			     *plvds_setting_info,
			     struct lvds_chip_information *plvds_chip_info)
{
	bool turn_off_first_powersequence = false;
	bool turn_off_second_powersequence = false;
	if (INTERFACE_LVDS0LVDS1 == plvds_chip_info->output_interface)
		turn_off_first_powersequence = true;
	if (INTERFACE_LVDS0 == plvds_chip_info->output_interface)
		turn_off_first_powersequence = true;
	if (INTERFACE_LVDS1 == plvds_chip_info->output_interface)
		turn_off_second_powersequence = true;
	if (turn_off_second_powersequence) {
		/* Use second power sequence control: */

		/* Turn off power sequence. */
		viafb_write_reg_mask(CRD4, VIACR, 0, BIT1);

		/* Turn off back light. */
		viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7);
	}
	if (turn_off_first_powersequence) {
		/* Use first power sequence control: */

		/* Turn off power sequence. */
		viafb_write_reg_mask(CR6A, VIACR, 0, BIT3);

		/* Turn off back light. */
		viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7);
	}

	/* Turn DFP High/Low Pad off. */
	viafb_write_reg_mask(SR2A, VIASR, 0, BIT0 + BIT1 + BIT2 + BIT3);

	/* Power off LVDS channel. */
	switch (plvds_chip_info->output_interface) {
	case INTERFACE_LVDS0:
		{
			viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7);
			break;
		}

	case INTERFACE_LVDS1:
		{
			viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6);
			break;
		}

	case INTERFACE_LVDS0LVDS1:
		{
			viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7);
			break;
		}
	}
}

static void integrated_lvds_enable(struct lvds_setting_information
			    *plvds_setting_info,
			    struct lvds_chip_information *plvds_chip_info)
{
	bool turn_on_first_powersequence = false;
	bool turn_on_second_powersequence = false;

	DEBUG_MSG(KERN_INFO "integrated_lvds_enable, out_interface:%d\n",
		  plvds_chip_info->output_interface);
	if (plvds_setting_info->lcd_mode == LCD_SPWG)
		viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);
	 else
		viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);
	if (INTERFACE_LVDS0LVDS1 == plvds_chip_info->output_interface)
		turn_on_first_powersequence = true;
	if (INTERFACE_LVDS0 == plvds_chip_info->output_interface)
		turn_on_first_powersequence = true;
	if (INTERFACE_LVDS1 == plvds_chip_info->output_interface)
		turn_on_second_powersequence = true;

	if (turn_on_second_powersequence) {
		/* Use second power sequence control: */

		/* Use hardware control power sequence. */
		viafb_write_reg_mask(CRD3, VIACR, 0, BIT0);

		/* Turn on back light. */
		viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7);

		/* Turn on hardware power sequence. */
		viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1);
	}
	if (turn_on_first_powersequence) {
		/* Use first power sequence control: */

		/* Use hardware control power sequence. */
		viafb_write_reg_mask(CR91, VIACR, 0, BIT0);

		/* Turn on back light. */
		viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7);

		/* Turn on hardware power sequence. */
		viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
	}

	/* Turn DFP High/Low pad on. */
	viafb_write_reg_mask(SR2A, VIASR, 0x0F, BIT0 + BIT1 + BIT2 + BIT3);

	/* Power on LVDS channel. */
	switch (plvds_chip_info->output_interface) {
	case INTERFACE_LVDS0:
		{
			viafb_write_reg_mask(CRD2, VIACR, 0, BIT7);
			break;
		}

	case INTERFACE_LVDS1:
		{
			viafb_write_reg_mask(CRD2, VIACR, 0, BIT6);
			break;
		}

	case INTERFACE_LVDS0LVDS1:
		{
			viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7);
			break;
		}
	}
}

void viafb_lcd_disable(void)
{

	if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
		lcd_powersequence_off();
		/* DI1 pad off */
		viafb_write_reg_mask(SR1E, VIASR, 0x00, 0x30);
	} else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
		if (viafb_LCD2_ON
		    && (INTEGRATED_LVDS ==
			viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
			integrated_lvds_disable(viaparinfo->lvds_setting_info,
				&viaparinfo->chip_info->lvds_chip_info2);
		if (INTEGRATED_LVDS ==
			viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
			integrated_lvds_disable(viaparinfo->lvds_setting_info,
				&viaparinfo->chip_info->lvds_chip_info);
		if (VT1636_LVDS == viaparinfo->chip_info->
			lvds_chip_info.lvds_chip_name)
			viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
				&viaparinfo->chip_info->lvds_chip_info);
	} else if (VT1636_LVDS ==
	viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
		viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
				    &viaparinfo->chip_info->lvds_chip_info);
	} else {
		/* DFP-HL pad off          */
		viafb_write_reg_mask(SR2A, VIASR, 0x00, 0x0F);
		/* Backlight off           */
		viafb_write_reg_mask(SR3D, VIASR, 0x00, 0x20);
		/* 24 bit DI data paht off */
		viafb_write_reg_mask(CR91, VIACR, 0x80, 0x80);
		/* Simultaneout disabled   */
		viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
	}

	/* Disable expansion bit   */
	viafb_write_reg_mask(CR79, VIACR, 0x00, 0x01);
	/* CRT path set to IGA1    */
	viafb_write_reg_mask(SR16, VIASR, 0x00, 0x40);
	/* Simultaneout disabled   */
	viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
	/* IGA2 path disabled      */
	viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x80);

}

void viafb_lcd_enable(void)
{
	if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
		/* DI1 pad on */
		viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30);
		lcd_powersequence_on();
	} else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
		if (viafb_LCD2_ON && (INTEGRATED_LVDS ==
			viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
			integrated_lvds_enable(viaparinfo->lvds_setting_info2, \
				&viaparinfo->chip_info->lvds_chip_info2);
		if (INTEGRATED_LVDS ==
			viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
			integrated_lvds_enable(viaparinfo->lvds_setting_info,
				&viaparinfo->chip_info->lvds_chip_info);
		if (VT1636_LVDS == viaparinfo->chip_info->
			lvds_chip_info.lvds_chip_name)
			viafb_enable_lvds_vt1636(viaparinfo->
			lvds_setting_info, &viaparinfo->chip_info->
			lvds_chip_info);
	} else if (VT1636_LVDS ==
	viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
		viafb_enable_lvds_vt1636(viaparinfo->lvds_setting_info,
				   &viaparinfo->chip_info->lvds_chip_info);
	} else {
		/* DFP-HL pad on           */
		viafb_write_reg_mask(SR2A, VIASR, 0x0F, 0x0F);
		/* Backlight on            */
		viafb_write_reg_mask(SR3D, VIASR, 0x20, 0x20);
		/* 24 bit DI data paht on  */
		viafb_write_reg_mask(CR91, VIACR, 0x00, 0x80);

		/* Set data source selection bit by iga path */
		if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
			/* DFP-H set to IGA1       */
			viafb_write_reg_mask(CR97, VIACR, 0x00, 0x10);
			/* DFP-L set to IGA1       */
			viafb_write_reg_mask(CR99, VIACR, 0x00, 0x10);
		} else {
			/* DFP-H set to IGA2       */
			viafb_write_reg_mask(CR97, VIACR, 0x10, 0x10);
			/* DFP-L set to IGA2       */
			viafb_write_reg_mask(CR99, VIACR, 0x10, 0x10);
		}
		/* LCD enabled             */
		viafb_write_reg_mask(CR6A, VIACR, 0x48, 0x48);
	}

	if ((viaparinfo->lvds_setting_info->iga_path == IGA1)
	    || (viaparinfo->lvds_setting_info->iga_path == IGA1_IGA2)) {
		/* CRT path set to IGA2    */
		viafb_write_reg_mask(SR16, VIASR, 0x40, 0x40);
		/* IGA2 path disabled      */
		viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x80);
		/* IGA2 path enabled       */
	} else {		/* IGA2 */
		viafb_write_reg_mask(CR6A, VIACR, 0x80, 0x80);
	}

}

static void lcd_powersequence_off(void)
{
	int i, mask, data;

	/* Software control power sequence */
	viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);

	for (i = 0; i < 3; i++) {
		mask = PowerSequenceOff[0][i];
		data = PowerSequenceOff[1][i] & mask;
		viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
		udelay(PowerSequenceOff[2][i]);
	}

	/* Disable LCD */
	viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x08);
}

static void lcd_powersequence_on(void)
{
	int i, mask, data;

	/* Software control power sequence */
	viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);

	/* Enable LCD */
	viafb_write_reg_mask(CR6A, VIACR, 0x08, 0x08);

	for (i = 0; i < 3; i++) {
		mask = PowerSequenceOn[0][i];
		data = PowerSequenceOn[1][i] & mask;
		viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
		udelay(PowerSequenceOn[2][i]);
	}

	udelay(1);
}

static void fill_lcd_format(void)
{
	u8 bdithering = 0, bdual = 0;