chuyenled.vhd

来自「fpga_begin dung cho lam quen」· VHDL 代码 · 共 19 行

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-- Company: 
-- Engineer: 
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-- Create Date:    21:19:01 11/10/2008 
-- Design Name: 
-- Module Name:    clock - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
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-- Dependencies: 
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-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
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