up_counter.vhd

up_counter code use VHDL for FPGA

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    23:49:24 03/17/2009 
-- Design Name: 
-- Module Name:    up_counter - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity up_counter is
      port (
          cout   :out std_logic_vector (7 downto 0); -- Output of the counter
          enable :in  std_logic;                     -- Enable counting
          clk    :in  std_logic;                     -- Input clock
          reset  :in  std_logic                      -- Input reset
      );
end entity;


architecture Behavioral of up_counter is
signal count :std_logic_vector (7 downto 0);
  begin
      process (clk, reset) begin
          if (reset = '1') then
              count <= (others=>'0');
          elsif (rising_edge(clk)) then
              if (enable = '1') then
                  count <= count + 1;
              end if;
          end if;
      end process;
      cout <= count;


end Behavioral;