f2407_c.h

永磁同步电机驱动控制

#define MSGID2H      ((PORT)0x7211)   /* CAN message ID for mailbox 2 *(upper 16 bits) */
#define MSGCTRL2     ((PORT)0x7212)   /* CAN RTR and DLC for mailbox 2 */
#define MBX2A        ((PORT)0x7214)   /* CAN 2 of 8 bytes of mailbox 2 */
#define MBX2B        ((PORT)0x7215)   /* CAN 2 of 8 bytes of mailbox 2 */
#define MBX2C        ((PORT)0x7216)   /* CAN 2 of 8 bytes of mailbox 2 */
#define MBX2D        ((PORT)0x7217)   /* CAN 2 of 8 bytes of mailbox 2 */

#define MSGID3L      ((PORT)0x7218)   /* CAN message ID for mailbox 3 *(lower 16 bits) */
#define MSGID3H      ((PORT)0x7219)   /* CAN message ID for mailbox 3 *(upper 16 bits) */
#define MSGCTRL3     ((PORT)0x721A)   /* CAN RTR and DLC for mailbox 3 */
#define MBX3A        ((PORT)0x721C)   /* CAN 2 of 8 bytes of mailbox 3 */
#define MBX3B        ((PORT)0x721D)   /* CAN 2 of 8 bytes of mailbox 3 */
#define MBX3C        ((PORT)0x721E)   /* CAN 2 of 8 bytes of mailbox 3 */
#define MBX3D        ((PORT)0x721F)   /* CAN 2 of 8 bytes of mailbox 3 */

#define MSGID4L      ((PORT)0x7220)   /* CAN message ID for mailbox 4 *(lower 16 bits) */
#define MSGID4H      ((PORT)0x7221)   /* CAN message ID for mailbox 4 *(upper 16 bits) */
#define MSGCTRL4     ((PORT)0x7222)   /* CAN RTR and DLC for mailbox 4 */
#define MBX4A        ((PORT)0x7224)   /* CAN 2 of 8 bytes of mailbox 4 */
#define MBX4B        ((PORT)0x7225)   /* CAN 2 of 8 bytes of mailbox 4 */
#define MBX4C        ((PORT)0x7226)   /* CAN 2 of 8 bytes of mailbox 4 */
#define MBX4D        ((PORT)0x7227)   /* CAN 2 of 8 bytes of mailbox 4 */

#define MSGID5L      ((PORT)0x7228)   /* CAN message ID for mailbox 5 *(lower 16 bits) */
#define MSGID5H      ((PORT)0x7229)   /* CAN message ID for mailbox 5 *(upper 16 bits) */
#define MSGCTRL5     ((PORT)0x722A)   /* CAN RTR and DLC for mailbox 5 */
#define MBX5A        ((PORT)0x722C)   /* CAN 2 of 8 bytes of mailbox 5 */
#define MBX5B        ((PORT)0x722D)   /* CAN 2 of 8 bytes of mailbox 5 */
#define MBX5C        ((PORT)0x722E)   /* CAN 2 of 8 bytes of mailbox 5 */
#define MBX5D        ((PORT)0x722F)   /* CAN 2 of 8 bytes of mailbox 5 */

/* Event Manager A *(EVA) registers */
#define GPTCONA      ((PORT)0x7400)   /* GP timer control reg A */
#define T1CNT        ((PORT)0x7401)   /* GP timer 1 counter reg */
#define T1CMPR       ((PORT)0x7402)   /* GP timer 1 compare reg */
#define T1PR         ((PORT)0x7403)   /* GP timer 1 period reg  */
#define T1CON        ((PORT)0x7404)   /* GP timer 1 control reg */
#define T2CNT        ((PORT)0x7405)   /* GP timer 2 counter reg */
#define T2CMPR       ((PORT)0x7406)   /* GP timer 2 compare reg */ 
#define T2PR         ((PORT)0x7407)   /* GP timer 2 period reg */
#define T2CON        ((PORT)0x7408)   /* GP timer 2 control reg */
#define COMCONA      ((PORT)0x7411)   /* Compare control reg A */
#define ACTRA        ((PORT)0x7413)   /* Compare action control reg A */
#define DBTCONA      ((PORT)0x7415)   /* Dead-band timer control reg A */
#define CMPR1        ((PORT)0x7417)   /* compare reg 1 */
#define CMPR2        ((PORT)0x7418)   /* compare reg 2 */ 
#define CMPR3        ((PORT)0x7419)   /* compare reg 3 */ 
#define CAPCONA      ((PORT)0x7420)   /* Capture control reg A */
#define CAPFIFOA     ((PORT)0x7422)   /* Capture FIFO status reg A */
#define CAP1FIFO     ((PORT)0x7423)   /* Capture Channel 1 FIFO top */
#define CAP2FIFO     ((PORT)0x7424)   /* Capture Channel 2 FIFO top */ 
#define CAP3FIFO     ((PORT)0x7425)   /* Capture Channel 3 FIFO top */ 
#define CAP1FBOT     ((PORT)0x7427)   /* Bottom reg of capture FIFO stack 1 */
#define CAP2FBOT     ((PORT)0x7427)   /* Bottom reg of capture FIFO stack 2 */ 
#define CAP3FBOT     ((PORT)0x7427)   /* Bottom reg of capture FIFO stack 3 */ 
#define EVAIMRA      ((PORT)0x742C)   /* EVA interrupt mask reg A */
#define EVAIMRB      ((PORT)0x742D)   /* EVA interrupt mask reg B */
#define EVAIMRC      ((PORT)0x742E)   /* EVA interrupt mask reg C */
#define EVAIFRA      ((PORT)0x742F)   /* EVA interrupt flag reg A */
#define EVAIFRB      ((PORT)0x7430)   /* EVA interrupt flag reg B */
#define EVAIFRC      ((PORT)0x7431)   /* EVA interrupt flag reg C */

/* Event Manager B *(EVB) registers */
#define GPTCONB      ((PORT)0x7500)   /* GP timer control reg B */
#define T3CNT        ((PORT)0x7501)   /* GP timer 3 counter reg */
#define T3CMPR       ((PORT)0x7502)   /* GP timer 3 compare reg */
#define T3PR         ((PORT)0x7503)   /* GP timer 3 period reg */
#define T3CON        ((PORT)0x7504)   /* GP timer 3 control reg */
#define T4CNT        ((PORT)0x7505)   /* GP timer 4 counter reg */
#define T4CMPR       ((PORT)0x7506)   /* GP timer 4 compare reg */
#define T4PR         ((PORT)0x7507)   /* GP timer 4 period reg */
#define T4CON        ((PORT)0x7508)   /* GP timer 4 control reg */
#define COMCONB      ((PORT)0x7511)   /* Compare control register B */
#define ACTRB        ((PORT)0x7513)   /* Compare action control register B */
#define DBTCONB      ((PORT)0x7515)   /* Dead-band timer control reg B */
#define CMPR4        ((PORT)0x7517)   /* Compare reg 4 */
#define CMPR5        ((PORT)0x7518)   /* Compare reg 5 */
#define CMPR6        ((PORT)0x7519)   /* Compare reg 6 */
#define CAPCONB      ((PORT)0x7520)   /* Capture control reg B */
#define CAPFIFOB     ((PORT)0x7522)   /* Capture FIFO status reg B */
#define CAP4FIFO     ((PORT)0x7523)   /* Capture channel 4 FIFO top */
#define CAP5FIFO     ((PORT)0x7524)   /* Capture channel 5 FIFO top */
#define CAP6FIFO     ((PORT)0x7525)   /* Capture channel 6 FIFO top */
#define CAP4FBOT     ((PORT)0x7527)   /* Bottom reg of capture FIFO stack 4 */
#define CAP5FBOT     ((PORT)0x7527)   /* Bottom reg of capture FIFO stack 5 */
#define CAP6FBOT     ((PORT)0x7527)   /* Bottom reg of capture FIFO stack 6 */
#define EVBIMRA      ((PORT)0x752C)   /* EVB interrupt mask reg A */
#define EVBIMRB      ((PORT)0x752D)   /* EVB interrupt mask reg B */
#define EVBIMRC      ((PORT)0x752E)   /* EVB interrupt mask reg C */
#define EVBIFRA      ((PORT)0x752F)   /* EVB interrupt flag reg A */
#define EVBIFRB      ((PORT)0x7530)   /* EVB interrupt flag reg B */
#define EVBIFRC      ((PORT)0x7531)   /* EVB interrupt flag reg C */


/*--------------------------------------------------------------------------*/
/* Bit codes for Test bit instruction *(BIT) *(15 Loads bit 0 into TC)        */
/*--------------------------------------------------------------------------*/
#define BIT15           0x0000              /* Bit Code for 15              */
#define BIT14           0x0001              /* Bit Code for 14*/
#define BIT13           0x0002              /* Bit Code for 13*/
#define BIT12           0x0003              /* Bit Code for 12*/
#define BIT11           0x0004              /* Bit Code for 11*/
#define BIT10           0x0005              /* Bit Code for 10*/
#define BIT9            0x0006              /* Bit Code for 9*/
#define BIT8            0x0007              /* Bit Code for 8*/
#define BIT7            0x0008              /* Bit Code for 7*/
#define BIT6            0x0009              /* Bit Code for 6*/
#define BIT5            0x000A              /* Bit Code for 5*/
#define BIT4            0x000B              /* Bit Code for 4*/
#define BIT3            0x000C              /* Bit Code for 3*/
#define BIT2            0x000D              /* Bit Code for 2*/
#define BIT1            0x000E              /* Bit Code for 1*/
#define BIT0            0x000F              /* Bit Code for 0*/

/*
--------------------------------------------------------------------------
Test mode on and off constants
--------------------------------------------------------------------------
*/

#define ABRPT           *(*(volatile int *)0x01f)          /* Analysis BreakPoint Register*/
#define PSA_ON          *(*(volatile int *)0x03A1)         /* Turn PSA and FEEDB on*/
#define PSA_FB_OFF      *(*(volatile int *)0x0121)         /* Turn PSA and FEEDB off*/
//#define USB_CS          ((PORT)0x0E000  /* EVB interrupt flag reg C */
//#define data            ((PORT)0x0300   /* EVB interrupt flag reg C */

/*--------------------------------------------------------------------------*/
/* I/O space mapped registers						    */
/*--------------------------------------------------------------------------*/
/* Wait-State Generator Control Reg */
#endif