output_design.tan.qmsg

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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 06 15:25:57 2006 " "Info: Processing started: Fri Oct 06 15:25:57 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off output_design -c output_design --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off output_design -c output_design --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "sout2 dec_out 8.686 ns Longest " "Info: Longest tpd from source pin \"sout2\" to destination pin \"dec_out\" is 8.686 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns sout2 1 PIN PIN_F16 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_F16; Fanout = 1; PIN Node = 'sout2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sout2 } "NODE_NAME" } } { "output_design.vhd" "" { Text "E:/viterbi213/output_design.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.706 ns) + CELL(0.366 ns) 5.159 ns dec_out~153 2 COMB LC_X7_Y30_N2 1 " "Info: 2: + IC(3.706 ns) + CELL(0.366 ns) = 5.159 ns; Loc. = LC_X7_Y30_N2; Fanout = 1; COMB Node = 'dec_out~153'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.072 ns" { sout2 dec_out~153 } "NODE_NAME" } } { "output_design.vhd" "" { Text "E:/viterbi213/output_design.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.123 ns) + CELL(2.404 ns) 8.686 ns dec_out 3 PIN PIN_F17 0 " "Info: 3: + IC(1.123 ns) + CELL(2.404 ns) = 8.686 ns; Loc. = PIN_F17; Fanout = 0; PIN Node = 'dec_out'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.527 ns" { dec_out~153 dec_out } "NODE_NAME" } } { "output_design.vhd" "" { Text "E:/viterbi213/output_design.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.857 ns ( 44.40 % ) " "Info: Total cell delay = 3.857 ns ( 44.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.829 ns ( 55.60 % ) " "Info: Total interconnect delay = 4.829 ns ( 55.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.686 ns" { sout2 dec_out~153 dec_out } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.686 ns" { sout2 sout2~out0 dec_out~153 dec_out } { 0.000ns 0.000ns 3.706ns 1.123ns } { 0.000ns 1.087ns 0.366ns 2.404ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 06 15:25:58 2006 " "Info: Processing ended: Fri Oct 06 15:25:58 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}