ceshi.tan.qmsg

以C语言和Java语言、嵌入式开发、算法实现为主

{ "Info" "ITDB_TSU_RESULT" "conv_213:inst\|df\[2\] inp clk 2.025 ns register " "Info: tsu for register \"conv_213:inst\|df\[2\]\" (data pin = \"inp\", clock pin = \"clk\") is 2.025 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.949 ns + Longest pin register " "Info: + Longest pin to register delay is 4.949 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns inp 1 PIN PIN_E19 1 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_E19; Fanout = 1; PIN Node = 'inp'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { inp } "NODE_NAME" } } { "ceshi.bdf" "" { Schematic "E:/viterbi213/ceshi.bdf" { { 256 24 192 272 "inp" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.176 ns) + CELL(0.539 ns) 4.949 ns conv_213:inst\|df\[2\] 2 REG LC_X1_Y30_N8 3 " "Info: 2: + IC(3.176 ns) + CELL(0.539 ns) = 4.949 ns; Loc. = LC_X1_Y30_N8; Fanout = 3; REG Node = 'conv_213:inst\|df\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.715 ns" { inp conv_213:inst|df[2] } "NODE_NAME" } } { "conv_213.vhd" "" { Text "E:/viterbi213/conv_213.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.773 ns ( 35.83 % ) " "Info: Total cell delay = 1.773 ns ( 35.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.176 ns ( 64.17 % ) " "Info: Total interconnect delay = 3.176 ns ( 64.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.949 ns" { inp conv_213:inst|df[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.949 ns" { inp inp~out0 conv_213:inst|df[2] } { 0.000ns 0.000ns 3.176ns } { 0.000ns 1.234ns 0.539ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "conv_213.vhd" "" { Text "E:/viterbi213/conv_213.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.934 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.934 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 5 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ceshi.bdf" "" { Schematic "E:/viterbi213/ceshi.bdf" { { 120 0 168 136 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.564 ns) + CELL(0.542 ns) 2.934 ns conv_213:inst\|df\[2\] 2 REG LC_X1_Y30_N8 3 " "Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N8; Fanout = 3; REG Node = 'conv_213:inst\|df\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.106 ns" { clk conv_213:inst|df[2] } "NODE_NAME" } } { "conv_213.vhd" "" { Text "E:/viterbi213/conv_213.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.69 % ) " "Info: Total cell delay = 1.370 ns ( 46.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.564 ns ( 53.31 % ) " "Info: Total interconnect delay = 1.564 ns ( 53.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.934 ns" { clk conv_213:inst|df[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.934 ns" { clk clk~out0 conv_213:inst|df[2] } { 0.000ns 0.000ns 1.564ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.949 ns" { inp conv_213:inst|df[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.949 ns" { inp inp~out0 conv_213:inst|df[2] } { 0.000ns 0.000ns 3.176ns } { 0.000ns 1.234ns 0.539ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.934 ns" { clk conv_213:inst|df[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.934 ns" { clk clk~out0 conv_213:inst|df[2] } { 0.000ns 0.000ns 1.564ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk outp\[1\] tr_dff2:inst1\|out_outp\[1\] 6.654 ns register " "Info: tco from clock \"clk\" to destination pin \"outp\[1\]\" through register \"tr_dff2:inst1\|out_outp\[1\]\" is 6.654 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.934 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.934 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 5 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ceshi.bdf" "" { Schematic "E:/viterbi213/ceshi.bdf" { { 120 0 168 136 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.564 ns) + CELL(0.542 ns) 2.934 ns tr_dff2:inst1\|out_outp\[1\] 2 REG LC_X1_Y30_N5 1 " "Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N5; Fanout = 1; REG Node = 'tr_dff2:inst1\|out_outp\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.106 ns" { clk tr_dff2:inst1|out_outp[1] } "NODE_NAME" } } { "tr_dff2.vhd" "" { Text "E:/viterbi213/tr_dff2.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.69 % ) " "Info: Total cell delay = 1.370 ns ( 46.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.564 ns ( 53.31 % ) " "Info: Total interconnect delay = 1.564 ns ( 53.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.934 ns" { clk tr_dff2:inst1|out_outp[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.934 ns" { clk clk~out0 tr_dff2:inst1|out_outp[1] } { 0.000ns 0.000ns 1.564ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "tr_dff2.vhd" "" { Text "E:/viterbi213/tr_dff2.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.564 ns + Longest register pin " "Info: + Longest register to pin delay is 3.564 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tr_dff2:inst1\|out_outp\[1\] 1 REG LC_X1_Y30_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y30_N5; Fanout = 1; REG Node = 'tr_dff2:inst1\|out_outp\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { tr_dff2:inst1|out_outp[1] } "NODE_NAME" } } { "tr_dff2.vhd" "" { Text "E:/viterbi213/tr_dff2.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.160 ns) + CELL(2.404 ns) 3.564 ns outp\[1\] 2 PIN PIN_M16 0 " "Info: 2: + IC(1.160 ns) + CELL(2.404 ns) = 3.564 ns; Loc. = PIN_M16; Fanout = 0; PIN Node = 'outp\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.564 ns" { tr_dff2:inst1|out_outp[1] outp[1] } "NODE_NAME" } } { "ceshi.bdf" "" { Schematic "E:/viterbi213/ceshi.bdf" { { 208 648 824 224 "outp\[1..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 67.45 % ) " "Info: Total cell delay = 2.404 ns ( 67.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.160 ns ( 32.55 % ) " "Info: Total interconnect delay = 1.160 ns ( 32.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.564 ns" { tr_dff2:inst1|out_outp[1] outp[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.564 ns" { tr_dff2:inst1|out_outp[1] outp[1] } { 0.000ns 1.160ns } { 0.000ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.934 ns" { clk tr_dff2:inst1|out_outp[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.934 ns" { clk clk~out0 tr_dff2:inst1|out_outp[1] } { 0.000ns 0.000ns 1.564ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.564 ns" { tr_dff2:inst1|out_outp[1] outp[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.564 ns" { tr_dff2:inst1|out_outp[1] outp[1] } { 0.000ns 1.160ns } { 0.000ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "conv_213:inst\|df\[2\] reset clk -1.616 ns register " "Info: th for register \"conv_213:inst\|df\[2\]\" (data pin = \"reset\", clock pin = \"clk\") is -1.616 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.934 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.934 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 5 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 5; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ceshi.bdf" "" { Schematic "E:/viterbi213/ceshi.bdf" { { 120 0 168 136 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.564 ns) + CELL(0.542 ns) 2.934 ns conv_213:inst\|df\[2\] 2 REG LC_X1_Y30_N8 3 " "Info: 2: + IC(1.564 ns) + CELL(0.542 ns) = 2.934 ns; Loc. = LC_X1_Y30_N8; Fanout = 3; REG Node = 'conv_213:inst\|df\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.106 ns" { clk conv_213:inst|df[2] } "NODE_NAME" } } { "conv_213.vhd" "" { Text "E:/viterbi213/conv_213.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.69 % ) " "Info: Total cell delay = 1.370 ns ( 46.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.564 ns ( 53.31 % ) " "Info: Total interconnect delay = 1.564 ns ( 53.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.934 ns" { clk conv_213:inst|df[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.934 ns" { clk clk~out0 conv_213:inst|df[2] } { 0.000ns 0.000ns 1.564ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "conv_213.vhd" "" { Text "E:/viterbi213/conv_213.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.650 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.650 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns reset 1 PIN PIN_E20 3 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_E20; Fanout = 3; PIN Node = 'reset'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "ceshi.bdf" "" { Schematic "E:/viterbi213/ceshi.bdf" { { 240 24 192 256 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.193 ns) + CELL(0.223 ns) 4.650 ns conv_213:inst\|df\[2\] 2 REG LC_X1_Y30_N8 3 " "Info: 2: + IC(3.193 ns) + CELL(0.223 ns) = 4.650 ns; Loc. = LC_X1_Y30_N8; Fanout = 3; REG Node = 'conv_213:inst\|df\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.416 ns" { reset conv_213:inst|df[2] } "NODE_NAME" } } { "conv_213.vhd" "" { Text "E:/viterbi213/conv_213.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.457 ns ( 31.33 % ) " "Info: Total cell delay = 1.457 ns ( 31.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.193 ns ( 68.67 % ) " "Info: Total interconnect delay = 3.193 ns ( 68.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.650 ns" { reset conv_213:inst|df[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.650 ns" { reset reset~out0 conv_213:inst|df[2] } { 0.000ns 0.000ns 3.193ns } { 0.000ns 1.234ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.934 ns" { clk conv_213:inst|df[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.934 ns" { clk clk~out0 conv_213:inst|df[2] } { 0.000ns 0.000ns 1.564ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.650 ns" { reset conv_213:inst|df[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.650 ns" { reset reset~out0 conv_213:inst|df[2] } { 0.000ns 0.000ns 3.193ns } { 0.000ns 1.234ns 0.223ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 02 13:12:06 2006 " "Info: Processing ended: Mon Oct 02 13:12:06 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}