📄 dec_copy.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register ACS_0:inst3\|om_0\[0\] register ACS_1:inst4\|acs_1 144.65 MHz 6.913 ns Internal " "Info: Clock \"clk\" has Internal fmax of 144.65 MHz between source register \"ACS_0:inst3\|om_0\[0\]\" and destination register \"ACS_1:inst4\|acs_1\" (period= 6.913 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.652 ns + Longest register register " "Info: + Longest register to register delay is 6.652 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ACS_0:inst3\|om_0\[0\] 1 REG LC_X20_Y13_N1 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y13_N1; Fanout = 7; REG Node = 'ACS_0:inst3\|om_0\[0\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ACS_0:inst3|om_0[0] } "NODE_NAME" } } { "ACS_0.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_0.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.273 ns) + CELL(0.432 ns) 1.705 ns ACS_1:inst4\|Add0~98COUT1_100 2 COMB LC_X19_Y10_N1 2 " "Info: 2: + IC(1.273 ns) + CELL(0.432 ns) = 1.705 ns; Loc. = LC_X19_Y10_N1; Fanout = 2; COMB Node = 'ACS_1:inst4\|Add0~98COUT1_100'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.705 ns" { ACS_0:inst3|om_0[0] ACS_1:inst4|Add0~98COUT1_100 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 2.313 ns ACS_1:inst4\|Add0~95 3 COMB LC_X19_Y10_N2 3 " "Info: 3: + IC(0.000 ns) + CELL(0.608 ns) = 2.313 ns; Loc. = LC_X19_Y10_N2; Fanout = 3; COMB Node = 'ACS_1:inst4\|Add0~95'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.608 ns" { ACS_1:inst4|Add0~98COUT1_100 ACS_1:inst4|Add0~95 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.109 ns) + CELL(0.564 ns) 3.986 ns ACS_1:inst4\|LessThan0~100 4 COMB LC_X20_Y10_N2 1 " "Info: 4: + IC(1.109 ns) + CELL(0.564 ns) = 3.986 ns; Loc. = LC_X20_Y10_N2; Fanout = 1; COMB Node = 'ACS_1:inst4\|LessThan0~100'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.673 ns" { ACS_1:inst4|Add0~95 ACS_1:inst4|LessThan0~100 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 4.064 ns ACS_1:inst4\|LessThan0~95 5 COMB LC_X20_Y10_N3 1 " "Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 4.064 ns; Loc. = LC_X20_Y10_N3; Fanout = 1; COMB Node = 'ACS_1:inst4\|LessThan0~95'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { ACS_1:inst4|LessThan0~100 ACS_1:inst4|LessThan0~95 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 4.242 ns ACS_1:inst4\|LessThan0~90 6 COMB LC_X20_Y10_N4 1 " "Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 4.242 ns; Loc. = LC_X20_Y10_N4; Fanout = 1; COMB Node = 'ACS_1:inst4\|LessThan0~90'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.178 ns" { ACS_1:inst4|LessThan0~95 ACS_1:inst4|LessThan0~90 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 4.863 ns ACS_1:inst4\|LessThan0~78 7 COMB LC_X20_Y10_N6 7 " "Info: 7: + IC(0.000 ns) + CELL(0.621 ns) = 4.863 ns; Loc. = LC_X20_Y10_N6; Fanout = 7; COMB Node = 'ACS_1:inst4\|LessThan0~78'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.621 ns" { ACS_1:inst4|LessThan0~90 ACS_1:inst4|LessThan0~78 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.311 ns) + CELL(0.478 ns) 6.652 ns ACS_1:inst4\|acs_1 8 REG LC_X20_Y13_N9 8 " "Info: 8: + IC(1.311 ns) + CELL(0.478 ns) = 6.652 ns; Loc. = LC_X20_Y13_N9; Fanout = 8; REG Node = 'ACS_1:inst4\|acs_1'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.789 ns" { ACS_1:inst4|LessThan0~78 ACS_1:inst4|acs_1 } "NODE_NAME" } } { "ACS_1.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_1.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.959 ns ( 44.48 % ) " "Info: Total cell delay = 2.959 ns ( 44.48 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.693 ns ( 55.52 % ) " "Info: Total interconnect delay = 3.693 ns ( 55.52 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.652 ns" { ACS_0:inst3|om_0[0] ACS_1:inst4|Add0~98COUT1_100 ACS_1:inst4|Add0~95 ACS_1:inst4|LessThan0~100 ACS_1:inst4|LessThan0~95 ACS_1:inst4|LessThan0~90 ACS_1:inst4|LessThan0~78 ACS_1:inst4|acs_1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.652 ns" { ACS_0:inst3|om_0[0] ACS_1:inst4|Add0~98COUT1_100 ACS_1:inst4|Add0~95 ACS_1:inst4|LessThan0~100 ACS_1:inst4|LessThan0~95 ACS_1:inst4|LessThan0~90 ACS_1:inst4|LessThan0~78 ACS_1:inst4|acs_1 } { 0.000ns 1.273ns 0.000ns 1.109ns 0.000ns 0.000ns 0.000ns 1.311ns } { 0.000ns 0.432ns 0.608ns 0.564ns 0.078ns 0.178ns 0.621ns 0.478ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.782 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 62 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 62; CLK Node = 'clk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dec_copy.bdf" "" { Schematic "E:/My viterbi/viterbi213/dec_copy.bdf" { { 128 232 400 144 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns ACS_1:inst4\|acs_1 2 REG LC_X20_Y13_N9 8 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X20_Y13_N9; Fanout = 8; REG Node = 'ACS_1:inst4\|acs_1'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.313 ns" { clk ACS_1:inst4|acs_1 } "NODE_NAME" } } { "ACS_1.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_1.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk ACS_1:inst4|acs_1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 ACS_1:inst4|acs_1 } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.782 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 62 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 62; CLK Node = 'clk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dec_copy.bdf" "" { Schematic "E:/My viterbi/viterbi213/dec_copy.bdf" { { 128 232 400 144 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns ACS_0:inst3\|om_0\[0\] 2 REG LC_X20_Y13_N1 7 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X20_Y13_N1; Fanout = 7; REG Node = 'ACS_0:inst3\|om_0\[0\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.313 ns" { clk ACS_0:inst3|om_0[0] } "NODE_NAME" } } { "ACS_0.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_0.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk ACS_0:inst3|om_0[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 ACS_0:inst3|om_0[0] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk ACS_1:inst4|acs_1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 ACS_1:inst4|acs_1 } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk ACS_0:inst3|om_0[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 ACS_0:inst3|om_0[0] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "ACS_0.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_0.vhd" 30 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "ACS_1.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_1.vhd" 16 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.652 ns" { ACS_0:inst3|om_0[0] ACS_1:inst4|Add0~98COUT1_100 ACS_1:inst4|Add0~95 ACS_1:inst4|LessThan0~100 ACS_1:inst4|LessThan0~95 ACS_1:inst4|LessThan0~90 ACS_1:inst4|LessThan0~78 ACS_1:inst4|acs_1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.652 ns" { ACS_0:inst3|om_0[0] ACS_1:inst4|Add0~98COUT1_100 ACS_1:inst4|Add0~95 ACS_1:inst4|LessThan0~100 ACS_1:inst4|LessThan0~95 ACS_1:inst4|LessThan0~90 ACS_1:inst4|LessThan0~78 ACS_1:inst4|acs_1 } { 0.000ns 1.273ns 0.000ns 1.109ns 0.000ns 0.000ns 0.000ns 1.311ns } { 0.000ns 0.432ns 0.608ns 0.564ns 0.078ns 0.178ns 0.621ns 0.478ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk ACS_1:inst4|acs_1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 ACS_1:inst4|acs_1 } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk ACS_0:inst3|om_0[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 ACS_0:inst3|om_0[0] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "ACS_2:inst5\|om_2\[0\] inp\[1\] clk 13.067 ns register " "Info: tsu for register \"ACS_2:inst5\|om_2\[0\]\" (data pin = \"inp\[1\]\", clock pin = \"clk\") is 13.067 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.812 ns + Longest pin register " "Info: + Longest pin to register delay is 15.812 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns inp\[1\] 1 PIN PIN_126 5 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_126; Fanout = 5; PIN Node = 'inp\[1\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { inp[1] } "NODE_NAME" } } { "dec_copy.bdf" "" { Schematic "E:/My viterbi/viterbi213/dec_copy.bdf" { { 360 216 384 376 "inp\[1..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.738 ns) + CELL(0.114 ns) 7.327 ns ACS_0:inst3\|mc_2~0 2 COMB LC_X21_Y13_N0 24 " "Info: 2: + IC(5.738 ns) + CELL(0.114 ns) = 7.327 ns; Loc. = LC_X21_Y13_N0; Fanout = 24; COMB Node = 'ACS_0:inst3\|mc_2~0'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.852 ns" { inp[1] ACS_0:inst3|mc_2~0 } "NODE_NAME" } } { "ACS_0.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_0.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.093 ns) + CELL(0.423 ns) 10.843 ns ACS_2:inst5\|Add1~104 3 COMB LC_X18_Y9_N1 2 " "Info: 3: + IC(3.093 ns) + CELL(0.423 ns) = 10.843 ns; Loc. = LC_X18_Y9_N1; Fanout = 2; COMB Node = 'ACS_2:inst5\|Add1~104'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.516 ns" { ACS_0:inst3|mc_2~0 ACS_2:inst5|Add1~104 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 10.921 ns ACS_2:inst5\|Add1~102 4 COMB LC_X18_Y9_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 10.921 ns; Loc. = LC_X18_Y9_N2; Fanout = 2; COMB Node = 'ACS_2:inst5\|Add1~102'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { ACS_2:inst5|Add1~104 ACS_2:inst5|Add1~102 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 10.999 ns ACS_2:inst5\|Add1~100 5 COMB LC_X18_Y9_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 10.999 ns; Loc. = LC_X18_Y9_N3; Fanout = 2; COMB Node = 'ACS_2:inst5\|Add1~100'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { ACS_2:inst5|Add1~102 ACS_2:inst5|Add1~100 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 11.177 ns ACS_2:inst5\|Add1~98 6 COMB LC_X18_Y9_N4 2 " "Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 11.177 ns; Loc. = LC_X18_Y9_N4; Fanout = 2; COMB Node = 'ACS_2:inst5\|Add1~98'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.178 ns" { ACS_2:inst5|Add1~100 ACS_2:inst5|Add1~98 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 11.798 ns ACS_2:inst5\|Add1~95 7 COMB LC_X18_Y9_N5 3 " "Info: 7: + IC(0.000 ns) + CELL(0.621 ns) = 11.798 ns; Loc. = LC_X18_Y9_N5; Fanout = 3; COMB Node = 'ACS_2:inst5\|Add1~95'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.621 ns" { ACS_2:inst5|Add1~98 ACS_2:inst5|Add1~95 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.243 ns) + CELL(0.575 ns) 13.616 ns ACS_2:inst5\|LessThan0~85COUT1_111 8 COMB LC_X19_Y11_N5 1 " "Info: 8: + IC(1.243 ns) + CELL(0.575 ns) = 13.616 ns; Loc. = LC_X19_Y11_N5; Fanout = 1; COMB Node = 'ACS_2:inst5\|LessThan0~85COUT1_111'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.818 ns" { ACS_2:inst5|Add1~95 ACS_2:inst5|LessThan0~85COUT1_111 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.608 ns) 14.224 ns ACS_2:inst5\|LessThan0~78 9 COMB LC_X19_Y11_N6 7 " "Info: 9: + IC(0.000 ns) + CELL(0.608 ns) = 14.224 ns; Loc. = LC_X19_Y11_N6; Fanout = 7; COMB Node = 'ACS_2:inst5\|LessThan0~78'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.608 ns" { ACS_2:inst5|LessThan0~85COUT1_111 ACS_2:inst5|LessThan0~78 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1547 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.279 ns) + CELL(0.309 ns) 15.812 ns ACS_2:inst5\|om_2\[0\] 10 REG LC_X18_Y13_N0 7 " "Info: 10: + IC(1.279 ns) + CELL(0.309 ns) = 15.812 ns; Loc. = LC_X18_Y13_N0; Fanout = 7; REG Node = 'ACS_2:inst5\|om_2\[0\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.588 ns" { ACS_2:inst5|LessThan0~78 ACS_2:inst5|om_2[0] } "NODE_NAME" } } { "ACS_2.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_2.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.459 ns ( 28.20 % ) " "Info: Total cell delay = 4.459 ns ( 28.20 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.353 ns ( 71.80 % ) " "Info: Total interconnect delay = 11.353 ns ( 71.80 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.812 ns" { inp[1] ACS_0:inst3|mc_2~0 ACS_2:inst5|Add1~104 ACS_2:inst5|Add1~102 ACS_2:inst5|Add1~100 ACS_2:inst5|Add1~98 ACS_2:inst5|Add1~95 ACS_2:inst5|LessThan0~85COUT1_111 ACS_2:inst5|LessThan0~78 ACS_2:inst5|om_2[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "15.812 ns" { inp[1] inp[1]~out0 ACS_0:inst3|mc_2~0 ACS_2:inst5|Add1~104 ACS_2:inst5|Add1~102 ACS_2:inst5|Add1~100 ACS_2:inst5|Add1~98 ACS_2:inst5|Add1~95 ACS_2:inst5|LessThan0~85COUT1_111 ACS_2:inst5|LessThan0~78 ACS_2:inst5|om_2[0] } { 0.000ns 0.000ns 5.738ns 3.093ns 0.000ns 0.000ns 0.000ns 0.000ns 1.243ns 0.000ns 1.279ns } { 0.000ns 1.475ns 0.114ns 0.423ns 0.078ns 0.078ns 0.178ns 0.621ns 0.575ns 0.608ns 0.309ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "ACS_2.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_2.vhd" 30 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.782 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 62 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 62; CLK Node = 'clk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dec_copy.bdf" "" { Schematic "E:/My viterbi/viterbi213/dec_copy.bdf" { { 128 232 400 144 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns ACS_2:inst5\|om_2\[0\] 2 REG LC_X18_Y13_N0 7 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X18_Y13_N0; Fanout = 7; REG Node = 'ACS_2:inst5\|om_2\[0\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.313 ns" { clk ACS_2:inst5|om_2[0] } "NODE_NAME" } } { "ACS_2.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_2.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk ACS_2:inst5|om_2[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 ACS_2:inst5|om_2[0] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "15.812 ns" { inp[1] ACS_0:inst3|mc_2~0 ACS_2:inst5|Add1~104 ACS_2:inst5|Add1~102 ACS_2:inst5|Add1~100 ACS_2:inst5|Add1~98 ACS_2:inst5|Add1~95 ACS_2:inst5|LessThan0~85COUT1_111 ACS_2:inst5|LessThan0~78 ACS_2:inst5|om_2[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "15.812 ns" { inp[1] inp[1]~out0 ACS_0:inst3|mc_2~0 ACS_2:inst5|Add1~104 ACS_2:inst5|Add1~102 ACS_2:inst5|Add1~100 ACS_2:inst5|Add1~98 ACS_2:inst5|Add1~95 ACS_2:inst5|LessThan0~85COUT1_111 ACS_2:inst5|LessThan0~78 ACS_2:inst5|om_2[0] } { 0.000ns 0.000ns 5.738ns 3.093ns 0.000ns 0.000ns 0.000ns 0.000ns 1.243ns 0.000ns 1.279ns } { 0.000ns 1.475ns 0.114ns 0.423ns 0.078ns 0.078ns 0.178ns 0.621ns 0.575ns 0.608ns 0.309ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk ACS_2:inst5|om_2[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 ACS_2:inst5|om_2[0] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dec_out reg_exchange:inst\|w3\[9\] 8.594 ns register " "Info: tco from clock \"clk\" to destination pin \"dec_out\" through register \"reg_exchange:inst\|w3\[9\]\" is 8.594 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.782 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 62 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 62; CLK Node = 'clk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dec_copy.bdf" "" { Schematic "E:/My viterbi/viterbi213/dec_copy.bdf" { { 128 232 400 144 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns reg_exchange:inst\|w3\[9\] 2 REG LC_X20_Y11_N8 1 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X20_Y11_N8; Fanout = 1; REG Node = 'reg_exchange:inst\|w3\[9\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.313 ns" { clk reg_exchange:inst|w3[9] } "NODE_NAME" } } { "reg_exchange.vhd" "" { Text "E:/My viterbi/viterbi213/reg_exchange.vhd" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk reg_exchange:inst|w3[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 reg_exchange:inst|w3[9] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "reg_exchange.vhd" "" { Text "E:/My viterbi/viterbi213/reg_exchange.vhd" 40 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.588 ns + Longest register pin " "Info: + Longest register to pin delay is 5.588 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns reg_exchange:inst\|w3\[9\] 1 REG LC_X20_Y11_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y11_N8; Fanout = 1; REG Node = 'reg_exchange:inst\|w3\[9\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reg_exchange:inst|w3[9] } "NODE_NAME" } } { "reg_exchange.vhd" "" { Text "E:/My viterbi/viterbi213/reg_exchange.vhd" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.768 ns) + CELL(0.590 ns) 1.358 ns output_design:inst1\|dec_out~153 2 COMB LC_X19_Y11_N8 1 " "Info: 2: + IC(0.768 ns) + CELL(0.590 ns) = 1.358 ns; Loc. = LC_X19_Y11_N8; Fanout = 1; COMB Node = 'output_design:inst1\|dec_out~153'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.358 ns" { reg_exchange:inst|w3[9] output_design:inst1|dec_out~153 } "NODE_NAME" } } { "output_design.vhd" "" { Text "E:/My viterbi/viterbi213/output_design.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.122 ns) + CELL(2.108 ns) 5.588 ns dec_out 3 PIN PIN_129 0 " "Info: 3: + IC(2.122 ns) + CELL(2.108 ns) = 5.588 ns; Loc. = PIN_129; Fanout = 0; PIN Node = 'dec_out'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.230 ns" { output_design:inst1|dec_out~153 dec_out } "NODE_NAME" } } { "dec_copy.bdf" "" { Schematic "E:/My viterbi/viterbi213/dec_copy.bdf" { { 536 1848 2024 552 "dec_out" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.698 ns ( 48.28 % ) " "Info: Total cell delay = 2.698 ns ( 48.28 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.890 ns ( 51.72 % ) " "Info: Total interconnect delay = 2.890 ns ( 51.72 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.588 ns" { reg_exchange:inst|w3[9] output_design:inst1|dec_out~153 dec_out } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.588 ns" { reg_exchange:inst|w3[9] output_design:inst1|dec_out~153 dec_out } { 0.000ns 0.768ns 2.122ns } { 0.000ns 0.590ns 2.108ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk reg_exchange:inst|w3[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 reg_exchange:inst|w3[9] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.588 ns" { reg_exchange:inst|w3[9] output_design:inst1|dec_out~153 dec_out } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.588 ns" { reg_exchange:inst|w3[9] output_design:inst1|dec_out~153 dec_out } { 0.000ns 0.768ns 2.122ns } { 0.000ns 0.590ns 2.108ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "ACS_2:inst5\|acs_2 reset clk -4.656 ns register " "Info: th for register \"ACS_2:inst5\|acs_2\" (data pin = \"reset\", clock pin = \"clk\") is -4.656 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.782 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 62 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 62; CLK Node = 'clk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dec_copy.bdf" "" { Schematic "E:/My viterbi/viterbi213/dec_copy.bdf" { { 128 232 400 144 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns ACS_2:inst5\|acs_2 2 REG LC_X20_Y13_N8 8 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X20_Y13_N8; Fanout = 8; REG Node = 'ACS_2:inst5\|acs_2'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.313 ns" { clk ACS_2:inst5|acs_2 } "NODE_NAME" } } { "ACS_2.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_2.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk ACS_2:inst5|acs_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 ACS_2:inst5|acs_2 } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" { } { { "ACS_2.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_2.vhd" 16 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.453 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.453 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns reset 1 PIN PIN_125 62 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_125; Fanout = 62; PIN Node = 'reset'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "dec_copy.bdf" "" { Schematic "E:/My viterbi/viterbi213/dec_copy.bdf" { { 144 232 400 160 "reset" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.500 ns) + CELL(0.478 ns) 7.453 ns ACS_2:inst5\|acs_2 2 REG LC_X20_Y13_N8 8 " "Info: 2: + IC(5.500 ns) + CELL(0.478 ns) = 7.453 ns; Loc. = LC_X20_Y13_N8; Fanout = 8; REG Node = 'ACS_2:inst5\|acs_2'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.978 ns" { reset ACS_2:inst5|acs_2 } "NODE_NAME" } } { "ACS_2.vhd" "" { Text "E:/My viterbi/viterbi213/ACS_2.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.953 ns ( 26.20 % ) " "Info: Total cell delay = 1.953 ns ( 26.20 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.500 ns ( 73.80 % ) " "Info: Total interconnect delay = 5.500 ns ( 73.80 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.453 ns" { reset ACS_2:inst5|acs_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.453 ns" { reset reset~out0 ACS_2:inst5|acs_2 } { 0.000ns 0.000ns 5.500ns } { 0.000ns 1.475ns 0.478ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { clk ACS_2:inst5|acs_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { clk clk~out0 ACS_2:inst5|acs_2 } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.453 ns" { reset ACS_2:inst5|acs_2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.453 ns" { reset reset~out0 ACS_2:inst5|acs_2 } { 0.000ns 0.000ns 5.500ns } { 0.000ns 1.475ns 0.478ns } } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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